Ecompass  version1.0
Macros
Peripheral_Registers_Bits_Definition
CMSIS » Stm32l152xe » Exported_constants

Macros

#define ADC_SR_AWD_Pos   (0U)
 
#define ADC_SR_AWD_Msk   (0x1U << ADC_SR_AWD_Pos)
 
#define ADC_SR_AWD   ADC_SR_AWD_Msk
 
#define ADC_SR_EOCS_Pos   (1U)
 
#define ADC_SR_EOCS_Msk   (0x1U << ADC_SR_EOCS_Pos)
 
#define ADC_SR_EOCS   ADC_SR_EOCS_Msk
 
#define ADC_SR_JEOS_Pos   (2U)
 
#define ADC_SR_JEOS_Msk   (0x1U << ADC_SR_JEOS_Pos)
 
#define ADC_SR_JEOS   ADC_SR_JEOS_Msk
 
#define ADC_SR_JSTRT_Pos   (3U)
 
#define ADC_SR_JSTRT_Msk   (0x1U << ADC_SR_JSTRT_Pos)
 
#define ADC_SR_JSTRT   ADC_SR_JSTRT_Msk
 
#define ADC_SR_STRT_Pos   (4U)
 
#define ADC_SR_STRT_Msk   (0x1U << ADC_SR_STRT_Pos)
 
#define ADC_SR_STRT   ADC_SR_STRT_Msk
 
#define ADC_SR_OVR_Pos   (5U)
 
#define ADC_SR_OVR_Msk   (0x1U << ADC_SR_OVR_Pos)
 
#define ADC_SR_OVR   ADC_SR_OVR_Msk
 
#define ADC_SR_ADONS_Pos   (6U)
 
#define ADC_SR_ADONS_Msk   (0x1U << ADC_SR_ADONS_Pos)
 
#define ADC_SR_ADONS   ADC_SR_ADONS_Msk
 
#define ADC_SR_RCNR_Pos   (8U)
 
#define ADC_SR_RCNR_Msk   (0x1U << ADC_SR_RCNR_Pos)
 
#define ADC_SR_RCNR   ADC_SR_RCNR_Msk
 
#define ADC_SR_JCNR_Pos   (9U)
 
#define ADC_SR_JCNR_Msk   (0x1U << ADC_SR_JCNR_Pos)
 
#define ADC_SR_JCNR   ADC_SR_JCNR_Msk
 
#define ADC_SR_EOC   (ADC_SR_EOCS)
 
#define ADC_SR_JEOC   (ADC_SR_JEOS)
 
#define ADC_CR1_AWDCH_Pos   (0U)
 
#define ADC_CR1_AWDCH_Msk   (0x1FU << ADC_CR1_AWDCH_Pos)
 
#define ADC_CR1_AWDCH   ADC_CR1_AWDCH_Msk
 
#define ADC_CR1_AWDCH_0   (0x01U << ADC_CR1_AWDCH_Pos)
 
#define ADC_CR1_AWDCH_1   (0x02U << ADC_CR1_AWDCH_Pos)
 
#define ADC_CR1_AWDCH_2   (0x04U << ADC_CR1_AWDCH_Pos)
 
#define ADC_CR1_AWDCH_3   (0x08U << ADC_CR1_AWDCH_Pos)
 
#define ADC_CR1_AWDCH_4   (0x10U << ADC_CR1_AWDCH_Pos)
 
#define ADC_CR1_EOCSIE_Pos   (5U)
 
#define ADC_CR1_EOCSIE_Msk   (0x1U << ADC_CR1_EOCSIE_Pos)
 
#define ADC_CR1_EOCSIE   ADC_CR1_EOCSIE_Msk
 
#define ADC_CR1_AWDIE_Pos   (6U)
 
#define ADC_CR1_AWDIE_Msk   (0x1U << ADC_CR1_AWDIE_Pos)
 
#define ADC_CR1_AWDIE   ADC_CR1_AWDIE_Msk
 
#define ADC_CR1_JEOSIE_Pos   (7U)
 
#define ADC_CR1_JEOSIE_Msk   (0x1U << ADC_CR1_JEOSIE_Pos)
 
#define ADC_CR1_JEOSIE   ADC_CR1_JEOSIE_Msk
 
#define ADC_CR1_SCAN_Pos   (8U)
 
#define ADC_CR1_SCAN_Msk   (0x1U << ADC_CR1_SCAN_Pos)
 
#define ADC_CR1_SCAN   ADC_CR1_SCAN_Msk
 
#define ADC_CR1_AWDSGL_Pos   (9U)
 
#define ADC_CR1_AWDSGL_Msk   (0x1U << ADC_CR1_AWDSGL_Pos)
 
#define ADC_CR1_AWDSGL   ADC_CR1_AWDSGL_Msk
 
#define ADC_CR1_JAUTO_Pos   (10U)
 
#define ADC_CR1_JAUTO_Msk   (0x1U << ADC_CR1_JAUTO_Pos)
 
#define ADC_CR1_JAUTO   ADC_CR1_JAUTO_Msk
 
#define ADC_CR1_DISCEN_Pos   (11U)
 
#define ADC_CR1_DISCEN_Msk   (0x1U << ADC_CR1_DISCEN_Pos)
 
#define ADC_CR1_DISCEN   ADC_CR1_DISCEN_Msk
 
#define ADC_CR1_JDISCEN_Pos   (12U)
 
#define ADC_CR1_JDISCEN_Msk   (0x1U << ADC_CR1_JDISCEN_Pos)
 
#define ADC_CR1_JDISCEN   ADC_CR1_JDISCEN_Msk
 
#define ADC_CR1_DISCNUM_Pos   (13U)
 
#define ADC_CR1_DISCNUM_Msk   (0x7U << ADC_CR1_DISCNUM_Pos)
 
#define ADC_CR1_DISCNUM   ADC_CR1_DISCNUM_Msk
 
#define ADC_CR1_DISCNUM_0   (0x1U << ADC_CR1_DISCNUM_Pos)
 
#define ADC_CR1_DISCNUM_1   (0x2U << ADC_CR1_DISCNUM_Pos)
 
#define ADC_CR1_DISCNUM_2   (0x4U << ADC_CR1_DISCNUM_Pos)
 
#define ADC_CR1_PDD_Pos   (16U)
 
#define ADC_CR1_PDD_Msk   (0x1U << ADC_CR1_PDD_Pos)
 
#define ADC_CR1_PDD   ADC_CR1_PDD_Msk
 
#define ADC_CR1_PDI_Pos   (17U)
 
#define ADC_CR1_PDI_Msk   (0x1U << ADC_CR1_PDI_Pos)
 
#define ADC_CR1_PDI   ADC_CR1_PDI_Msk
 
#define ADC_CR1_JAWDEN_Pos   (22U)
 
#define ADC_CR1_JAWDEN_Msk   (0x1U << ADC_CR1_JAWDEN_Pos)
 
#define ADC_CR1_JAWDEN   ADC_CR1_JAWDEN_Msk
 
#define ADC_CR1_AWDEN_Pos   (23U)
 
#define ADC_CR1_AWDEN_Msk   (0x1U << ADC_CR1_AWDEN_Pos)
 
#define ADC_CR1_AWDEN   ADC_CR1_AWDEN_Msk
 
#define ADC_CR1_RES_Pos   (24U)
 
#define ADC_CR1_RES_Msk   (0x3U << ADC_CR1_RES_Pos)
 
#define ADC_CR1_RES   ADC_CR1_RES_Msk
 
#define ADC_CR1_RES_0   (0x1U << ADC_CR1_RES_Pos)
 
#define ADC_CR1_RES_1   (0x2U << ADC_CR1_RES_Pos)
 
#define ADC_CR1_OVRIE_Pos   (26U)
 
#define ADC_CR1_OVRIE_Msk   (0x1U << ADC_CR1_OVRIE_Pos)
 
#define ADC_CR1_OVRIE   ADC_CR1_OVRIE_Msk
 
#define ADC_CR1_EOCIE   (ADC_CR1_EOCSIE)
 
#define ADC_CR1_JEOCIE   (ADC_CR1_JEOSIE)
 
#define ADC_CR2_ADON_Pos   (0U)
 
#define ADC_CR2_ADON_Msk   (0x1U << ADC_CR2_ADON_Pos)
 
#define ADC_CR2_ADON   ADC_CR2_ADON_Msk
 
#define ADC_CR2_CONT_Pos   (1U)
 
#define ADC_CR2_CONT_Msk   (0x1U << ADC_CR2_CONT_Pos)
 
#define ADC_CR2_CONT   ADC_CR2_CONT_Msk
 
#define ADC_CR2_CFG_Pos   (2U)
 
#define ADC_CR2_CFG_Msk   (0x1U << ADC_CR2_CFG_Pos)
 
#define ADC_CR2_CFG   ADC_CR2_CFG_Msk
 
#define ADC_CR2_DELS_Pos   (4U)
 
#define ADC_CR2_DELS_Msk   (0x7U << ADC_CR2_DELS_Pos)
 
#define ADC_CR2_DELS   ADC_CR2_DELS_Msk
 
#define ADC_CR2_DELS_0   (0x1U << ADC_CR2_DELS_Pos)
 
#define ADC_CR2_DELS_1   (0x2U << ADC_CR2_DELS_Pos)
 
#define ADC_CR2_DELS_2   (0x4U << ADC_CR2_DELS_Pos)
 
#define ADC_CR2_DMA_Pos   (8U)
 
#define ADC_CR2_DMA_Msk   (0x1U << ADC_CR2_DMA_Pos)
 
#define ADC_CR2_DMA   ADC_CR2_DMA_Msk
 
#define ADC_CR2_DDS_Pos   (9U)
 
#define ADC_CR2_DDS_Msk   (0x1U << ADC_CR2_DDS_Pos)
 
#define ADC_CR2_DDS   ADC_CR2_DDS_Msk
 
#define ADC_CR2_EOCS_Pos   (10U)
 
#define ADC_CR2_EOCS_Msk   (0x1U << ADC_CR2_EOCS_Pos)
 
#define ADC_CR2_EOCS   ADC_CR2_EOCS_Msk
 
#define ADC_CR2_ALIGN_Pos   (11U)
 
#define ADC_CR2_ALIGN_Msk   (0x1U << ADC_CR2_ALIGN_Pos)
 
#define ADC_CR2_ALIGN   ADC_CR2_ALIGN_Msk
 
#define ADC_CR2_JEXTSEL_Pos   (16U)
 
#define ADC_CR2_JEXTSEL_Msk   (0xFU << ADC_CR2_JEXTSEL_Pos)
 
#define ADC_CR2_JEXTSEL   ADC_CR2_JEXTSEL_Msk
 
#define ADC_CR2_JEXTSEL_0   (0x1U << ADC_CR2_JEXTSEL_Pos)
 
#define ADC_CR2_JEXTSEL_1   (0x2U << ADC_CR2_JEXTSEL_Pos)
 
#define ADC_CR2_JEXTSEL_2   (0x4U << ADC_CR2_JEXTSEL_Pos)
 
#define ADC_CR2_JEXTSEL_3   (0x8U << ADC_CR2_JEXTSEL_Pos)
 
#define ADC_CR2_JEXTEN_Pos   (20U)
 
#define ADC_CR2_JEXTEN_Msk   (0x3U << ADC_CR2_JEXTEN_Pos)
 
#define ADC_CR2_JEXTEN   ADC_CR2_JEXTEN_Msk
 
#define ADC_CR2_JEXTEN_0   (0x1U << ADC_CR2_JEXTEN_Pos)
 
#define ADC_CR2_JEXTEN_1   (0x2U << ADC_CR2_JEXTEN_Pos)
 
#define ADC_CR2_JSWSTART_Pos   (22U)
 
#define ADC_CR2_JSWSTART_Msk   (0x1U << ADC_CR2_JSWSTART_Pos)
 
#define ADC_CR2_JSWSTART   ADC_CR2_JSWSTART_Msk
 
#define ADC_CR2_EXTSEL_Pos   (24U)
 
#define ADC_CR2_EXTSEL_Msk   (0xFU << ADC_CR2_EXTSEL_Pos)
 
#define ADC_CR2_EXTSEL   ADC_CR2_EXTSEL_Msk
 
#define ADC_CR2_EXTSEL_0   (0x1U << ADC_CR2_EXTSEL_Pos)
 
#define ADC_CR2_EXTSEL_1   (0x2U << ADC_CR2_EXTSEL_Pos)
 
#define ADC_CR2_EXTSEL_2   (0x4U << ADC_CR2_EXTSEL_Pos)
 
#define ADC_CR2_EXTSEL_3   (0x8U << ADC_CR2_EXTSEL_Pos)
 
#define ADC_CR2_EXTEN_Pos   (28U)
 
#define ADC_CR2_EXTEN_Msk   (0x3U << ADC_CR2_EXTEN_Pos)
 
#define ADC_CR2_EXTEN   ADC_CR2_EXTEN_Msk
 
#define ADC_CR2_EXTEN_0   (0x1U << ADC_CR2_EXTEN_Pos)
 
#define ADC_CR2_EXTEN_1   (0x2U << ADC_CR2_EXTEN_Pos)
 
#define ADC_CR2_SWSTART_Pos   (30U)
 
#define ADC_CR2_SWSTART_Msk   (0x1U << ADC_CR2_SWSTART_Pos)
 
#define ADC_CR2_SWSTART   ADC_CR2_SWSTART_Msk
 
#define ADC_SMPR1_SMP20_Pos   (0U)
 
#define ADC_SMPR1_SMP20_Msk   (0x7U << ADC_SMPR1_SMP20_Pos)
 
#define ADC_SMPR1_SMP20   ADC_SMPR1_SMP20_Msk
 
#define ADC_SMPR1_SMP20_0   (0x1U << ADC_SMPR1_SMP20_Pos)
 
#define ADC_SMPR1_SMP20_1   (0x2U << ADC_SMPR1_SMP20_Pos)
 
#define ADC_SMPR1_SMP20_2   (0x4U << ADC_SMPR1_SMP20_Pos)
 
#define ADC_SMPR1_SMP21_Pos   (3U)
 
#define ADC_SMPR1_SMP21_Msk   (0x7U << ADC_SMPR1_SMP21_Pos)
 
#define ADC_SMPR1_SMP21   ADC_SMPR1_SMP21_Msk
 
#define ADC_SMPR1_SMP21_0   (0x1U << ADC_SMPR1_SMP21_Pos)
 
#define ADC_SMPR1_SMP21_1   (0x2U << ADC_SMPR1_SMP21_Pos)
 
#define ADC_SMPR1_SMP21_2   (0x4U << ADC_SMPR1_SMP21_Pos)
 
#define ADC_SMPR1_SMP22_Pos   (6U)
 
#define ADC_SMPR1_SMP22_Msk   (0x7U << ADC_SMPR1_SMP22_Pos)
 
#define ADC_SMPR1_SMP22   ADC_SMPR1_SMP22_Msk
 
#define ADC_SMPR1_SMP22_0   (0x1U << ADC_SMPR1_SMP22_Pos)
 
#define ADC_SMPR1_SMP22_1   (0x2U << ADC_SMPR1_SMP22_Pos)
 
#define ADC_SMPR1_SMP22_2   (0x4U << ADC_SMPR1_SMP22_Pos)
 
#define ADC_SMPR1_SMP23_Pos   (9U)
 
#define ADC_SMPR1_SMP23_Msk   (0x7U << ADC_SMPR1_SMP23_Pos)
 
#define ADC_SMPR1_SMP23   ADC_SMPR1_SMP23_Msk
 
#define ADC_SMPR1_SMP23_0   (0x1U << ADC_SMPR1_SMP23_Pos)
 
#define ADC_SMPR1_SMP23_1   (0x2U << ADC_SMPR1_SMP23_Pos)
 
#define ADC_SMPR1_SMP23_2   (0x4U << ADC_SMPR1_SMP23_Pos)
 
#define ADC_SMPR1_SMP24_Pos   (12U)
 
#define ADC_SMPR1_SMP24_Msk   (0x7U << ADC_SMPR1_SMP24_Pos)
 
#define ADC_SMPR1_SMP24   ADC_SMPR1_SMP24_Msk
 
#define ADC_SMPR1_SMP24_0   (0x1U << ADC_SMPR1_SMP24_Pos)
 
#define ADC_SMPR1_SMP24_1   (0x2U << ADC_SMPR1_SMP24_Pos)
 
#define ADC_SMPR1_SMP24_2   (0x4U << ADC_SMPR1_SMP24_Pos)
 
#define ADC_SMPR1_SMP25_Pos   (15U)
 
#define ADC_SMPR1_SMP25_Msk   (0x7U << ADC_SMPR1_SMP25_Pos)
 
#define ADC_SMPR1_SMP25   ADC_SMPR1_SMP25_Msk
 
#define ADC_SMPR1_SMP25_0   (0x1U << ADC_SMPR1_SMP25_Pos)
 
#define ADC_SMPR1_SMP25_1   (0x2U << ADC_SMPR1_SMP25_Pos)
 
#define ADC_SMPR1_SMP25_2   (0x4U << ADC_SMPR1_SMP25_Pos)
 
#define ADC_SMPR1_SMP26_Pos   (18U)
 
#define ADC_SMPR1_SMP26_Msk   (0x7U << ADC_SMPR1_SMP26_Pos)
 
#define ADC_SMPR1_SMP26   ADC_SMPR1_SMP26_Msk
 
#define ADC_SMPR1_SMP26_0   (0x1U << ADC_SMPR1_SMP26_Pos)
 
#define ADC_SMPR1_SMP26_1   (0x2U << ADC_SMPR1_SMP26_Pos)
 
#define ADC_SMPR1_SMP26_2   (0x4U << ADC_SMPR1_SMP26_Pos)
 
#define ADC_SMPR1_SMP27_Pos   (21U)
 
#define ADC_SMPR1_SMP27_Msk   (0x7U << ADC_SMPR1_SMP27_Pos)
 
#define ADC_SMPR1_SMP27   ADC_SMPR1_SMP27_Msk
 
#define ADC_SMPR1_SMP27_0   (0x1U << ADC_SMPR1_SMP27_Pos)
 
#define ADC_SMPR1_SMP27_1   (0x2U << ADC_SMPR1_SMP27_Pos)
 
#define ADC_SMPR1_SMP27_2   (0x4U << ADC_SMPR1_SMP27_Pos)
 
#define ADC_SMPR1_SMP28_Pos   (24U)
 
#define ADC_SMPR1_SMP28_Msk   (0x7U << ADC_SMPR1_SMP28_Pos)
 
#define ADC_SMPR1_SMP28   ADC_SMPR1_SMP28_Msk
 
#define ADC_SMPR1_SMP28_0   (0x1U << ADC_SMPR1_SMP28_Pos)
 
#define ADC_SMPR1_SMP28_1   (0x2U << ADC_SMPR1_SMP28_Pos)
 
#define ADC_SMPR1_SMP28_2   (0x4U << ADC_SMPR1_SMP28_Pos)
 
#define ADC_SMPR1_SMP29_Pos   (27U)
 
#define ADC_SMPR1_SMP29_Msk   (0x7U << ADC_SMPR1_SMP29_Pos)
 
#define ADC_SMPR1_SMP29   ADC_SMPR1_SMP29_Msk
 
#define ADC_SMPR1_SMP29_0   (0x1U << ADC_SMPR1_SMP29_Pos)
 
#define ADC_SMPR1_SMP29_1   (0x2U << ADC_SMPR1_SMP29_Pos)
 
#define ADC_SMPR1_SMP29_2   (0x4U << ADC_SMPR1_SMP29_Pos)
 
#define ADC_SMPR2_SMP10_Pos   (0U)
 
#define ADC_SMPR2_SMP10_Msk   (0x7U << ADC_SMPR2_SMP10_Pos)
 
#define ADC_SMPR2_SMP10   ADC_SMPR2_SMP10_Msk
 
#define ADC_SMPR2_SMP10_0   (0x1U << ADC_SMPR2_SMP10_Pos)
 
#define ADC_SMPR2_SMP10_1   (0x2U << ADC_SMPR2_SMP10_Pos)
 
#define ADC_SMPR2_SMP10_2   (0x4U << ADC_SMPR2_SMP10_Pos)
 
#define ADC_SMPR2_SMP11_Pos   (3U)
 
#define ADC_SMPR2_SMP11_Msk   (0x7U << ADC_SMPR2_SMP11_Pos)
 
#define ADC_SMPR2_SMP11   ADC_SMPR2_SMP11_Msk
 
#define ADC_SMPR2_SMP11_0   (0x1U << ADC_SMPR2_SMP11_Pos)
 
#define ADC_SMPR2_SMP11_1   (0x2U << ADC_SMPR2_SMP11_Pos)
 
#define ADC_SMPR2_SMP11_2   (0x4U << ADC_SMPR2_SMP11_Pos)
 
#define ADC_SMPR2_SMP12_Pos   (6U)
 
#define ADC_SMPR2_SMP12_Msk   (0x7U << ADC_SMPR2_SMP12_Pos)
 
#define ADC_SMPR2_SMP12   ADC_SMPR2_SMP12_Msk
 
#define ADC_SMPR2_SMP12_0   (0x1U << ADC_SMPR2_SMP12_Pos)
 
#define ADC_SMPR2_SMP12_1   (0x2U << ADC_SMPR2_SMP12_Pos)
 
#define ADC_SMPR2_SMP12_2   (0x4U << ADC_SMPR2_SMP12_Pos)
 
#define ADC_SMPR2_SMP13_Pos   (9U)
 
#define ADC_SMPR2_SMP13_Msk   (0x7U << ADC_SMPR2_SMP13_Pos)
 
#define ADC_SMPR2_SMP13   ADC_SMPR2_SMP13_Msk
 
#define ADC_SMPR2_SMP13_0   (0x1U << ADC_SMPR2_SMP13_Pos)
 
#define ADC_SMPR2_SMP13_1   (0x2U << ADC_SMPR2_SMP13_Pos)
 
#define ADC_SMPR2_SMP13_2   (0x4U << ADC_SMPR2_SMP13_Pos)
 
#define ADC_SMPR2_SMP14_Pos   (12U)
 
#define ADC_SMPR2_SMP14_Msk   (0x7U << ADC_SMPR2_SMP14_Pos)
 
#define ADC_SMPR2_SMP14   ADC_SMPR2_SMP14_Msk
 
#define ADC_SMPR2_SMP14_0   (0x1U << ADC_SMPR2_SMP14_Pos)
 
#define ADC_SMPR2_SMP14_1   (0x2U << ADC_SMPR2_SMP14_Pos)
 
#define ADC_SMPR2_SMP14_2   (0x4U << ADC_SMPR2_SMP14_Pos)
 
#define ADC_SMPR2_SMP15_Pos   (15U)
 
#define ADC_SMPR2_SMP15_Msk   (0x7U << ADC_SMPR2_SMP15_Pos)
 
#define ADC_SMPR2_SMP15   ADC_SMPR2_SMP15_Msk
 
#define ADC_SMPR2_SMP15_0   (0x1U << ADC_SMPR2_SMP15_Pos)
 
#define ADC_SMPR2_SMP15_1   (0x2U << ADC_SMPR2_SMP15_Pos)
 
#define ADC_SMPR2_SMP15_2   (0x4U << ADC_SMPR2_SMP15_Pos)
 
#define ADC_SMPR2_SMP16_Pos   (18U)
 
#define ADC_SMPR2_SMP16_Msk   (0x7U << ADC_SMPR2_SMP16_Pos)
 
#define ADC_SMPR2_SMP16   ADC_SMPR2_SMP16_Msk
 
#define ADC_SMPR2_SMP16_0   (0x1U << ADC_SMPR2_SMP16_Pos)
 
#define ADC_SMPR2_SMP16_1   (0x2U << ADC_SMPR2_SMP16_Pos)
 
#define ADC_SMPR2_SMP16_2   (0x4U << ADC_SMPR2_SMP16_Pos)
 
#define ADC_SMPR2_SMP17_Pos   (21U)
 
#define ADC_SMPR2_SMP17_Msk   (0x7U << ADC_SMPR2_SMP17_Pos)
 
#define ADC_SMPR2_SMP17   ADC_SMPR2_SMP17_Msk
 
#define ADC_SMPR2_SMP17_0   (0x1U << ADC_SMPR2_SMP17_Pos)
 
#define ADC_SMPR2_SMP17_1   (0x2U << ADC_SMPR2_SMP17_Pos)
 
#define ADC_SMPR2_SMP17_2   (0x4U << ADC_SMPR2_SMP17_Pos)
 
#define ADC_SMPR2_SMP18_Pos   (24U)
 
#define ADC_SMPR2_SMP18_Msk   (0x7U << ADC_SMPR2_SMP18_Pos)
 
#define ADC_SMPR2_SMP18   ADC_SMPR2_SMP18_Msk
 
#define ADC_SMPR2_SMP18_0   (0x1U << ADC_SMPR2_SMP18_Pos)
 
#define ADC_SMPR2_SMP18_1   (0x2U << ADC_SMPR2_SMP18_Pos)
 
#define ADC_SMPR2_SMP18_2   (0x4U << ADC_SMPR2_SMP18_Pos)
 
#define ADC_SMPR2_SMP19_Pos   (27U)
 
#define ADC_SMPR2_SMP19_Msk   (0x7U << ADC_SMPR2_SMP19_Pos)
 
#define ADC_SMPR2_SMP19   ADC_SMPR2_SMP19_Msk
 
#define ADC_SMPR2_SMP19_0   (0x1U << ADC_SMPR2_SMP19_Pos)
 
#define ADC_SMPR2_SMP19_1   (0x2U << ADC_SMPR2_SMP19_Pos)
 
#define ADC_SMPR2_SMP19_2   (0x4U << ADC_SMPR2_SMP19_Pos)
 
#define ADC_SMPR3_SMP0_Pos   (0U)
 
#define ADC_SMPR3_SMP0_Msk   (0x7U << ADC_SMPR3_SMP0_Pos)
 
#define ADC_SMPR3_SMP0   ADC_SMPR3_SMP0_Msk
 
#define ADC_SMPR3_SMP0_0   (0x1U << ADC_SMPR3_SMP0_Pos)
 
#define ADC_SMPR3_SMP0_1   (0x2U << ADC_SMPR3_SMP0_Pos)
 
#define ADC_SMPR3_SMP0_2   (0x4U << ADC_SMPR3_SMP0_Pos)
 
#define ADC_SMPR3_SMP1_Pos   (3U)
 
#define ADC_SMPR3_SMP1_Msk   (0x7U << ADC_SMPR3_SMP1_Pos)
 
#define ADC_SMPR3_SMP1   ADC_SMPR3_SMP1_Msk
 
#define ADC_SMPR3_SMP1_0   (0x1U << ADC_SMPR3_SMP1_Pos)
 
#define ADC_SMPR3_SMP1_1   (0x2U << ADC_SMPR3_SMP1_Pos)
 
#define ADC_SMPR3_SMP1_2   (0x4U << ADC_SMPR3_SMP1_Pos)
 
#define ADC_SMPR3_SMP2_Pos   (6U)
 
#define ADC_SMPR3_SMP2_Msk   (0x7U << ADC_SMPR3_SMP2_Pos)
 
#define ADC_SMPR3_SMP2   ADC_SMPR3_SMP2_Msk
 
#define ADC_SMPR3_SMP2_0   (0x1U << ADC_SMPR3_SMP2_Pos)
 
#define ADC_SMPR3_SMP2_1   (0x2U << ADC_SMPR3_SMP2_Pos)
 
#define ADC_SMPR3_SMP2_2   (0x4U << ADC_SMPR3_SMP2_Pos)
 
#define ADC_SMPR3_SMP3_Pos   (9U)
 
#define ADC_SMPR3_SMP3_Msk   (0x7U << ADC_SMPR3_SMP3_Pos)
 
#define ADC_SMPR3_SMP3   ADC_SMPR3_SMP3_Msk
 
#define ADC_SMPR3_SMP3_0   (0x1U << ADC_SMPR3_SMP3_Pos)
 
#define ADC_SMPR3_SMP3_1   (0x2U << ADC_SMPR3_SMP3_Pos)
 
#define ADC_SMPR3_SMP3_2   (0x4U << ADC_SMPR3_SMP3_Pos)
 
#define ADC_SMPR3_SMP4_Pos   (12U)
 
#define ADC_SMPR3_SMP4_Msk   (0x7U << ADC_SMPR3_SMP4_Pos)
 
#define ADC_SMPR3_SMP4   ADC_SMPR3_SMP4_Msk
 
#define ADC_SMPR3_SMP4_0   (0x1U << ADC_SMPR3_SMP4_Pos)
 
#define ADC_SMPR3_SMP4_1   (0x2U << ADC_SMPR3_SMP4_Pos)
 
#define ADC_SMPR3_SMP4_2   (0x4U << ADC_SMPR3_SMP4_Pos)
 
#define ADC_SMPR3_SMP5_Pos   (15U)
 
#define ADC_SMPR3_SMP5_Msk   (0x7U << ADC_SMPR3_SMP5_Pos)
 
#define ADC_SMPR3_SMP5   ADC_SMPR3_SMP5_Msk
 
#define ADC_SMPR3_SMP5_0   (0x1U << ADC_SMPR3_SMP5_Pos)
 
#define ADC_SMPR3_SMP5_1   (0x2U << ADC_SMPR3_SMP5_Pos)
 
#define ADC_SMPR3_SMP5_2   (0x4U << ADC_SMPR3_SMP5_Pos)
 
#define ADC_SMPR3_SMP6_Pos   (18U)
 
#define ADC_SMPR3_SMP6_Msk   (0x7U << ADC_SMPR3_SMP6_Pos)
 
#define ADC_SMPR3_SMP6   ADC_SMPR3_SMP6_Msk
 
#define ADC_SMPR3_SMP6_0   (0x1U << ADC_SMPR3_SMP6_Pos)
 
#define ADC_SMPR3_SMP6_1   (0x2U << ADC_SMPR3_SMP6_Pos)
 
#define ADC_SMPR3_SMP6_2   (0x4U << ADC_SMPR3_SMP6_Pos)
 
#define ADC_SMPR3_SMP7_Pos   (21U)
 
#define ADC_SMPR3_SMP7_Msk   (0x7U << ADC_SMPR3_SMP7_Pos)
 
#define ADC_SMPR3_SMP7   ADC_SMPR3_SMP7_Msk
 
#define ADC_SMPR3_SMP7_0   (0x1U << ADC_SMPR3_SMP7_Pos)
 
#define ADC_SMPR3_SMP7_1   (0x2U << ADC_SMPR3_SMP7_Pos)
 
#define ADC_SMPR3_SMP7_2   (0x4U << ADC_SMPR3_SMP7_Pos)
 
#define ADC_SMPR3_SMP8_Pos   (24U)
 
#define ADC_SMPR3_SMP8_Msk   (0x7U << ADC_SMPR3_SMP8_Pos)
 
#define ADC_SMPR3_SMP8   ADC_SMPR3_SMP8_Msk
 
#define ADC_SMPR3_SMP8_0   (0x1U << ADC_SMPR3_SMP8_Pos)
 
#define ADC_SMPR3_SMP8_1   (0x2U << ADC_SMPR3_SMP8_Pos)
 
#define ADC_SMPR3_SMP8_2   (0x4U << ADC_SMPR3_SMP8_Pos)
 
#define ADC_SMPR3_SMP9_Pos   (27U)
 
#define ADC_SMPR3_SMP9_Msk   (0x7U << ADC_SMPR3_SMP9_Pos)
 
#define ADC_SMPR3_SMP9   ADC_SMPR3_SMP9_Msk
 
#define ADC_SMPR3_SMP9_0   (0x1U << ADC_SMPR3_SMP9_Pos)
 
#define ADC_SMPR3_SMP9_1   (0x2U << ADC_SMPR3_SMP9_Pos)
 
#define ADC_SMPR3_SMP9_2   (0x4U << ADC_SMPR3_SMP9_Pos)
 
#define ADC_JOFR1_JOFFSET1_Pos   (0U)
 
#define ADC_JOFR1_JOFFSET1_Msk   (0xFFFU << ADC_JOFR1_JOFFSET1_Pos)
 
#define ADC_JOFR1_JOFFSET1   ADC_JOFR1_JOFFSET1_Msk
 
#define ADC_JOFR2_JOFFSET2_Pos   (0U)
 
#define ADC_JOFR2_JOFFSET2_Msk   (0xFFFU << ADC_JOFR2_JOFFSET2_Pos)
 
#define ADC_JOFR2_JOFFSET2   ADC_JOFR2_JOFFSET2_Msk
 
#define ADC_JOFR3_JOFFSET3_Pos   (0U)
 
#define ADC_JOFR3_JOFFSET3_Msk   (0xFFFU << ADC_JOFR3_JOFFSET3_Pos)
 
#define ADC_JOFR3_JOFFSET3   ADC_JOFR3_JOFFSET3_Msk
 
#define ADC_JOFR4_JOFFSET4_Pos   (0U)
 
#define ADC_JOFR4_JOFFSET4_Msk   (0xFFFU << ADC_JOFR4_JOFFSET4_Pos)
 
#define ADC_JOFR4_JOFFSET4   ADC_JOFR4_JOFFSET4_Msk
 
#define ADC_HTR_HT_Pos   (0U)
 
#define ADC_HTR_HT_Msk   (0xFFFU << ADC_HTR_HT_Pos)
 
#define ADC_HTR_HT   ADC_HTR_HT_Msk
 
#define ADC_LTR_LT_Pos   (0U)
 
#define ADC_LTR_LT_Msk   (0xFFFU << ADC_LTR_LT_Pos)
 
#define ADC_LTR_LT   ADC_LTR_LT_Msk
 
#define ADC_SQR1_L_Pos   (20U)
 
#define ADC_SQR1_L_Msk   (0x1FU << ADC_SQR1_L_Pos)
 
#define ADC_SQR1_L   ADC_SQR1_L_Msk
 
#define ADC_SQR1_L_0   (0x01U << ADC_SQR1_L_Pos)
 
#define ADC_SQR1_L_1   (0x02U << ADC_SQR1_L_Pos)
 
#define ADC_SQR1_L_2   (0x04U << ADC_SQR1_L_Pos)
 
#define ADC_SQR1_L_3   (0x08U << ADC_SQR1_L_Pos)
 
#define ADC_SQR1_L_4   (0x10U << ADC_SQR1_L_Pos)
 
#define ADC_SQR1_SQ28_Pos   (15U)
 
#define ADC_SQR1_SQ28_Msk   (0x1FU << ADC_SQR1_SQ28_Pos)
 
#define ADC_SQR1_SQ28   ADC_SQR1_SQ28_Msk
 
#define ADC_SQR1_SQ28_0   (0x01U << ADC_SQR1_SQ28_Pos)
 
#define ADC_SQR1_SQ28_1   (0x02U << ADC_SQR1_SQ28_Pos)
 
#define ADC_SQR1_SQ28_2   (0x04U << ADC_SQR1_SQ28_Pos)
 
#define ADC_SQR1_SQ28_3   (0x08U << ADC_SQR1_SQ28_Pos)
 
#define ADC_SQR1_SQ28_4   (0x10U << ADC_SQR1_SQ28_Pos)
 
#define ADC_SQR1_SQ27_Pos   (10U)
 
#define ADC_SQR1_SQ27_Msk   (0x1FU << ADC_SQR1_SQ27_Pos)
 
#define ADC_SQR1_SQ27   ADC_SQR1_SQ27_Msk
 
#define ADC_SQR1_SQ27_0   (0x01U << ADC_SQR1_SQ27_Pos)
 
#define ADC_SQR1_SQ27_1   (0x02U << ADC_SQR1_SQ27_Pos)
 
#define ADC_SQR1_SQ27_2   (0x04U << ADC_SQR1_SQ27_Pos)
 
#define ADC_SQR1_SQ27_3   (0x08U << ADC_SQR1_SQ27_Pos)
 
#define ADC_SQR1_SQ27_4   (0x10U << ADC_SQR1_SQ27_Pos)
 
#define ADC_SQR1_SQ26_Pos   (5U)
 
#define ADC_SQR1_SQ26_Msk   (0x1FU << ADC_SQR1_SQ26_Pos)
 
#define ADC_SQR1_SQ26   ADC_SQR1_SQ26_Msk
 
#define ADC_SQR1_SQ26_0   (0x01U << ADC_SQR1_SQ26_Pos)
 
#define ADC_SQR1_SQ26_1   (0x02U << ADC_SQR1_SQ26_Pos)
 
#define ADC_SQR1_SQ26_2   (0x04U << ADC_SQR1_SQ26_Pos)
 
#define ADC_SQR1_SQ26_3   (0x08U << ADC_SQR1_SQ26_Pos)
 
#define ADC_SQR1_SQ26_4   (0x10U << ADC_SQR1_SQ26_Pos)
 
#define ADC_SQR1_SQ25_Pos   (0U)
 
#define ADC_SQR1_SQ25_Msk   (0x1FU << ADC_SQR1_SQ25_Pos)
 
#define ADC_SQR1_SQ25   ADC_SQR1_SQ25_Msk
 
#define ADC_SQR1_SQ25_0   (0x01U << ADC_SQR1_SQ25_Pos)
 
#define ADC_SQR1_SQ25_1   (0x02U << ADC_SQR1_SQ25_Pos)
 
#define ADC_SQR1_SQ25_2   (0x04U << ADC_SQR1_SQ25_Pos)
 
#define ADC_SQR1_SQ25_3   (0x08U << ADC_SQR1_SQ25_Pos)
 
#define ADC_SQR1_SQ25_4   (0x10U << ADC_SQR1_SQ25_Pos)
 
#define ADC_SQR2_SQ19_Pos   (0U)
 
#define ADC_SQR2_SQ19_Msk   (0x1FU << ADC_SQR2_SQ19_Pos)
 
#define ADC_SQR2_SQ19   ADC_SQR2_SQ19_Msk
 
#define ADC_SQR2_SQ19_0   (0x01U << ADC_SQR2_SQ19_Pos)
 
#define ADC_SQR2_SQ19_1   (0x02U << ADC_SQR2_SQ19_Pos)
 
#define ADC_SQR2_SQ19_2   (0x04U << ADC_SQR2_SQ19_Pos)
 
#define ADC_SQR2_SQ19_3   (0x08U << ADC_SQR2_SQ19_Pos)
 
#define ADC_SQR2_SQ19_4   (0x10U << ADC_SQR2_SQ19_Pos)
 
#define ADC_SQR2_SQ20_Pos   (5U)
 
#define ADC_SQR2_SQ20_Msk   (0x1FU << ADC_SQR2_SQ20_Pos)
 
#define ADC_SQR2_SQ20   ADC_SQR2_SQ20_Msk
 
#define ADC_SQR2_SQ20_0   (0x01U << ADC_SQR2_SQ20_Pos)
 
#define ADC_SQR2_SQ20_1   (0x02U << ADC_SQR2_SQ20_Pos)
 
#define ADC_SQR2_SQ20_2   (0x04U << ADC_SQR2_SQ20_Pos)
 
#define ADC_SQR2_SQ20_3   (0x08U << ADC_SQR2_SQ20_Pos)
 
#define ADC_SQR2_SQ20_4   (0x10U << ADC_SQR2_SQ20_Pos)
 
#define ADC_SQR2_SQ21_Pos   (10U)
 
#define ADC_SQR2_SQ21_Msk   (0x1FU << ADC_SQR2_SQ21_Pos)
 
#define ADC_SQR2_SQ21   ADC_SQR2_SQ21_Msk
 
#define ADC_SQR2_SQ21_0   (0x01U << ADC_SQR2_SQ21_Pos)
 
#define ADC_SQR2_SQ21_1   (0x02U << ADC_SQR2_SQ21_Pos)
 
#define ADC_SQR2_SQ21_2   (0x04U << ADC_SQR2_SQ21_Pos)
 
#define ADC_SQR2_SQ21_3   (0x08U << ADC_SQR2_SQ21_Pos)
 
#define ADC_SQR2_SQ21_4   (0x10U << ADC_SQR2_SQ21_Pos)
 
#define ADC_SQR2_SQ22_Pos   (15U)
 
#define ADC_SQR2_SQ22_Msk   (0x1FU << ADC_SQR2_SQ22_Pos)
 
#define ADC_SQR2_SQ22   ADC_SQR2_SQ22_Msk
 
#define ADC_SQR2_SQ22_0   (0x01U << ADC_SQR2_SQ22_Pos)
 
#define ADC_SQR2_SQ22_1   (0x02U << ADC_SQR2_SQ22_Pos)
 
#define ADC_SQR2_SQ22_2   (0x04U << ADC_SQR2_SQ22_Pos)
 
#define ADC_SQR2_SQ22_3   (0x08U << ADC_SQR2_SQ22_Pos)
 
#define ADC_SQR2_SQ22_4   (0x10U << ADC_SQR2_SQ22_Pos)
 
#define ADC_SQR2_SQ23_Pos   (20U)
 
#define ADC_SQR2_SQ23_Msk   (0x1FU << ADC_SQR2_SQ23_Pos)
 
#define ADC_SQR2_SQ23   ADC_SQR2_SQ23_Msk
 
#define ADC_SQR2_SQ23_0   (0x01U << ADC_SQR2_SQ23_Pos)
 
#define ADC_SQR2_SQ23_1   (0x02U << ADC_SQR2_SQ23_Pos)
 
#define ADC_SQR2_SQ23_2   (0x04U << ADC_SQR2_SQ23_Pos)
 
#define ADC_SQR2_SQ23_3   (0x08U << ADC_SQR2_SQ23_Pos)
 
#define ADC_SQR2_SQ23_4   (0x10U << ADC_SQR2_SQ23_Pos)
 
#define ADC_SQR2_SQ24_Pos   (25U)
 
#define ADC_SQR2_SQ24_Msk   (0x1FU << ADC_SQR2_SQ24_Pos)
 
#define ADC_SQR2_SQ24   ADC_SQR2_SQ24_Msk
 
#define ADC_SQR2_SQ24_0   (0x01U << ADC_SQR2_SQ24_Pos)
 
#define ADC_SQR2_SQ24_1   (0x02U << ADC_SQR2_SQ24_Pos)
 
#define ADC_SQR2_SQ24_2   (0x04U << ADC_SQR2_SQ24_Pos)
 
#define ADC_SQR2_SQ24_3   (0x08U << ADC_SQR2_SQ24_Pos)
 
#define ADC_SQR2_SQ24_4   (0x10U << ADC_SQR2_SQ24_Pos)
 
#define ADC_SQR3_SQ13_Pos   (0U)
 
#define ADC_SQR3_SQ13_Msk   (0x1FU << ADC_SQR3_SQ13_Pos)
 
#define ADC_SQR3_SQ13   ADC_SQR3_SQ13_Msk
 
#define ADC_SQR3_SQ13_0   (0x01U << ADC_SQR3_SQ13_Pos)
 
#define ADC_SQR3_SQ13_1   (0x02U << ADC_SQR3_SQ13_Pos)
 
#define ADC_SQR3_SQ13_2   (0x04U << ADC_SQR3_SQ13_Pos)
 
#define ADC_SQR3_SQ13_3   (0x08U << ADC_SQR3_SQ13_Pos)
 
#define ADC_SQR3_SQ13_4   (0x10U << ADC_SQR3_SQ13_Pos)
 
#define ADC_SQR3_SQ14_Pos   (5U)
 
#define ADC_SQR3_SQ14_Msk   (0x1FU << ADC_SQR3_SQ14_Pos)
 
#define ADC_SQR3_SQ14   ADC_SQR3_SQ14_Msk
 
#define ADC_SQR3_SQ14_0   (0x01U << ADC_SQR3_SQ14_Pos)
 
#define ADC_SQR3_SQ14_1   (0x02U << ADC_SQR3_SQ14_Pos)
 
#define ADC_SQR3_SQ14_2   (0x04U << ADC_SQR3_SQ14_Pos)
 
#define ADC_SQR3_SQ14_3   (0x08U << ADC_SQR3_SQ14_Pos)
 
#define ADC_SQR3_SQ14_4   (0x10U << ADC_SQR3_SQ14_Pos)
 
#define ADC_SQR3_SQ15_Pos   (10U)
 
#define ADC_SQR3_SQ15_Msk   (0x1FU << ADC_SQR3_SQ15_Pos)
 
#define ADC_SQR3_SQ15   ADC_SQR3_SQ15_Msk
 
#define ADC_SQR3_SQ15_0   (0x01U << ADC_SQR3_SQ15_Pos)
 
#define ADC_SQR3_SQ15_1   (0x02U << ADC_SQR3_SQ15_Pos)
 
#define ADC_SQR3_SQ15_2   (0x04U << ADC_SQR3_SQ15_Pos)
 
#define ADC_SQR3_SQ15_3   (0x08U << ADC_SQR3_SQ15_Pos)
 
#define ADC_SQR3_SQ15_4   (0x10U << ADC_SQR3_SQ15_Pos)
 
#define ADC_SQR3_SQ16_Pos   (15U)
 
#define ADC_SQR3_SQ16_Msk   (0x1FU << ADC_SQR3_SQ16_Pos)
 
#define ADC_SQR3_SQ16   ADC_SQR3_SQ16_Msk
 
#define ADC_SQR3_SQ16_0   (0x01U << ADC_SQR3_SQ16_Pos)
 
#define ADC_SQR3_SQ16_1   (0x02U << ADC_SQR3_SQ16_Pos)
 
#define ADC_SQR3_SQ16_2   (0x04U << ADC_SQR3_SQ16_Pos)
 
#define ADC_SQR3_SQ16_3   (0x08U << ADC_SQR3_SQ16_Pos)
 
#define ADC_SQR3_SQ16_4   (0x10U << ADC_SQR3_SQ16_Pos)
 
#define ADC_SQR3_SQ17_Pos   (20U)
 
#define ADC_SQR3_SQ17_Msk   (0x1FU << ADC_SQR3_SQ17_Pos)
 
#define ADC_SQR3_SQ17   ADC_SQR3_SQ17_Msk
 
#define ADC_SQR3_SQ17_0   (0x01U << ADC_SQR3_SQ17_Pos)
 
#define ADC_SQR3_SQ17_1   (0x02U << ADC_SQR3_SQ17_Pos)
 
#define ADC_SQR3_SQ17_2   (0x04U << ADC_SQR3_SQ17_Pos)
 
#define ADC_SQR3_SQ17_3   (0x08U << ADC_SQR3_SQ17_Pos)
 
#define ADC_SQR3_SQ17_4   (0x10U << ADC_SQR3_SQ17_Pos)
 
#define ADC_SQR3_SQ18_Pos   (25U)
 
#define ADC_SQR3_SQ18_Msk   (0x1FU << ADC_SQR3_SQ18_Pos)
 
#define ADC_SQR3_SQ18   ADC_SQR3_SQ18_Msk
 
#define ADC_SQR3_SQ18_0   (0x01U << ADC_SQR3_SQ18_Pos)
 
#define ADC_SQR3_SQ18_1   (0x02U << ADC_SQR3_SQ18_Pos)
 
#define ADC_SQR3_SQ18_2   (0x04U << ADC_SQR3_SQ18_Pos)
 
#define ADC_SQR3_SQ18_3   (0x08U << ADC_SQR3_SQ18_Pos)
 
#define ADC_SQR3_SQ18_4   (0x10U << ADC_SQR3_SQ18_Pos)
 
#define ADC_SQR4_SQ7_Pos   (0U)
 
#define ADC_SQR4_SQ7_Msk   (0x1FU << ADC_SQR4_SQ7_Pos)
 
#define ADC_SQR4_SQ7   ADC_SQR4_SQ7_Msk
 
#define ADC_SQR4_SQ7_0   (0x01U << ADC_SQR4_SQ7_Pos)
 
#define ADC_SQR4_SQ7_1   (0x02U << ADC_SQR4_SQ7_Pos)
 
#define ADC_SQR4_SQ7_2   (0x04U << ADC_SQR4_SQ7_Pos)
 
#define ADC_SQR4_SQ7_3   (0x08U << ADC_SQR4_SQ7_Pos)
 
#define ADC_SQR4_SQ7_4   (0x10U << ADC_SQR4_SQ7_Pos)
 
#define ADC_SQR4_SQ8_Pos   (5U)
 
#define ADC_SQR4_SQ8_Msk   (0x1FU << ADC_SQR4_SQ8_Pos)
 
#define ADC_SQR4_SQ8   ADC_SQR4_SQ8_Msk
 
#define ADC_SQR4_SQ8_0   (0x01U << ADC_SQR4_SQ8_Pos)
 
#define ADC_SQR4_SQ8_1   (0x02U << ADC_SQR4_SQ8_Pos)
 
#define ADC_SQR4_SQ8_2   (0x04U << ADC_SQR4_SQ8_Pos)
 
#define ADC_SQR4_SQ8_3   (0x08U << ADC_SQR4_SQ8_Pos)
 
#define ADC_SQR4_SQ8_4   (0x10U << ADC_SQR4_SQ8_Pos)
 
#define ADC_SQR4_SQ9_Pos   (10U)
 
#define ADC_SQR4_SQ9_Msk   (0x1FU << ADC_SQR4_SQ9_Pos)
 
#define ADC_SQR4_SQ9   ADC_SQR4_SQ9_Msk
 
#define ADC_SQR4_SQ9_0   (0x01U << ADC_SQR4_SQ9_Pos)
 
#define ADC_SQR4_SQ9_1   (0x02U << ADC_SQR4_SQ9_Pos)
 
#define ADC_SQR4_SQ9_2   (0x04U << ADC_SQR4_SQ9_Pos)
 
#define ADC_SQR4_SQ9_3   (0x08U << ADC_SQR4_SQ9_Pos)
 
#define ADC_SQR4_SQ9_4   (0x10U << ADC_SQR4_SQ9_Pos)
 
#define ADC_SQR4_SQ10_Pos   (15U)
 
#define ADC_SQR4_SQ10_Msk   (0x1FU << ADC_SQR4_SQ10_Pos)
 
#define ADC_SQR4_SQ10   ADC_SQR4_SQ10_Msk
 
#define ADC_SQR4_SQ10_0   (0x01U << ADC_SQR4_SQ10_Pos)
 
#define ADC_SQR4_SQ10_1   (0x02U << ADC_SQR4_SQ10_Pos)
 
#define ADC_SQR4_SQ10_2   (0x04U << ADC_SQR4_SQ10_Pos)
 
#define ADC_SQR4_SQ10_3   (0x08U << ADC_SQR4_SQ10_Pos)
 
#define ADC_SQR4_SQ10_4   (0x10U << ADC_SQR4_SQ10_Pos)
 
#define ADC_SQR4_SQ11_Pos   (20U)
 
#define ADC_SQR4_SQ11_Msk   (0x1FU << ADC_SQR4_SQ11_Pos)
 
#define ADC_SQR4_SQ11   ADC_SQR4_SQ11_Msk
 
#define ADC_SQR4_SQ11_0   (0x01U << ADC_SQR4_SQ11_Pos)
 
#define ADC_SQR4_SQ11_1   (0x02U << ADC_SQR4_SQ11_Pos)
 
#define ADC_SQR4_SQ11_2   (0x04U << ADC_SQR4_SQ11_Pos)
 
#define ADC_SQR4_SQ11_3   (0x08U << ADC_SQR4_SQ11_Pos)
 
#define ADC_SQR4_SQ11_4   (0x10U << ADC_SQR4_SQ11_Pos)
 
#define ADC_SQR4_SQ12_Pos   (25U)
 
#define ADC_SQR4_SQ12_Msk   (0x1FU << ADC_SQR4_SQ12_Pos)
 
#define ADC_SQR4_SQ12   ADC_SQR4_SQ12_Msk
 
#define ADC_SQR4_SQ12_0   (0x01U << ADC_SQR4_SQ12_Pos)
 
#define ADC_SQR4_SQ12_1   (0x02U << ADC_SQR4_SQ12_Pos)
 
#define ADC_SQR4_SQ12_2   (0x04U << ADC_SQR4_SQ12_Pos)
 
#define ADC_SQR4_SQ12_3   (0x08U << ADC_SQR4_SQ12_Pos)
 
#define ADC_SQR4_SQ12_4   (0x10U << ADC_SQR4_SQ12_Pos)
 
#define ADC_SQR5_SQ1_Pos   (0U)
 
#define ADC_SQR5_SQ1_Msk   (0x1FU << ADC_SQR5_SQ1_Pos)
 
#define ADC_SQR5_SQ1   ADC_SQR5_SQ1_Msk
 
#define ADC_SQR5_SQ1_0   (0x01U << ADC_SQR5_SQ1_Pos)
 
#define ADC_SQR5_SQ1_1   (0x02U << ADC_SQR5_SQ1_Pos)
 
#define ADC_SQR5_SQ1_2   (0x04U << ADC_SQR5_SQ1_Pos)
 
#define ADC_SQR5_SQ1_3   (0x08U << ADC_SQR5_SQ1_Pos)
 
#define ADC_SQR5_SQ1_4   (0x10U << ADC_SQR5_SQ1_Pos)
 
#define ADC_SQR5_SQ2_Pos   (5U)
 
#define ADC_SQR5_SQ2_Msk   (0x1FU << ADC_SQR5_SQ2_Pos)
 
#define ADC_SQR5_SQ2   ADC_SQR5_SQ2_Msk
 
#define ADC_SQR5_SQ2_0   (0x01U << ADC_SQR5_SQ2_Pos)
 
#define ADC_SQR5_SQ2_1   (0x02U << ADC_SQR5_SQ2_Pos)
 
#define ADC_SQR5_SQ2_2   (0x04U << ADC_SQR5_SQ2_Pos)
 
#define ADC_SQR5_SQ2_3   (0x08U << ADC_SQR5_SQ2_Pos)
 
#define ADC_SQR5_SQ2_4   (0x10U << ADC_SQR5_SQ2_Pos)
 
#define ADC_SQR5_SQ3_Pos   (10U)
 
#define ADC_SQR5_SQ3_Msk   (0x1FU << ADC_SQR5_SQ3_Pos)
 
#define ADC_SQR5_SQ3   ADC_SQR5_SQ3_Msk
 
#define ADC_SQR5_SQ3_0   (0x01U << ADC_SQR5_SQ3_Pos)
 
#define ADC_SQR5_SQ3_1   (0x02U << ADC_SQR5_SQ3_Pos)
 
#define ADC_SQR5_SQ3_2   (0x04U << ADC_SQR5_SQ3_Pos)
 
#define ADC_SQR5_SQ3_3   (0x08U << ADC_SQR5_SQ3_Pos)
 
#define ADC_SQR5_SQ3_4   (0x10U << ADC_SQR5_SQ3_Pos)
 
#define ADC_SQR5_SQ4_Pos   (15U)
 
#define ADC_SQR5_SQ4_Msk   (0x1FU << ADC_SQR5_SQ4_Pos)
 
#define ADC_SQR5_SQ4   ADC_SQR5_SQ4_Msk
 
#define ADC_SQR5_SQ4_0   (0x01U << ADC_SQR5_SQ4_Pos)
 
#define ADC_SQR5_SQ4_1   (0x02U << ADC_SQR5_SQ4_Pos)
 
#define ADC_SQR5_SQ4_2   (0x04U << ADC_SQR5_SQ4_Pos)
 
#define ADC_SQR5_SQ4_3   (0x08U << ADC_SQR5_SQ4_Pos)
 
#define ADC_SQR5_SQ4_4   (0x10U << ADC_SQR5_SQ4_Pos)
 
#define ADC_SQR5_SQ5_Pos   (20U)
 
#define ADC_SQR5_SQ5_Msk   (0x1FU << ADC_SQR5_SQ5_Pos)
 
#define ADC_SQR5_SQ5   ADC_SQR5_SQ5_Msk
 
#define ADC_SQR5_SQ5_0   (0x01U << ADC_SQR5_SQ5_Pos)
 
#define ADC_SQR5_SQ5_1   (0x02U << ADC_SQR5_SQ5_Pos)
 
#define ADC_SQR5_SQ5_2   (0x04U << ADC_SQR5_SQ5_Pos)
 
#define ADC_SQR5_SQ5_3   (0x08U << ADC_SQR5_SQ5_Pos)
 
#define ADC_SQR5_SQ5_4   (0x10U << ADC_SQR5_SQ5_Pos)
 
#define ADC_SQR5_SQ6_Pos   (25U)
 
#define ADC_SQR5_SQ6_Msk   (0x1FU << ADC_SQR5_SQ6_Pos)
 
#define ADC_SQR5_SQ6   ADC_SQR5_SQ6_Msk
 
#define ADC_SQR5_SQ6_0   (0x01U << ADC_SQR5_SQ6_Pos)
 
#define ADC_SQR5_SQ6_1   (0x02U << ADC_SQR5_SQ6_Pos)
 
#define ADC_SQR5_SQ6_2   (0x04U << ADC_SQR5_SQ6_Pos)
 
#define ADC_SQR5_SQ6_3   (0x08U << ADC_SQR5_SQ6_Pos)
 
#define ADC_SQR5_SQ6_4   (0x10U << ADC_SQR5_SQ6_Pos)
 
#define ADC_JSQR_JSQ1_Pos   (0U)
 
#define ADC_JSQR_JSQ1_Msk   (0x1FU << ADC_JSQR_JSQ1_Pos)
 
#define ADC_JSQR_JSQ1   ADC_JSQR_JSQ1_Msk
 
#define ADC_JSQR_JSQ1_0   (0x01U << ADC_JSQR_JSQ1_Pos)
 
#define ADC_JSQR_JSQ1_1   (0x02U << ADC_JSQR_JSQ1_Pos)
 
#define ADC_JSQR_JSQ1_2   (0x04U << ADC_JSQR_JSQ1_Pos)
 
#define ADC_JSQR_JSQ1_3   (0x08U << ADC_JSQR_JSQ1_Pos)
 
#define ADC_JSQR_JSQ1_4   (0x10U << ADC_JSQR_JSQ1_Pos)
 
#define ADC_JSQR_JSQ2_Pos   (5U)
 
#define ADC_JSQR_JSQ2_Msk   (0x1FU << ADC_JSQR_JSQ2_Pos)
 
#define ADC_JSQR_JSQ2   ADC_JSQR_JSQ2_Msk
 
#define ADC_JSQR_JSQ2_0   (0x01U << ADC_JSQR_JSQ2_Pos)
 
#define ADC_JSQR_JSQ2_1   (0x02U << ADC_JSQR_JSQ2_Pos)
 
#define ADC_JSQR_JSQ2_2   (0x04U << ADC_JSQR_JSQ2_Pos)
 
#define ADC_JSQR_JSQ2_3   (0x08U << ADC_JSQR_JSQ2_Pos)
 
#define ADC_JSQR_JSQ2_4   (0x10U << ADC_JSQR_JSQ2_Pos)
 
#define ADC_JSQR_JSQ3_Pos   (10U)
 
#define ADC_JSQR_JSQ3_Msk   (0x1FU << ADC_JSQR_JSQ3_Pos)
 
#define ADC_JSQR_JSQ3   ADC_JSQR_JSQ3_Msk
 
#define ADC_JSQR_JSQ3_0   (0x01U << ADC_JSQR_JSQ3_Pos)
 
#define ADC_JSQR_JSQ3_1   (0x02U << ADC_JSQR_JSQ3_Pos)
 
#define ADC_JSQR_JSQ3_2   (0x04U << ADC_JSQR_JSQ3_Pos)
 
#define ADC_JSQR_JSQ3_3   (0x08U << ADC_JSQR_JSQ3_Pos)
 
#define ADC_JSQR_JSQ3_4   (0x10U << ADC_JSQR_JSQ3_Pos)
 
#define ADC_JSQR_JSQ4_Pos   (15U)
 
#define ADC_JSQR_JSQ4_Msk   (0x1FU << ADC_JSQR_JSQ4_Pos)
 
#define ADC_JSQR_JSQ4   ADC_JSQR_JSQ4_Msk
 
#define ADC_JSQR_JSQ4_0   (0x01U << ADC_JSQR_JSQ4_Pos)
 
#define ADC_JSQR_JSQ4_1   (0x02U << ADC_JSQR_JSQ4_Pos)
 
#define ADC_JSQR_JSQ4_2   (0x04U << ADC_JSQR_JSQ4_Pos)
 
#define ADC_JSQR_JSQ4_3   (0x08U << ADC_JSQR_JSQ4_Pos)
 
#define ADC_JSQR_JSQ4_4   (0x10U << ADC_JSQR_JSQ4_Pos)
 
#define ADC_JSQR_JL_Pos   (20U)
 
#define ADC_JSQR_JL_Msk   (0x3U << ADC_JSQR_JL_Pos)
 
#define ADC_JSQR_JL   ADC_JSQR_JL_Msk
 
#define ADC_JSQR_JL_0   (0x1U << ADC_JSQR_JL_Pos)
 
#define ADC_JSQR_JL_1   (0x2U << ADC_JSQR_JL_Pos)
 
#define ADC_JDR1_JDATA_Pos   (0U)
 
#define ADC_JDR1_JDATA_Msk   (0xFFFFU << ADC_JDR1_JDATA_Pos)
 
#define ADC_JDR1_JDATA   ADC_JDR1_JDATA_Msk
 
#define ADC_JDR2_JDATA_Pos   (0U)
 
#define ADC_JDR2_JDATA_Msk   (0xFFFFU << ADC_JDR2_JDATA_Pos)
 
#define ADC_JDR2_JDATA   ADC_JDR2_JDATA_Msk
 
#define ADC_JDR3_JDATA_Pos   (0U)
 
#define ADC_JDR3_JDATA_Msk   (0xFFFFU << ADC_JDR3_JDATA_Pos)
 
#define ADC_JDR3_JDATA   ADC_JDR3_JDATA_Msk
 
#define ADC_JDR4_JDATA_Pos   (0U)
 
#define ADC_JDR4_JDATA_Msk   (0xFFFFU << ADC_JDR4_JDATA_Pos)
 
#define ADC_JDR4_JDATA   ADC_JDR4_JDATA_Msk
 
#define ADC_DR_DATA_Pos   (0U)
 
#define ADC_DR_DATA_Msk   (0xFFFFU << ADC_DR_DATA_Pos)
 
#define ADC_DR_DATA   ADC_DR_DATA_Msk
 
#define ADC_SMPR0_SMP30_Pos   (0U)
 
#define ADC_SMPR0_SMP30_Msk   (0x7U << ADC_SMPR0_SMP30_Pos)
 
#define ADC_SMPR0_SMP30   ADC_SMPR0_SMP30_Msk
 
#define ADC_SMPR0_SMP30_0   (0x1U << ADC_SMPR0_SMP30_Pos)
 
#define ADC_SMPR0_SMP30_1   (0x2U << ADC_SMPR0_SMP30_Pos)
 
#define ADC_SMPR0_SMP30_2   (0x4U << ADC_SMPR0_SMP30_Pos)
 
#define ADC_SMPR0_SMP31_Pos   (3U)
 
#define ADC_SMPR0_SMP31_Msk   (0x7U << ADC_SMPR0_SMP31_Pos)
 
#define ADC_SMPR0_SMP31   ADC_SMPR0_SMP31_Msk
 
#define ADC_SMPR0_SMP31_0   (0x1U << ADC_SMPR0_SMP31_Pos)
 
#define ADC_SMPR0_SMP31_1   (0x2U << ADC_SMPR0_SMP31_Pos)
 
#define ADC_SMPR0_SMP31_2   (0x4U << ADC_SMPR0_SMP31_Pos)
 
#define ADC_CSR_AWD1_Pos   (0U)
 
#define ADC_CSR_AWD1_Msk   (0x1U << ADC_CSR_AWD1_Pos)
 
#define ADC_CSR_AWD1   ADC_CSR_AWD1_Msk
 
#define ADC_CSR_EOCS1_Pos   (1U)
 
#define ADC_CSR_EOCS1_Msk   (0x1U << ADC_CSR_EOCS1_Pos)
 
#define ADC_CSR_EOCS1   ADC_CSR_EOCS1_Msk
 
#define ADC_CSR_JEOS1_Pos   (2U)
 
#define ADC_CSR_JEOS1_Msk   (0x1U << ADC_CSR_JEOS1_Pos)
 
#define ADC_CSR_JEOS1   ADC_CSR_JEOS1_Msk
 
#define ADC_CSR_JSTRT1_Pos   (3U)
 
#define ADC_CSR_JSTRT1_Msk   (0x1U << ADC_CSR_JSTRT1_Pos)
 
#define ADC_CSR_JSTRT1   ADC_CSR_JSTRT1_Msk
 
#define ADC_CSR_STRT1_Pos   (4U)
 
#define ADC_CSR_STRT1_Msk   (0x1U << ADC_CSR_STRT1_Pos)
 
#define ADC_CSR_STRT1   ADC_CSR_STRT1_Msk
 
#define ADC_CSR_OVR1_Pos   (5U)
 
#define ADC_CSR_OVR1_Msk   (0x1U << ADC_CSR_OVR1_Pos)
 
#define ADC_CSR_OVR1   ADC_CSR_OVR1_Msk
 
#define ADC_CSR_ADONS1_Pos   (6U)
 
#define ADC_CSR_ADONS1_Msk   (0x1U << ADC_CSR_ADONS1_Pos)
 
#define ADC_CSR_ADONS1   ADC_CSR_ADONS1_Msk
 
#define ADC_CSR_EOC1   (ADC_CSR_EOCS1)
 
#define ADC_CSR_JEOC1   (ADC_CSR_JEOS1)
 
#define ADC_CCR_ADCPRE_Pos   (16U)
 
#define ADC_CCR_ADCPRE_Msk   (0x3U << ADC_CCR_ADCPRE_Pos)
 
#define ADC_CCR_ADCPRE   ADC_CCR_ADCPRE_Msk
 
#define ADC_CCR_ADCPRE_0   (0x1U << ADC_CCR_ADCPRE_Pos)
 
#define ADC_CCR_ADCPRE_1   (0x2U << ADC_CCR_ADCPRE_Pos)
 
#define ADC_CCR_TSVREFE_Pos   (23U)
 
#define ADC_CCR_TSVREFE_Msk   (0x1U << ADC_CCR_TSVREFE_Pos)
 
#define ADC_CCR_TSVREFE   ADC_CCR_TSVREFE_Msk
 
#define COMP_CSR_10KPU   (0x00000001U)
 
#define COMP_CSR_400KPU   (0x00000002U)
 
#define COMP_CSR_10KPD   (0x00000004U)
 
#define COMP_CSR_400KPD   (0x00000008U)
 
#define COMP_CSR_CMP1EN_Pos   (4U)
 
#define COMP_CSR_CMP1EN_Msk   (0x1U << COMP_CSR_CMP1EN_Pos)
 
#define COMP_CSR_CMP1EN   COMP_CSR_CMP1EN_Msk
 
#define COMP_CSR_CMP1OUT_Pos   (7U)
 
#define COMP_CSR_CMP1OUT_Msk   (0x1U << COMP_CSR_CMP1OUT_Pos)
 
#define COMP_CSR_CMP1OUT   COMP_CSR_CMP1OUT_Msk
 
#define COMP_CSR_SPEED_Pos   (12U)
 
#define COMP_CSR_SPEED_Msk   (0x1U << COMP_CSR_SPEED_Pos)
 
#define COMP_CSR_SPEED   COMP_CSR_SPEED_Msk
 
#define COMP_CSR_CMP2OUT_Pos   (13U)
 
#define COMP_CSR_CMP2OUT_Msk   (0x1U << COMP_CSR_CMP2OUT_Pos)
 
#define COMP_CSR_CMP2OUT   COMP_CSR_CMP2OUT_Msk
 
#define COMP_CSR_WNDWE_Pos   (17U)
 
#define COMP_CSR_WNDWE_Msk   (0x1U << COMP_CSR_WNDWE_Pos)
 
#define COMP_CSR_WNDWE   COMP_CSR_WNDWE_Msk
 
#define COMP_CSR_INSEL_Pos   (18U)
 
#define COMP_CSR_INSEL_Msk   (0x7U << COMP_CSR_INSEL_Pos)
 
#define COMP_CSR_INSEL   COMP_CSR_INSEL_Msk
 
#define COMP_CSR_INSEL_0   (0x1U << COMP_CSR_INSEL_Pos)
 
#define COMP_CSR_INSEL_1   (0x2U << COMP_CSR_INSEL_Pos)
 
#define COMP_CSR_INSEL_2   (0x4U << COMP_CSR_INSEL_Pos)
 
#define COMP_CSR_OUTSEL_Pos   (21U)
 
#define COMP_CSR_OUTSEL_Msk   (0x7U << COMP_CSR_OUTSEL_Pos)
 
#define COMP_CSR_OUTSEL   COMP_CSR_OUTSEL_Msk
 
#define COMP_CSR_OUTSEL_0   (0x1U << COMP_CSR_OUTSEL_Pos)
 
#define COMP_CSR_OUTSEL_1   (0x2U << COMP_CSR_OUTSEL_Pos)
 
#define COMP_CSR_OUTSEL_2   (0x4U << COMP_CSR_OUTSEL_Pos)
 
#define COMP_CSR_SW1_Pos   (5U)
 
#define COMP_CSR_SW1_Msk   (0x1U << COMP_CSR_SW1_Pos)
 
#define COMP_CSR_SW1   COMP_CSR_SW1_Msk
 
#define COMP_CSR_VREFOUTEN_Pos   (16U)
 
#define COMP_CSR_VREFOUTEN_Msk   (0x1U << COMP_CSR_VREFOUTEN_Pos)
 
#define COMP_CSR_VREFOUTEN   COMP_CSR_VREFOUTEN_Msk
 
#define COMP_CSR_FCH3_Pos   (26U)
 
#define COMP_CSR_FCH3_Msk   (0x1U << COMP_CSR_FCH3_Pos)
 
#define COMP_CSR_FCH3   COMP_CSR_FCH3_Msk
 
#define COMP_CSR_FCH8_Pos   (27U)
 
#define COMP_CSR_FCH8_Msk   (0x1U << COMP_CSR_FCH8_Pos)
 
#define COMP_CSR_FCH8   COMP_CSR_FCH8_Msk
 
#define COMP_CSR_RCH13_Pos   (28U)
 
#define COMP_CSR_RCH13_Msk   (0x1U << COMP_CSR_RCH13_Pos)
 
#define COMP_CSR_RCH13   COMP_CSR_RCH13_Msk
 
#define COMP_CSR_CAIE_Pos   (29U)
 
#define COMP_CSR_CAIE_Msk   (0x1U << COMP_CSR_CAIE_Pos)
 
#define COMP_CSR_CAIE   COMP_CSR_CAIE_Msk
 
#define COMP_CSR_CAIF_Pos   (30U)
 
#define COMP_CSR_CAIF_Msk   (0x1U << COMP_CSR_CAIF_Pos)
 
#define COMP_CSR_CAIF   COMP_CSR_CAIF_Msk
 
#define COMP_CSR_TSUSP_Pos   (31U)
 
#define COMP_CSR_TSUSP_Msk   (0x1U << COMP_CSR_TSUSP_Pos)
 
#define COMP_CSR_TSUSP   COMP_CSR_TSUSP_Msk
 
#define OPAMP_CSR_OPA1PD_Pos   (0U)
 
#define OPAMP_CSR_OPA1PD_Msk   (0x1U << OPAMP_CSR_OPA1PD_Pos)
 
#define OPAMP_CSR_OPA1PD   OPAMP_CSR_OPA1PD_Msk
 
#define OPAMP_CSR_S3SEL1_Pos   (1U)
 
#define OPAMP_CSR_S3SEL1_Msk   (0x1U << OPAMP_CSR_S3SEL1_Pos)
 
#define OPAMP_CSR_S3SEL1   OPAMP_CSR_S3SEL1_Msk
 
#define OPAMP_CSR_S4SEL1_Pos   (2U)
 
#define OPAMP_CSR_S4SEL1_Msk   (0x1U << OPAMP_CSR_S4SEL1_Pos)
 
#define OPAMP_CSR_S4SEL1   OPAMP_CSR_S4SEL1_Msk
 
#define OPAMP_CSR_S5SEL1_Pos   (3U)
 
#define OPAMP_CSR_S5SEL1_Msk   (0x1U << OPAMP_CSR_S5SEL1_Pos)
 
#define OPAMP_CSR_S5SEL1   OPAMP_CSR_S5SEL1_Msk
 
#define OPAMP_CSR_S6SEL1_Pos   (4U)
 
#define OPAMP_CSR_S6SEL1_Msk   (0x1U << OPAMP_CSR_S6SEL1_Pos)
 
#define OPAMP_CSR_S6SEL1   OPAMP_CSR_S6SEL1_Msk
 
#define OPAMP_CSR_OPA1CAL_L_Pos   (5U)
 
#define OPAMP_CSR_OPA1CAL_L_Msk   (0x1U << OPAMP_CSR_OPA1CAL_L_Pos)
 
#define OPAMP_CSR_OPA1CAL_L   OPAMP_CSR_OPA1CAL_L_Msk
 
#define OPAMP_CSR_OPA1CAL_H_Pos   (6U)
 
#define OPAMP_CSR_OPA1CAL_H_Msk   (0x1U << OPAMP_CSR_OPA1CAL_H_Pos)
 
#define OPAMP_CSR_OPA1CAL_H   OPAMP_CSR_OPA1CAL_H_Msk
 
#define OPAMP_CSR_OPA1LPM_Pos   (7U)
 
#define OPAMP_CSR_OPA1LPM_Msk   (0x1U << OPAMP_CSR_OPA1LPM_Pos)
 
#define OPAMP_CSR_OPA1LPM   OPAMP_CSR_OPA1LPM_Msk
 
#define OPAMP_CSR_OPA2PD_Pos   (8U)
 
#define OPAMP_CSR_OPA2PD_Msk   (0x1U << OPAMP_CSR_OPA2PD_Pos)
 
#define OPAMP_CSR_OPA2PD   OPAMP_CSR_OPA2PD_Msk
 
#define OPAMP_CSR_S3SEL2_Pos   (9U)
 
#define OPAMP_CSR_S3SEL2_Msk   (0x1U << OPAMP_CSR_S3SEL2_Pos)
 
#define OPAMP_CSR_S3SEL2   OPAMP_CSR_S3SEL2_Msk
 
#define OPAMP_CSR_S4SEL2_Pos   (10U)
 
#define OPAMP_CSR_S4SEL2_Msk   (0x1U << OPAMP_CSR_S4SEL2_Pos)
 
#define OPAMP_CSR_S4SEL2   OPAMP_CSR_S4SEL2_Msk
 
#define OPAMP_CSR_S5SEL2_Pos   (11U)
 
#define OPAMP_CSR_S5SEL2_Msk   (0x1U << OPAMP_CSR_S5SEL2_Pos)
 
#define OPAMP_CSR_S5SEL2   OPAMP_CSR_S5SEL2_Msk
 
#define OPAMP_CSR_S6SEL2_Pos   (12U)
 
#define OPAMP_CSR_S6SEL2_Msk   (0x1U << OPAMP_CSR_S6SEL2_Pos)
 
#define OPAMP_CSR_S6SEL2   OPAMP_CSR_S6SEL2_Msk
 
#define OPAMP_CSR_OPA2CAL_L_Pos   (13U)
 
#define OPAMP_CSR_OPA2CAL_L_Msk   (0x1U << OPAMP_CSR_OPA2CAL_L_Pos)
 
#define OPAMP_CSR_OPA2CAL_L   OPAMP_CSR_OPA2CAL_L_Msk
 
#define OPAMP_CSR_OPA2CAL_H_Pos   (14U)
 
#define OPAMP_CSR_OPA2CAL_H_Msk   (0x1U << OPAMP_CSR_OPA2CAL_H_Pos)
 
#define OPAMP_CSR_OPA2CAL_H   OPAMP_CSR_OPA2CAL_H_Msk
 
#define OPAMP_CSR_OPA2LPM_Pos   (15U)
 
#define OPAMP_CSR_OPA2LPM_Msk   (0x1U << OPAMP_CSR_OPA2LPM_Pos)
 
#define OPAMP_CSR_OPA2LPM   OPAMP_CSR_OPA2LPM_Msk
 
#define OPAMP_CSR_ANAWSEL1_Pos   (24U)
 
#define OPAMP_CSR_ANAWSEL1_Msk   (0x1U << OPAMP_CSR_ANAWSEL1_Pos)
 
#define OPAMP_CSR_ANAWSEL1   OPAMP_CSR_ANAWSEL1_Msk
 
#define OPAMP_CSR_ANAWSEL2_Pos   (25U)
 
#define OPAMP_CSR_ANAWSEL2_Msk   (0x1U << OPAMP_CSR_ANAWSEL2_Pos)
 
#define OPAMP_CSR_ANAWSEL2   OPAMP_CSR_ANAWSEL2_Msk
 
#define OPAMP_CSR_S7SEL2_Pos   (27U)
 
#define OPAMP_CSR_S7SEL2_Msk   (0x1U << OPAMP_CSR_S7SEL2_Pos)
 
#define OPAMP_CSR_S7SEL2   OPAMP_CSR_S7SEL2_Msk
 
#define OPAMP_CSR_AOP_RANGE_Pos   (28U)
 
#define OPAMP_CSR_AOP_RANGE_Msk   (0x1U << OPAMP_CSR_AOP_RANGE_Pos)
 
#define OPAMP_CSR_AOP_RANGE   OPAMP_CSR_AOP_RANGE_Msk
 
#define OPAMP_CSR_OPA1CALOUT_Pos   (29U)
 
#define OPAMP_CSR_OPA1CALOUT_Msk   (0x1U << OPAMP_CSR_OPA1CALOUT_Pos)
 
#define OPAMP_CSR_OPA1CALOUT   OPAMP_CSR_OPA1CALOUT_Msk
 
#define OPAMP_CSR_OPA2CALOUT_Pos   (30U)
 
#define OPAMP_CSR_OPA2CALOUT_Msk   (0x1U << OPAMP_CSR_OPA2CALOUT_Pos)
 
#define OPAMP_CSR_OPA2CALOUT   OPAMP_CSR_OPA2CALOUT_Msk
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos   (0U)
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk   (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos)
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos   (5U)
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk   (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos)
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos   (10U)
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk   (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos)
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW   OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos   (15U)
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk   (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos)
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH   OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk
 
#define OPAMP_OTR_OT_USER_Pos   (31U)
 
#define OPAMP_OTR_OT_USER_Msk   (0x1U << OPAMP_OTR_OT_USER_Pos)
 
#define OPAMP_OTR_OT_USER   OPAMP_OTR_OT_USER_Msk
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos   (0U)
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk   (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos)
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos   (5U)
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk   (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos)
 
#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos   (10U)
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk   (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos)
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW   OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos   (15U)
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk   (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos)
 
#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH   OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk
 
#define CRC_DR_DR_Pos   (0U)
 
#define CRC_DR_DR_Msk   (0xFFFFFFFFU << CRC_DR_DR_Pos)
 
#define CRC_DR_DR   CRC_DR_DR_Msk
 
#define CRC_IDR_IDR_Pos   (0U)
 
#define CRC_IDR_IDR_Msk   (0xFFU << CRC_IDR_IDR_Pos)
 
#define CRC_IDR_IDR   CRC_IDR_IDR_Msk
 
#define CRC_CR_RESET_Pos   (0U)
 
#define CRC_CR_RESET_Msk   (0x1U << CRC_CR_RESET_Pos)
 
#define CRC_CR_RESET   CRC_CR_RESET_Msk
 
#define DAC_CR_EN1_Pos   (0U)
 
#define DAC_CR_EN1_Msk   (0x1U << DAC_CR_EN1_Pos)
 
#define DAC_CR_EN1   DAC_CR_EN1_Msk
 
#define DAC_CR_BOFF1_Pos   (1U)
 
#define DAC_CR_BOFF1_Msk   (0x1U << DAC_CR_BOFF1_Pos)
 
#define DAC_CR_BOFF1   DAC_CR_BOFF1_Msk
 
#define DAC_CR_TEN1_Pos   (2U)
 
#define DAC_CR_TEN1_Msk   (0x1U << DAC_CR_TEN1_Pos)
 
#define DAC_CR_TEN1   DAC_CR_TEN1_Msk
 
#define DAC_CR_TSEL1_Pos   (3U)
 
#define DAC_CR_TSEL1_Msk   (0x7U << DAC_CR_TSEL1_Pos)
 
#define DAC_CR_TSEL1   DAC_CR_TSEL1_Msk
 
#define DAC_CR_TSEL1_0   (0x1U << DAC_CR_TSEL1_Pos)
 
#define DAC_CR_TSEL1_1   (0x2U << DAC_CR_TSEL1_Pos)
 
#define DAC_CR_TSEL1_2   (0x4U << DAC_CR_TSEL1_Pos)
 
#define DAC_CR_WAVE1_Pos   (6U)
 
#define DAC_CR_WAVE1_Msk   (0x3U << DAC_CR_WAVE1_Pos)
 
#define DAC_CR_WAVE1   DAC_CR_WAVE1_Msk
 
#define DAC_CR_WAVE1_0   (0x1U << DAC_CR_WAVE1_Pos)
 
#define DAC_CR_WAVE1_1   (0x2U << DAC_CR_WAVE1_Pos)
 
#define DAC_CR_MAMP1_Pos   (8U)
 
#define DAC_CR_MAMP1_Msk   (0xFU << DAC_CR_MAMP1_Pos)
 
#define DAC_CR_MAMP1   DAC_CR_MAMP1_Msk
 
#define DAC_CR_MAMP1_0   (0x1U << DAC_CR_MAMP1_Pos)
 
#define DAC_CR_MAMP1_1   (0x2U << DAC_CR_MAMP1_Pos)
 
#define DAC_CR_MAMP1_2   (0x4U << DAC_CR_MAMP1_Pos)
 
#define DAC_CR_MAMP1_3   (0x8U << DAC_CR_MAMP1_Pos)
 
#define DAC_CR_DMAEN1_Pos   (12U)
 
#define DAC_CR_DMAEN1_Msk   (0x1U << DAC_CR_DMAEN1_Pos)
 
#define DAC_CR_DMAEN1   DAC_CR_DMAEN1_Msk
 
#define DAC_CR_DMAUDRIE1_Pos   (13U)
 
#define DAC_CR_DMAUDRIE1_Msk   (0x1U << DAC_CR_DMAUDRIE1_Pos)
 
#define DAC_CR_DMAUDRIE1   DAC_CR_DMAUDRIE1_Msk
 
#define DAC_CR_EN2_Pos   (16U)
 
#define DAC_CR_EN2_Msk   (0x1U << DAC_CR_EN2_Pos)
 
#define DAC_CR_EN2   DAC_CR_EN2_Msk
 
#define DAC_CR_BOFF2_Pos   (17U)
 
#define DAC_CR_BOFF2_Msk   (0x1U << DAC_CR_BOFF2_Pos)
 
#define DAC_CR_BOFF2   DAC_CR_BOFF2_Msk
 
#define DAC_CR_TEN2_Pos   (18U)
 
#define DAC_CR_TEN2_Msk   (0x1U << DAC_CR_TEN2_Pos)
 
#define DAC_CR_TEN2   DAC_CR_TEN2_Msk
 
#define DAC_CR_TSEL2_Pos   (19U)
 
#define DAC_CR_TSEL2_Msk   (0x7U << DAC_CR_TSEL2_Pos)
 
#define DAC_CR_TSEL2   DAC_CR_TSEL2_Msk
 
#define DAC_CR_TSEL2_0   (0x1U << DAC_CR_TSEL2_Pos)
 
#define DAC_CR_TSEL2_1   (0x2U << DAC_CR_TSEL2_Pos)
 
#define DAC_CR_TSEL2_2   (0x4U << DAC_CR_TSEL2_Pos)
 
#define DAC_CR_WAVE2_Pos   (22U)
 
#define DAC_CR_WAVE2_Msk   (0x3U << DAC_CR_WAVE2_Pos)
 
#define DAC_CR_WAVE2   DAC_CR_WAVE2_Msk
 
#define DAC_CR_WAVE2_0   (0x1U << DAC_CR_WAVE2_Pos)
 
#define DAC_CR_WAVE2_1   (0x2U << DAC_CR_WAVE2_Pos)
 
#define DAC_CR_MAMP2_Pos   (24U)
 
#define DAC_CR_MAMP2_Msk   (0xFU << DAC_CR_MAMP2_Pos)
 
#define DAC_CR_MAMP2   DAC_CR_MAMP2_Msk
 
#define DAC_CR_MAMP2_0   (0x1U << DAC_CR_MAMP2_Pos)
 
#define DAC_CR_MAMP2_1   (0x2U << DAC_CR_MAMP2_Pos)
 
#define DAC_CR_MAMP2_2   (0x4U << DAC_CR_MAMP2_Pos)
 
#define DAC_CR_MAMP2_3   (0x8U << DAC_CR_MAMP2_Pos)
 
#define DAC_CR_DMAEN2_Pos   (28U)
 
#define DAC_CR_DMAEN2_Msk   (0x1U << DAC_CR_DMAEN2_Pos)
 
#define DAC_CR_DMAEN2   DAC_CR_DMAEN2_Msk
 
#define DAC_CR_DMAUDRIE2_Pos   (29U)
 
#define DAC_CR_DMAUDRIE2_Msk   (0x1U << DAC_CR_DMAUDRIE2_Pos)
 
#define DAC_CR_DMAUDRIE2   DAC_CR_DMAUDRIE2_Msk
 
#define DAC_SWTRIGR_SWTRIG1_Pos   (0U)
 
#define DAC_SWTRIGR_SWTRIG1_Msk   (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)
 
#define DAC_SWTRIGR_SWTRIG1   DAC_SWTRIGR_SWTRIG1_Msk
 
#define DAC_SWTRIGR_SWTRIG2_Pos   (1U)
 
#define DAC_SWTRIGR_SWTRIG2_Msk   (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)
 
#define DAC_SWTRIGR_SWTRIG2   DAC_SWTRIGR_SWTRIG2_Msk
 
#define DAC_DHR12R1_DACC1DHR_Pos   (0U)
 
#define DAC_DHR12R1_DACC1DHR_Msk   (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)
 
#define DAC_DHR12R1_DACC1DHR   DAC_DHR12R1_DACC1DHR_Msk
 
#define DAC_DHR12L1_DACC1DHR_Pos   (4U)
 
#define DAC_DHR12L1_DACC1DHR_Msk   (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)
 
#define DAC_DHR12L1_DACC1DHR   DAC_DHR12L1_DACC1DHR_Msk
 
#define DAC_DHR8R1_DACC1DHR_Pos   (0U)
 
#define DAC_DHR8R1_DACC1DHR_Msk   (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)
 
#define DAC_DHR8R1_DACC1DHR   DAC_DHR8R1_DACC1DHR_Msk
 
#define DAC_DHR12R2_DACC2DHR_Pos   (0U)
 
#define DAC_DHR12R2_DACC2DHR_Msk   (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)
 
#define DAC_DHR12R2_DACC2DHR   DAC_DHR12R2_DACC2DHR_Msk
 
#define DAC_DHR12L2_DACC2DHR_Pos   (4U)
 
#define DAC_DHR12L2_DACC2DHR_Msk   (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)
 
#define DAC_DHR12L2_DACC2DHR   DAC_DHR12L2_DACC2DHR_Msk
 
#define DAC_DHR8R2_DACC2DHR_Pos   (0U)
 
#define DAC_DHR8R2_DACC2DHR_Msk   (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)
 
#define DAC_DHR8R2_DACC2DHR   DAC_DHR8R2_DACC2DHR_Msk
 
#define DAC_DHR12RD_DACC1DHR_Pos   (0U)
 
#define DAC_DHR12RD_DACC1DHR_Msk   (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)
 
#define DAC_DHR12RD_DACC1DHR   DAC_DHR12RD_DACC1DHR_Msk
 
#define DAC_DHR12RD_DACC2DHR_Pos   (16U)
 
#define DAC_DHR12RD_DACC2DHR_Msk   (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)
 
#define DAC_DHR12RD_DACC2DHR   DAC_DHR12RD_DACC2DHR_Msk
 
#define DAC_DHR12LD_DACC1DHR_Pos   (4U)
 
#define DAC_DHR12LD_DACC1DHR_Msk   (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)
 
#define DAC_DHR12LD_DACC1DHR   DAC_DHR12LD_DACC1DHR_Msk
 
#define DAC_DHR12LD_DACC2DHR_Pos   (20U)
 
#define DAC_DHR12LD_DACC2DHR_Msk   (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)
 
#define DAC_DHR12LD_DACC2DHR   DAC_DHR12LD_DACC2DHR_Msk
 
#define DAC_DHR8RD_DACC1DHR_Pos   (0U)
 
#define DAC_DHR8RD_DACC1DHR_Msk   (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)
 
#define DAC_DHR8RD_DACC1DHR   DAC_DHR8RD_DACC1DHR_Msk
 
#define DAC_DHR8RD_DACC2DHR_Pos   (8U)
 
#define DAC_DHR8RD_DACC2DHR_Msk   (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)
 
#define DAC_DHR8RD_DACC2DHR   DAC_DHR8RD_DACC2DHR_Msk
 
#define DAC_DOR1_DACC1DOR_Pos   (0U)
 
#define DAC_DOR1_DACC1DOR_Msk   (0xFFFU << DAC_DOR1_DACC1DOR_Pos)
 
#define DAC_DOR1_DACC1DOR   DAC_DOR1_DACC1DOR_Msk
 
#define DAC_DOR2_DACC2DOR_Pos   (0U)
 
#define DAC_DOR2_DACC2DOR_Msk   (0xFFFU << DAC_DOR2_DACC2DOR_Pos)
 
#define DAC_DOR2_DACC2DOR   DAC_DOR2_DACC2DOR_Msk
 
#define DAC_SR_DMAUDR1_Pos   (13U)
 
#define DAC_SR_DMAUDR1_Msk   (0x1U << DAC_SR_DMAUDR1_Pos)
 
#define DAC_SR_DMAUDR1   DAC_SR_DMAUDR1_Msk
 
#define DAC_SR_DMAUDR2_Pos   (29U)
 
#define DAC_SR_DMAUDR2_Msk   (0x1U << DAC_SR_DMAUDR2_Pos)
 
#define DAC_SR_DMAUDR2   DAC_SR_DMAUDR2_Msk
 
#define DBGMCU_IDCODE_DEV_ID_Pos   (0U)
 
#define DBGMCU_IDCODE_DEV_ID_Msk   (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos)
 
#define DBGMCU_IDCODE_DEV_ID   DBGMCU_IDCODE_DEV_ID_Msk
 
#define DBGMCU_IDCODE_REV_ID_Pos   (16U)
 
#define DBGMCU_IDCODE_REV_ID_Msk   (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID   DBGMCU_IDCODE_REV_ID_Msk
 
#define DBGMCU_IDCODE_REV_ID_0   (0x0001U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_1   (0x0002U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_2   (0x0004U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_3   (0x0008U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_4   (0x0010U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_5   (0x0020U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_6   (0x0040U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_7   (0x0080U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_8   (0x0100U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_9   (0x0200U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_10   (0x0400U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_11   (0x0800U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_12   (0x1000U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_13   (0x2000U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_14   (0x4000U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_IDCODE_REV_ID_15   (0x8000U << DBGMCU_IDCODE_REV_ID_Pos)
 
#define DBGMCU_CR_DBG_SLEEP_Pos   (0U)
 
#define DBGMCU_CR_DBG_SLEEP_Msk   (0x1U << DBGMCU_CR_DBG_SLEEP_Pos)
 
#define DBGMCU_CR_DBG_SLEEP   DBGMCU_CR_DBG_SLEEP_Msk
 
#define DBGMCU_CR_DBG_STOP_Pos   (1U)
 
#define DBGMCU_CR_DBG_STOP_Msk   (0x1U << DBGMCU_CR_DBG_STOP_Pos)
 
#define DBGMCU_CR_DBG_STOP   DBGMCU_CR_DBG_STOP_Msk
 
#define DBGMCU_CR_DBG_STANDBY_Pos   (2U)
 
#define DBGMCU_CR_DBG_STANDBY_Msk   (0x1U << DBGMCU_CR_DBG_STANDBY_Pos)
 
#define DBGMCU_CR_DBG_STANDBY   DBGMCU_CR_DBG_STANDBY_Msk
 
#define DBGMCU_CR_TRACE_IOEN_Pos   (5U)
 
#define DBGMCU_CR_TRACE_IOEN_Msk   (0x1U << DBGMCU_CR_TRACE_IOEN_Pos)
 
#define DBGMCU_CR_TRACE_IOEN   DBGMCU_CR_TRACE_IOEN_Msk
 
#define DBGMCU_CR_TRACE_MODE_Pos   (6U)
 
#define DBGMCU_CR_TRACE_MODE_Msk   (0x3U << DBGMCU_CR_TRACE_MODE_Pos)
 
#define DBGMCU_CR_TRACE_MODE   DBGMCU_CR_TRACE_MODE_Msk
 
#define DBGMCU_CR_TRACE_MODE_0   (0x1U << DBGMCU_CR_TRACE_MODE_Pos)
 
#define DBGMCU_CR_TRACE_MODE_1   (0x2U << DBGMCU_CR_TRACE_MODE_Pos)
 
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos   (0U)
 
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)
 
#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk
 
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos   (1U)
 
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)
 
#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk
 
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos   (2U)
 
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)
 
#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk
 
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos   (3U)
 
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)
 
#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk
 
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos   (4U)
 
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)
 
#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk
 
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos   (5U)
 
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)
 
#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk
 
#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos   (10U)
 
#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)
 
#define DBGMCU_APB1_FZ_DBG_RTC_STOP   DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk
 
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos   (11U)
 
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)
 
#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk
 
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos   (12U)
 
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)
 
#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk
 
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos   (21U)
 
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)
 
#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk
 
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos   (22U)
 
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)
 
#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk
 
#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos   (2U)
 
#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk   (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)
 
#define DBGMCU_APB2_FZ_DBG_TIM9_STOP   DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk
 
#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos   (3U)
 
#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk   (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)
 
#define DBGMCU_APB2_FZ_DBG_TIM10_STOP   DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk
 
#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos   (4U)
 
#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk   (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)
 
#define DBGMCU_APB2_FZ_DBG_TIM11_STOP   DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk
 
#define DMA_ISR_GIF1_Pos   (0U)
 
#define DMA_ISR_GIF1_Msk   (0x1U << DMA_ISR_GIF1_Pos)
 
#define DMA_ISR_GIF1   DMA_ISR_GIF1_Msk
 
#define DMA_ISR_TCIF1_Pos   (1U)
 
#define DMA_ISR_TCIF1_Msk   (0x1U << DMA_ISR_TCIF1_Pos)
 
#define DMA_ISR_TCIF1   DMA_ISR_TCIF1_Msk
 
#define DMA_ISR_HTIF1_Pos   (2U)
 
#define DMA_ISR_HTIF1_Msk   (0x1U << DMA_ISR_HTIF1_Pos)
 
#define DMA_ISR_HTIF1   DMA_ISR_HTIF1_Msk
 
#define DMA_ISR_TEIF1_Pos   (3U)
 
#define DMA_ISR_TEIF1_Msk   (0x1U << DMA_ISR_TEIF1_Pos)
 
#define DMA_ISR_TEIF1   DMA_ISR_TEIF1_Msk
 
#define DMA_ISR_GIF2_Pos   (4U)
 
#define DMA_ISR_GIF2_Msk   (0x1U << DMA_ISR_GIF2_Pos)
 
#define DMA_ISR_GIF2   DMA_ISR_GIF2_Msk
 
#define DMA_ISR_TCIF2_Pos   (5U)
 
#define DMA_ISR_TCIF2_Msk   (0x1U << DMA_ISR_TCIF2_Pos)
 
#define DMA_ISR_TCIF2   DMA_ISR_TCIF2_Msk
 
#define DMA_ISR_HTIF2_Pos   (6U)
 
#define DMA_ISR_HTIF2_Msk   (0x1U << DMA_ISR_HTIF2_Pos)
 
#define DMA_ISR_HTIF2   DMA_ISR_HTIF2_Msk
 
#define DMA_ISR_TEIF2_Pos   (7U)
 
#define DMA_ISR_TEIF2_Msk   (0x1U << DMA_ISR_TEIF2_Pos)
 
#define DMA_ISR_TEIF2   DMA_ISR_TEIF2_Msk
 
#define DMA_ISR_GIF3_Pos   (8U)
 
#define DMA_ISR_GIF3_Msk   (0x1U << DMA_ISR_GIF3_Pos)
 
#define DMA_ISR_GIF3   DMA_ISR_GIF3_Msk
 
#define DMA_ISR_TCIF3_Pos   (9U)
 
#define DMA_ISR_TCIF3_Msk   (0x1U << DMA_ISR_TCIF3_Pos)
 
#define DMA_ISR_TCIF3   DMA_ISR_TCIF3_Msk
 
#define DMA_ISR_HTIF3_Pos   (10U)
 
#define DMA_ISR_HTIF3_Msk   (0x1U << DMA_ISR_HTIF3_Pos)
 
#define DMA_ISR_HTIF3   DMA_ISR_HTIF3_Msk
 
#define DMA_ISR_TEIF3_Pos   (11U)
 
#define DMA_ISR_TEIF3_Msk   (0x1U << DMA_ISR_TEIF3_Pos)
 
#define DMA_ISR_TEIF3   DMA_ISR_TEIF3_Msk
 
#define DMA_ISR_GIF4_Pos   (12U)
 
#define DMA_ISR_GIF4_Msk   (0x1U << DMA_ISR_GIF4_Pos)
 
#define DMA_ISR_GIF4   DMA_ISR_GIF4_Msk
 
#define DMA_ISR_TCIF4_Pos   (13U)
 
#define DMA_ISR_TCIF4_Msk   (0x1U << DMA_ISR_TCIF4_Pos)
 
#define DMA_ISR_TCIF4   DMA_ISR_TCIF4_Msk
 
#define DMA_ISR_HTIF4_Pos   (14U)
 
#define DMA_ISR_HTIF4_Msk   (0x1U << DMA_ISR_HTIF4_Pos)
 
#define DMA_ISR_HTIF4   DMA_ISR_HTIF4_Msk
 
#define DMA_ISR_TEIF4_Pos   (15U)
 
#define DMA_ISR_TEIF4_Msk   (0x1U << DMA_ISR_TEIF4_Pos)
 
#define DMA_ISR_TEIF4   DMA_ISR_TEIF4_Msk
 
#define DMA_ISR_GIF5_Pos   (16U)
 
#define DMA_ISR_GIF5_Msk   (0x1U << DMA_ISR_GIF5_Pos)
 
#define DMA_ISR_GIF5   DMA_ISR_GIF5_Msk
 
#define DMA_ISR_TCIF5_Pos   (17U)
 
#define DMA_ISR_TCIF5_Msk   (0x1U << DMA_ISR_TCIF5_Pos)
 
#define DMA_ISR_TCIF5   DMA_ISR_TCIF5_Msk
 
#define DMA_ISR_HTIF5_Pos   (18U)
 
#define DMA_ISR_HTIF5_Msk   (0x1U << DMA_ISR_HTIF5_Pos)
 
#define DMA_ISR_HTIF5   DMA_ISR_HTIF5_Msk
 
#define DMA_ISR_TEIF5_Pos   (19U)
 
#define DMA_ISR_TEIF5_Msk   (0x1U << DMA_ISR_TEIF5_Pos)
 
#define DMA_ISR_TEIF5   DMA_ISR_TEIF5_Msk
 
#define DMA_ISR_GIF6_Pos   (20U)
 
#define DMA_ISR_GIF6_Msk   (0x1U << DMA_ISR_GIF6_Pos)
 
#define DMA_ISR_GIF6   DMA_ISR_GIF6_Msk
 
#define DMA_ISR_TCIF6_Pos   (21U)
 
#define DMA_ISR_TCIF6_Msk   (0x1U << DMA_ISR_TCIF6_Pos)
 
#define DMA_ISR_TCIF6   DMA_ISR_TCIF6_Msk
 
#define DMA_ISR_HTIF6_Pos   (22U)
 
#define DMA_ISR_HTIF6_Msk   (0x1U << DMA_ISR_HTIF6_Pos)
 
#define DMA_ISR_HTIF6   DMA_ISR_HTIF6_Msk
 
#define DMA_ISR_TEIF6_Pos   (23U)
 
#define DMA_ISR_TEIF6_Msk   (0x1U << DMA_ISR_TEIF6_Pos)
 
#define DMA_ISR_TEIF6   DMA_ISR_TEIF6_Msk
 
#define DMA_ISR_GIF7_Pos   (24U)
 
#define DMA_ISR_GIF7_Msk   (0x1U << DMA_ISR_GIF7_Pos)
 
#define DMA_ISR_GIF7   DMA_ISR_GIF7_Msk
 
#define DMA_ISR_TCIF7_Pos   (25U)
 
#define DMA_ISR_TCIF7_Msk   (0x1U << DMA_ISR_TCIF7_Pos)
 
#define DMA_ISR_TCIF7   DMA_ISR_TCIF7_Msk
 
#define DMA_ISR_HTIF7_Pos   (26U)
 
#define DMA_ISR_HTIF7_Msk   (0x1U << DMA_ISR_HTIF7_Pos)
 
#define DMA_ISR_HTIF7   DMA_ISR_HTIF7_Msk
 
#define DMA_ISR_TEIF7_Pos   (27U)
 
#define DMA_ISR_TEIF7_Msk   (0x1U << DMA_ISR_TEIF7_Pos)
 
#define DMA_ISR_TEIF7   DMA_ISR_TEIF7_Msk
 
#define DMA_IFCR_CGIF1_Pos   (0U)
 
#define DMA_IFCR_CGIF1_Msk   (0x1U << DMA_IFCR_CGIF1_Pos)
 
#define DMA_IFCR_CGIF1   DMA_IFCR_CGIF1_Msk
 
#define DMA_IFCR_CTCIF1_Pos   (1U)
 
#define DMA_IFCR_CTCIF1_Msk   (0x1U << DMA_IFCR_CTCIF1_Pos)
 
#define DMA_IFCR_CTCIF1   DMA_IFCR_CTCIF1_Msk
 
#define DMA_IFCR_CHTIF1_Pos   (2U)
 
#define DMA_IFCR_CHTIF1_Msk   (0x1U << DMA_IFCR_CHTIF1_Pos)
 
#define DMA_IFCR_CHTIF1   DMA_IFCR_CHTIF1_Msk
 
#define DMA_IFCR_CTEIF1_Pos   (3U)
 
#define DMA_IFCR_CTEIF1_Msk   (0x1U << DMA_IFCR_CTEIF1_Pos)
 
#define DMA_IFCR_CTEIF1   DMA_IFCR_CTEIF1_Msk
 
#define DMA_IFCR_CGIF2_Pos   (4U)
 
#define DMA_IFCR_CGIF2_Msk   (0x1U << DMA_IFCR_CGIF2_Pos)
 
#define DMA_IFCR_CGIF2   DMA_IFCR_CGIF2_Msk
 
#define DMA_IFCR_CTCIF2_Pos   (5U)
 
#define DMA_IFCR_CTCIF2_Msk   (0x1U << DMA_IFCR_CTCIF2_Pos)
 
#define DMA_IFCR_CTCIF2   DMA_IFCR_CTCIF2_Msk
 
#define DMA_IFCR_CHTIF2_Pos   (6U)
 
#define DMA_IFCR_CHTIF2_Msk   (0x1U << DMA_IFCR_CHTIF2_Pos)
 
#define DMA_IFCR_CHTIF2   DMA_IFCR_CHTIF2_Msk
 
#define DMA_IFCR_CTEIF2_Pos   (7U)
 
#define DMA_IFCR_CTEIF2_Msk   (0x1U << DMA_IFCR_CTEIF2_Pos)
 
#define DMA_IFCR_CTEIF2   DMA_IFCR_CTEIF2_Msk
 
#define DMA_IFCR_CGIF3_Pos   (8U)
 
#define DMA_IFCR_CGIF3_Msk   (0x1U << DMA_IFCR_CGIF3_Pos)
 
#define DMA_IFCR_CGIF3   DMA_IFCR_CGIF3_Msk
 
#define DMA_IFCR_CTCIF3_Pos   (9U)
 
#define DMA_IFCR_CTCIF3_Msk   (0x1U << DMA_IFCR_CTCIF3_Pos)
 
#define DMA_IFCR_CTCIF3   DMA_IFCR_CTCIF3_Msk
 
#define DMA_IFCR_CHTIF3_Pos   (10U)
 
#define DMA_IFCR_CHTIF3_Msk   (0x1U << DMA_IFCR_CHTIF3_Pos)
 
#define DMA_IFCR_CHTIF3   DMA_IFCR_CHTIF3_Msk
 
#define DMA_IFCR_CTEIF3_Pos   (11U)
 
#define DMA_IFCR_CTEIF3_Msk   (0x1U << DMA_IFCR_CTEIF3_Pos)
 
#define DMA_IFCR_CTEIF3   DMA_IFCR_CTEIF3_Msk
 
#define DMA_IFCR_CGIF4_Pos   (12U)
 
#define DMA_IFCR_CGIF4_Msk   (0x1U << DMA_IFCR_CGIF4_Pos)
 
#define DMA_IFCR_CGIF4   DMA_IFCR_CGIF4_Msk
 
#define DMA_IFCR_CTCIF4_Pos   (13U)
 
#define DMA_IFCR_CTCIF4_Msk   (0x1U << DMA_IFCR_CTCIF4_Pos)
 
#define DMA_IFCR_CTCIF4   DMA_IFCR_CTCIF4_Msk
 
#define DMA_IFCR_CHTIF4_Pos   (14U)
 
#define DMA_IFCR_CHTIF4_Msk   (0x1U << DMA_IFCR_CHTIF4_Pos)
 
#define DMA_IFCR_CHTIF4   DMA_IFCR_CHTIF4_Msk
 
#define DMA_IFCR_CTEIF4_Pos   (15U)
 
#define DMA_IFCR_CTEIF4_Msk   (0x1U << DMA_IFCR_CTEIF4_Pos)
 
#define DMA_IFCR_CTEIF4   DMA_IFCR_CTEIF4_Msk
 
#define DMA_IFCR_CGIF5_Pos   (16U)
 
#define DMA_IFCR_CGIF5_Msk   (0x1U << DMA_IFCR_CGIF5_Pos)
 
#define DMA_IFCR_CGIF5   DMA_IFCR_CGIF5_Msk
 
#define DMA_IFCR_CTCIF5_Pos   (17U)
 
#define DMA_IFCR_CTCIF5_Msk   (0x1U << DMA_IFCR_CTCIF5_Pos)
 
#define DMA_IFCR_CTCIF5   DMA_IFCR_CTCIF5_Msk
 
#define DMA_IFCR_CHTIF5_Pos   (18U)
 
#define DMA_IFCR_CHTIF5_Msk   (0x1U << DMA_IFCR_CHTIF5_Pos)
 
#define DMA_IFCR_CHTIF5   DMA_IFCR_CHTIF5_Msk
 
#define DMA_IFCR_CTEIF5_Pos   (19U)
 
#define DMA_IFCR_CTEIF5_Msk   (0x1U << DMA_IFCR_CTEIF5_Pos)
 
#define DMA_IFCR_CTEIF5   DMA_IFCR_CTEIF5_Msk
 
#define DMA_IFCR_CGIF6_Pos   (20U)
 
#define DMA_IFCR_CGIF6_Msk   (0x1U << DMA_IFCR_CGIF6_Pos)
 
#define DMA_IFCR_CGIF6   DMA_IFCR_CGIF6_Msk
 
#define DMA_IFCR_CTCIF6_Pos   (21U)
 
#define DMA_IFCR_CTCIF6_Msk   (0x1U << DMA_IFCR_CTCIF6_Pos)
 
#define DMA_IFCR_CTCIF6   DMA_IFCR_CTCIF6_Msk
 
#define DMA_IFCR_CHTIF6_Pos   (22U)
 
#define DMA_IFCR_CHTIF6_Msk   (0x1U << DMA_IFCR_CHTIF6_Pos)
 
#define DMA_IFCR_CHTIF6   DMA_IFCR_CHTIF6_Msk
 
#define DMA_IFCR_CTEIF6_Pos   (23U)
 
#define DMA_IFCR_CTEIF6_Msk   (0x1U << DMA_IFCR_CTEIF6_Pos)
 
#define DMA_IFCR_CTEIF6   DMA_IFCR_CTEIF6_Msk
 
#define DMA_IFCR_CGIF7_Pos   (24U)
 
#define DMA_IFCR_CGIF7_Msk   (0x1U << DMA_IFCR_CGIF7_Pos)
 
#define DMA_IFCR_CGIF7   DMA_IFCR_CGIF7_Msk
 
#define DMA_IFCR_CTCIF7_Pos   (25U)
 
#define DMA_IFCR_CTCIF7_Msk   (0x1U << DMA_IFCR_CTCIF7_Pos)
 
#define DMA_IFCR_CTCIF7   DMA_IFCR_CTCIF7_Msk
 
#define DMA_IFCR_CHTIF7_Pos   (26U)
 
#define DMA_IFCR_CHTIF7_Msk   (0x1U << DMA_IFCR_CHTIF7_Pos)
 
#define DMA_IFCR_CHTIF7   DMA_IFCR_CHTIF7_Msk
 
#define DMA_IFCR_CTEIF7_Pos   (27U)
 
#define DMA_IFCR_CTEIF7_Msk   (0x1U << DMA_IFCR_CTEIF7_Pos)
 
#define DMA_IFCR_CTEIF7   DMA_IFCR_CTEIF7_Msk
 
#define DMA_CCR_EN_Pos   (0U)
 
#define DMA_CCR_EN_Msk   (0x1U << DMA_CCR_EN_Pos)
 
#define DMA_CCR_EN   DMA_CCR_EN_Msk
 
#define DMA_CCR_TCIE_Pos   (1U)
 
#define DMA_CCR_TCIE_Msk   (0x1U << DMA_CCR_TCIE_Pos)
 
#define DMA_CCR_TCIE   DMA_CCR_TCIE_Msk
 
#define DMA_CCR_HTIE_Pos   (2U)
 
#define DMA_CCR_HTIE_Msk   (0x1U << DMA_CCR_HTIE_Pos)
 
#define DMA_CCR_HTIE   DMA_CCR_HTIE_Msk
 
#define DMA_CCR_TEIE_Pos   (3U)
 
#define DMA_CCR_TEIE_Msk   (0x1U << DMA_CCR_TEIE_Pos)
 
#define DMA_CCR_TEIE   DMA_CCR_TEIE_Msk
 
#define DMA_CCR_DIR_Pos   (4U)
 
#define DMA_CCR_DIR_Msk   (0x1U << DMA_CCR_DIR_Pos)
 
#define DMA_CCR_DIR   DMA_CCR_DIR_Msk
 
#define DMA_CCR_CIRC_Pos   (5U)
 
#define DMA_CCR_CIRC_Msk   (0x1U << DMA_CCR_CIRC_Pos)
 
#define DMA_CCR_CIRC   DMA_CCR_CIRC_Msk
 
#define DMA_CCR_PINC_Pos   (6U)
 
#define DMA_CCR_PINC_Msk   (0x1U << DMA_CCR_PINC_Pos)
 
#define DMA_CCR_PINC   DMA_CCR_PINC_Msk
 
#define DMA_CCR_MINC_Pos   (7U)
 
#define DMA_CCR_MINC_Msk   (0x1U << DMA_CCR_MINC_Pos)
 
#define DMA_CCR_MINC   DMA_CCR_MINC_Msk
 
#define DMA_CCR_PSIZE_Pos   (8U)
 
#define DMA_CCR_PSIZE_Msk   (0x3U << DMA_CCR_PSIZE_Pos)
 
#define DMA_CCR_PSIZE   DMA_CCR_PSIZE_Msk
 
#define DMA_CCR_PSIZE_0   (0x1U << DMA_CCR_PSIZE_Pos)
 
#define DMA_CCR_PSIZE_1   (0x2U << DMA_CCR_PSIZE_Pos)
 
#define DMA_CCR_MSIZE_Pos   (10U)
 
#define DMA_CCR_MSIZE_Msk   (0x3U << DMA_CCR_MSIZE_Pos)
 
#define DMA_CCR_MSIZE   DMA_CCR_MSIZE_Msk
 
#define DMA_CCR_MSIZE_0   (0x1U << DMA_CCR_MSIZE_Pos)
 
#define DMA_CCR_MSIZE_1   (0x2U << DMA_CCR_MSIZE_Pos)
 
#define DMA_CCR_PL_Pos   (12U)
 
#define DMA_CCR_PL_Msk   (0x3U << DMA_CCR_PL_Pos)
 
#define DMA_CCR_PL   DMA_CCR_PL_Msk
 
#define DMA_CCR_PL_0   (0x1U << DMA_CCR_PL_Pos)
 
#define DMA_CCR_PL_1   (0x2U << DMA_CCR_PL_Pos)
 
#define DMA_CCR_MEM2MEM_Pos   (14U)
 
#define DMA_CCR_MEM2MEM_Msk   (0x1U << DMA_CCR_MEM2MEM_Pos)
 
#define DMA_CCR_MEM2MEM   DMA_CCR_MEM2MEM_Msk
 
#define DMA_CNDTR_NDT_Pos   (0U)
 
#define DMA_CNDTR_NDT_Msk   (0xFFFFU << DMA_CNDTR_NDT_Pos)
 
#define DMA_CNDTR_NDT   DMA_CNDTR_NDT_Msk
 
#define DMA_CNDTR1_NDT_Pos   (0U)
 
#define DMA_CNDTR1_NDT_Msk   (0xFFFFU << DMA_CNDTR1_NDT_Pos)
 
#define DMA_CNDTR1_NDT   DMA_CNDTR1_NDT_Msk
 
#define DMA_CNDTR2_NDT_Pos   (0U)
 
#define DMA_CNDTR2_NDT_Msk   (0xFFFFU << DMA_CNDTR2_NDT_Pos)
 
#define DMA_CNDTR2_NDT   DMA_CNDTR2_NDT_Msk
 
#define DMA_CNDTR3_NDT_Pos   (0U)
 
#define DMA_CNDTR3_NDT_Msk   (0xFFFFU << DMA_CNDTR3_NDT_Pos)
 
#define DMA_CNDTR3_NDT   DMA_CNDTR3_NDT_Msk
 
#define DMA_CNDTR4_NDT_Pos   (0U)
 
#define DMA_CNDTR4_NDT_Msk   (0xFFFFU << DMA_CNDTR4_NDT_Pos)
 
#define DMA_CNDTR4_NDT   DMA_CNDTR4_NDT_Msk
 
#define DMA_CNDTR5_NDT_Pos   (0U)
 
#define DMA_CNDTR5_NDT_Msk   (0xFFFFU << DMA_CNDTR5_NDT_Pos)
 
#define DMA_CNDTR5_NDT   DMA_CNDTR5_NDT_Msk
 
#define DMA_CNDTR6_NDT_Pos   (0U)
 
#define DMA_CNDTR6_NDT_Msk   (0xFFFFU << DMA_CNDTR6_NDT_Pos)
 
#define DMA_CNDTR6_NDT   DMA_CNDTR6_NDT_Msk
 
#define DMA_CNDTR7_NDT_Pos   (0U)
 
#define DMA_CNDTR7_NDT_Msk   (0xFFFFU << DMA_CNDTR7_NDT_Pos)
 
#define DMA_CNDTR7_NDT   DMA_CNDTR7_NDT_Msk
 
#define DMA_CPAR_PA_Pos   (0U)
 
#define DMA_CPAR_PA_Msk   (0xFFFFFFFFU << DMA_CPAR_PA_Pos)
 
#define DMA_CPAR_PA   DMA_CPAR_PA_Msk
 
#define DMA_CPAR1_PA_Pos   (0U)
 
#define DMA_CPAR1_PA_Msk   (0xFFFFFFFFU << DMA_CPAR1_PA_Pos)
 
#define DMA_CPAR1_PA   DMA_CPAR1_PA_Msk
 
#define DMA_CPAR2_PA_Pos   (0U)
 
#define DMA_CPAR2_PA_Msk   (0xFFFFFFFFU << DMA_CPAR2_PA_Pos)
 
#define DMA_CPAR2_PA   DMA_CPAR2_PA_Msk
 
#define DMA_CPAR3_PA_Pos   (0U)
 
#define DMA_CPAR3_PA_Msk   (0xFFFFFFFFU << DMA_CPAR3_PA_Pos)
 
#define DMA_CPAR3_PA   DMA_CPAR3_PA_Msk
 
#define DMA_CPAR4_PA_Pos   (0U)
 
#define DMA_CPAR4_PA_Msk   (0xFFFFFFFFU << DMA_CPAR4_PA_Pos)
 
#define DMA_CPAR4_PA   DMA_CPAR4_PA_Msk
 
#define DMA_CPAR5_PA_Pos   (0U)
 
#define DMA_CPAR5_PA_Msk   (0xFFFFFFFFU << DMA_CPAR5_PA_Pos)
 
#define DMA_CPAR5_PA   DMA_CPAR5_PA_Msk
 
#define DMA_CPAR6_PA_Pos   (0U)
 
#define DMA_CPAR6_PA_Msk   (0xFFFFFFFFU << DMA_CPAR6_PA_Pos)
 
#define DMA_CPAR6_PA   DMA_CPAR6_PA_Msk
 
#define DMA_CPAR7_PA_Pos   (0U)
 
#define DMA_CPAR7_PA_Msk   (0xFFFFFFFFU << DMA_CPAR7_PA_Pos)
 
#define DMA_CPAR7_PA   DMA_CPAR7_PA_Msk
 
#define DMA_CMAR_MA_Pos   (0U)
 
#define DMA_CMAR_MA_Msk   (0xFFFFFFFFU << DMA_CMAR_MA_Pos)
 
#define DMA_CMAR_MA   DMA_CMAR_MA_Msk
 
#define DMA_CMAR1_MA_Pos   (0U)
 
#define DMA_CMAR1_MA_Msk   (0xFFFFFFFFU << DMA_CMAR1_MA_Pos)
 
#define DMA_CMAR1_MA   DMA_CMAR1_MA_Msk
 
#define DMA_CMAR2_MA_Pos   (0U)
 
#define DMA_CMAR2_MA_Msk   (0xFFFFFFFFU << DMA_CMAR2_MA_Pos)
 
#define DMA_CMAR2_MA   DMA_CMAR2_MA_Msk
 
#define DMA_CMAR3_MA_Pos   (0U)
 
#define DMA_CMAR3_MA_Msk   (0xFFFFFFFFU << DMA_CMAR3_MA_Pos)
 
#define DMA_CMAR3_MA   DMA_CMAR3_MA_Msk
 
#define DMA_CMAR4_MA_Pos   (0U)
 
#define DMA_CMAR4_MA_Msk   (0xFFFFFFFFU << DMA_CMAR4_MA_Pos)
 
#define DMA_CMAR4_MA   DMA_CMAR4_MA_Msk
 
#define DMA_CMAR5_MA_Pos   (0U)
 
#define DMA_CMAR5_MA_Msk   (0xFFFFFFFFU << DMA_CMAR5_MA_Pos)
 
#define DMA_CMAR5_MA   DMA_CMAR5_MA_Msk
 
#define DMA_CMAR6_MA_Pos   (0U)
 
#define DMA_CMAR6_MA_Msk   (0xFFFFFFFFU << DMA_CMAR6_MA_Pos)
 
#define DMA_CMAR6_MA   DMA_CMAR6_MA_Msk
 
#define DMA_CMAR7_MA_Pos   (0U)
 
#define DMA_CMAR7_MA_Msk   (0xFFFFFFFFU << DMA_CMAR7_MA_Pos)
 
#define DMA_CMAR7_MA   DMA_CMAR7_MA_Msk
 
#define EXTI_IMR_MR0_Pos   (0U)
 
#define EXTI_IMR_MR0_Msk   (0x1U << EXTI_IMR_MR0_Pos)
 
#define EXTI_IMR_MR0   EXTI_IMR_MR0_Msk
 
#define EXTI_IMR_MR1_Pos   (1U)
 
#define EXTI_IMR_MR1_Msk   (0x1U << EXTI_IMR_MR1_Pos)
 
#define EXTI_IMR_MR1   EXTI_IMR_MR1_Msk
 
#define EXTI_IMR_MR2_Pos   (2U)
 
#define EXTI_IMR_MR2_Msk   (0x1U << EXTI_IMR_MR2_Pos)
 
#define EXTI_IMR_MR2   EXTI_IMR_MR2_Msk
 
#define EXTI_IMR_MR3_Pos   (3U)
 
#define EXTI_IMR_MR3_Msk   (0x1U << EXTI_IMR_MR3_Pos)
 
#define EXTI_IMR_MR3   EXTI_IMR_MR3_Msk
 
#define EXTI_IMR_MR4_Pos   (4U)
 
#define EXTI_IMR_MR4_Msk   (0x1U << EXTI_IMR_MR4_Pos)
 
#define EXTI_IMR_MR4   EXTI_IMR_MR4_Msk
 
#define EXTI_IMR_MR5_Pos   (5U)
 
#define EXTI_IMR_MR5_Msk   (0x1U << EXTI_IMR_MR5_Pos)
 
#define EXTI_IMR_MR5   EXTI_IMR_MR5_Msk
 
#define EXTI_IMR_MR6_Pos   (6U)
 
#define EXTI_IMR_MR6_Msk   (0x1U << EXTI_IMR_MR6_Pos)
 
#define EXTI_IMR_MR6   EXTI_IMR_MR6_Msk
 
#define EXTI_IMR_MR7_Pos   (7U)
 
#define EXTI_IMR_MR7_Msk   (0x1U << EXTI_IMR_MR7_Pos)
 
#define EXTI_IMR_MR7   EXTI_IMR_MR7_Msk
 
#define EXTI_IMR_MR8_Pos   (8U)
 
#define EXTI_IMR_MR8_Msk   (0x1U << EXTI_IMR_MR8_Pos)
 
#define EXTI_IMR_MR8   EXTI_IMR_MR8_Msk
 
#define EXTI_IMR_MR9_Pos   (9U)
 
#define EXTI_IMR_MR9_Msk   (0x1U << EXTI_IMR_MR9_Pos)
 
#define EXTI_IMR_MR9   EXTI_IMR_MR9_Msk
 
#define EXTI_IMR_MR10_Pos   (10U)
 
#define EXTI_IMR_MR10_Msk   (0x1U << EXTI_IMR_MR10_Pos)
 
#define EXTI_IMR_MR10   EXTI_IMR_MR10_Msk
 
#define EXTI_IMR_MR11_Pos   (11U)
 
#define EXTI_IMR_MR11_Msk   (0x1U << EXTI_IMR_MR11_Pos)
 
#define EXTI_IMR_MR11   EXTI_IMR_MR11_Msk
 
#define EXTI_IMR_MR12_Pos   (12U)
 
#define EXTI_IMR_MR12_Msk   (0x1U << EXTI_IMR_MR12_Pos)
 
#define EXTI_IMR_MR12   EXTI_IMR_MR12_Msk
 
#define EXTI_IMR_MR13_Pos   (13U)
 
#define EXTI_IMR_MR13_Msk   (0x1U << EXTI_IMR_MR13_Pos)
 
#define EXTI_IMR_MR13   EXTI_IMR_MR13_Msk
 
#define EXTI_IMR_MR14_Pos   (14U)
 
#define EXTI_IMR_MR14_Msk   (0x1U << EXTI_IMR_MR14_Pos)
 
#define EXTI_IMR_MR14   EXTI_IMR_MR14_Msk
 
#define EXTI_IMR_MR15_Pos   (15U)
 
#define EXTI_IMR_MR15_Msk   (0x1U << EXTI_IMR_MR15_Pos)
 
#define EXTI_IMR_MR15   EXTI_IMR_MR15_Msk
 
#define EXTI_IMR_MR16_Pos   (16U)
 
#define EXTI_IMR_MR16_Msk   (0x1U << EXTI_IMR_MR16_Pos)
 
#define EXTI_IMR_MR16   EXTI_IMR_MR16_Msk
 
#define EXTI_IMR_MR17_Pos   (17U)
 
#define EXTI_IMR_MR17_Msk   (0x1U << EXTI_IMR_MR17_Pos)
 
#define EXTI_IMR_MR17   EXTI_IMR_MR17_Msk
 
#define EXTI_IMR_MR18_Pos   (18U)
 
#define EXTI_IMR_MR18_Msk   (0x1U << EXTI_IMR_MR18_Pos)
 
#define EXTI_IMR_MR18   EXTI_IMR_MR18_Msk
 
#define EXTI_IMR_MR19_Pos   (19U)
 
#define EXTI_IMR_MR19_Msk   (0x1U << EXTI_IMR_MR19_Pos)
 
#define EXTI_IMR_MR19   EXTI_IMR_MR19_Msk
 
#define EXTI_IMR_MR20_Pos   (20U)
 
#define EXTI_IMR_MR20_Msk   (0x1U << EXTI_IMR_MR20_Pos)
 
#define EXTI_IMR_MR20   EXTI_IMR_MR20_Msk
 
#define EXTI_IMR_MR21_Pos   (21U)
 
#define EXTI_IMR_MR21_Msk   (0x1U << EXTI_IMR_MR21_Pos)
 
#define EXTI_IMR_MR21   EXTI_IMR_MR21_Msk
 
#define EXTI_IMR_MR22_Pos   (22U)
 
#define EXTI_IMR_MR22_Msk   (0x1U << EXTI_IMR_MR22_Pos)
 
#define EXTI_IMR_MR22   EXTI_IMR_MR22_Msk
 
#define EXTI_IMR_MR23_Pos   (23U)
 
#define EXTI_IMR_MR23_Msk   (0x1U << EXTI_IMR_MR23_Pos)
 
#define EXTI_IMR_MR23   EXTI_IMR_MR23_Msk
 
#define EXTI_IMR_IM0   EXTI_IMR_MR0
 
#define EXTI_IMR_IM1   EXTI_IMR_MR1
 
#define EXTI_IMR_IM2   EXTI_IMR_MR2
 
#define EXTI_IMR_IM3   EXTI_IMR_MR3
 
#define EXTI_IMR_IM4   EXTI_IMR_MR4
 
#define EXTI_IMR_IM5   EXTI_IMR_MR5
 
#define EXTI_IMR_IM6   EXTI_IMR_MR6
 
#define EXTI_IMR_IM7   EXTI_IMR_MR7
 
#define EXTI_IMR_IM8   EXTI_IMR_MR8
 
#define EXTI_IMR_IM9   EXTI_IMR_MR9
 
#define EXTI_IMR_IM10   EXTI_IMR_MR10
 
#define EXTI_IMR_IM11   EXTI_IMR_MR11
 
#define EXTI_IMR_IM12   EXTI_IMR_MR12
 
#define EXTI_IMR_IM13   EXTI_IMR_MR13
 
#define EXTI_IMR_IM14   EXTI_IMR_MR14
 
#define EXTI_IMR_IM15   EXTI_IMR_MR15
 
#define EXTI_IMR_IM16   EXTI_IMR_MR16
 
#define EXTI_IMR_IM17   EXTI_IMR_MR17
 
#define EXTI_IMR_IM18   EXTI_IMR_MR18
 
#define EXTI_IMR_IM19   EXTI_IMR_MR19
 
#define EXTI_IMR_IM20   EXTI_IMR_MR20
 
#define EXTI_IMR_IM21   EXTI_IMR_MR21
 
#define EXTI_IMR_IM22   EXTI_IMR_MR22
 
#define EXTI_IMR_IM23   EXTI_IMR_MR23
 
#define EXTI_IMR_IM_Pos   (0U)
 
#define EXTI_IMR_IM_Msk   (0xFFFFFFU << EXTI_IMR_IM_Pos)
 
#define EXTI_IMR_IM   EXTI_IMR_IM_Msk
 
#define EXTI_EMR_MR0_Pos   (0U)
 
#define EXTI_EMR_MR0_Msk   (0x1U << EXTI_EMR_MR0_Pos)
 
#define EXTI_EMR_MR0   EXTI_EMR_MR0_Msk
 
#define EXTI_EMR_MR1_Pos   (1U)
 
#define EXTI_EMR_MR1_Msk   (0x1U << EXTI_EMR_MR1_Pos)
 
#define EXTI_EMR_MR1   EXTI_EMR_MR1_Msk
 
#define EXTI_EMR_MR2_Pos   (2U)
 
#define EXTI_EMR_MR2_Msk   (0x1U << EXTI_EMR_MR2_Pos)
 
#define EXTI_EMR_MR2   EXTI_EMR_MR2_Msk
 
#define EXTI_EMR_MR3_Pos   (3U)
 
#define EXTI_EMR_MR3_Msk   (0x1U << EXTI_EMR_MR3_Pos)
 
#define EXTI_EMR_MR3   EXTI_EMR_MR3_Msk
 
#define EXTI_EMR_MR4_Pos   (4U)
 
#define EXTI_EMR_MR4_Msk   (0x1U << EXTI_EMR_MR4_Pos)
 
#define EXTI_EMR_MR4   EXTI_EMR_MR4_Msk
 
#define EXTI_EMR_MR5_Pos   (5U)
 
#define EXTI_EMR_MR5_Msk   (0x1U << EXTI_EMR_MR5_Pos)
 
#define EXTI_EMR_MR5   EXTI_EMR_MR5_Msk
 
#define EXTI_EMR_MR6_Pos   (6U)
 
#define EXTI_EMR_MR6_Msk   (0x1U << EXTI_EMR_MR6_Pos)
 
#define EXTI_EMR_MR6   EXTI_EMR_MR6_Msk
 
#define EXTI_EMR_MR7_Pos   (7U)
 
#define EXTI_EMR_MR7_Msk   (0x1U << EXTI_EMR_MR7_Pos)
 
#define EXTI_EMR_MR7   EXTI_EMR_MR7_Msk
 
#define EXTI_EMR_MR8_Pos   (8U)
 
#define EXTI_EMR_MR8_Msk   (0x1U << EXTI_EMR_MR8_Pos)
 
#define EXTI_EMR_MR8   EXTI_EMR_MR8_Msk
 
#define EXTI_EMR_MR9_Pos   (9U)
 
#define EXTI_EMR_MR9_Msk   (0x1U << EXTI_EMR_MR9_Pos)
 
#define EXTI_EMR_MR9   EXTI_EMR_MR9_Msk
 
#define EXTI_EMR_MR10_Pos   (10U)
 
#define EXTI_EMR_MR10_Msk   (0x1U << EXTI_EMR_MR10_Pos)
 
#define EXTI_EMR_MR10   EXTI_EMR_MR10_Msk
 
#define EXTI_EMR_MR11_Pos   (11U)
 
#define EXTI_EMR_MR11_Msk   (0x1U << EXTI_EMR_MR11_Pos)
 
#define EXTI_EMR_MR11   EXTI_EMR_MR11_Msk
 
#define EXTI_EMR_MR12_Pos   (12U)
 
#define EXTI_EMR_MR12_Msk   (0x1U << EXTI_EMR_MR12_Pos)
 
#define EXTI_EMR_MR12   EXTI_EMR_MR12_Msk
 
#define EXTI_EMR_MR13_Pos   (13U)
 
#define EXTI_EMR_MR13_Msk   (0x1U << EXTI_EMR_MR13_Pos)
 
#define EXTI_EMR_MR13   EXTI_EMR_MR13_Msk
 
#define EXTI_EMR_MR14_Pos   (14U)
 
#define EXTI_EMR_MR14_Msk   (0x1U << EXTI_EMR_MR14_Pos)
 
#define EXTI_EMR_MR14   EXTI_EMR_MR14_Msk
 
#define EXTI_EMR_MR15_Pos   (15U)
 
#define EXTI_EMR_MR15_Msk   (0x1U << EXTI_EMR_MR15_Pos)
 
#define EXTI_EMR_MR15   EXTI_EMR_MR15_Msk
 
#define EXTI_EMR_MR16_Pos   (16U)
 
#define EXTI_EMR_MR16_Msk   (0x1U << EXTI_EMR_MR16_Pos)
 
#define EXTI_EMR_MR16   EXTI_EMR_MR16_Msk
 
#define EXTI_EMR_MR17_Pos   (17U)
 
#define EXTI_EMR_MR17_Msk   (0x1U << EXTI_EMR_MR17_Pos)
 
#define EXTI_EMR_MR17   EXTI_EMR_MR17_Msk
 
#define EXTI_EMR_MR18_Pos   (18U)
 
#define EXTI_EMR_MR18_Msk   (0x1U << EXTI_EMR_MR18_Pos)
 
#define EXTI_EMR_MR18   EXTI_EMR_MR18_Msk
 
#define EXTI_EMR_MR19_Pos   (19U)
 
#define EXTI_EMR_MR19_Msk   (0x1U << EXTI_EMR_MR19_Pos)
 
#define EXTI_EMR_MR19   EXTI_EMR_MR19_Msk
 
#define EXTI_EMR_MR20_Pos   (20U)
 
#define EXTI_EMR_MR20_Msk   (0x1U << EXTI_EMR_MR20_Pos)
 
#define EXTI_EMR_MR20   EXTI_EMR_MR20_Msk
 
#define EXTI_EMR_MR21_Pos   (21U)
 
#define EXTI_EMR_MR21_Msk   (0x1U << EXTI_EMR_MR21_Pos)
 
#define EXTI_EMR_MR21   EXTI_EMR_MR21_Msk
 
#define EXTI_EMR_MR22_Pos   (22U)
 
#define EXTI_EMR_MR22_Msk   (0x1U << EXTI_EMR_MR22_Pos)
 
#define EXTI_EMR_MR22   EXTI_EMR_MR22_Msk
 
#define EXTI_EMR_MR23_Pos   (23U)
 
#define EXTI_EMR_MR23_Msk   (0x1U << EXTI_EMR_MR23_Pos)
 
#define EXTI_EMR_MR23   EXTI_EMR_MR23_Msk
 
#define EXTI_EMR_EM0   EXTI_EMR_MR0
 
#define EXTI_EMR_EM1   EXTI_EMR_MR1
 
#define EXTI_EMR_EM2   EXTI_EMR_MR2
 
#define EXTI_EMR_EM3   EXTI_EMR_MR3
 
#define EXTI_EMR_EM4   EXTI_EMR_MR4
 
#define EXTI_EMR_EM5   EXTI_EMR_MR5
 
#define EXTI_EMR_EM6   EXTI_EMR_MR6
 
#define EXTI_EMR_EM7   EXTI_EMR_MR7
 
#define EXTI_EMR_EM8   EXTI_EMR_MR8
 
#define EXTI_EMR_EM9   EXTI_EMR_MR9
 
#define EXTI_EMR_EM10   EXTI_EMR_MR10
 
#define EXTI_EMR_EM11   EXTI_EMR_MR11
 
#define EXTI_EMR_EM12   EXTI_EMR_MR12
 
#define EXTI_EMR_EM13   EXTI_EMR_MR13
 
#define EXTI_EMR_EM14   EXTI_EMR_MR14
 
#define EXTI_EMR_EM15   EXTI_EMR_MR15
 
#define EXTI_EMR_EM16   EXTI_EMR_MR16
 
#define EXTI_EMR_EM17   EXTI_EMR_MR17
 
#define EXTI_EMR_EM18   EXTI_EMR_MR18
 
#define EXTI_EMR_EM19   EXTI_EMR_MR19
 
#define EXTI_EMR_EM20   EXTI_EMR_MR20
 
#define EXTI_EMR_EM21   EXTI_EMR_MR21
 
#define EXTI_EMR_EM22   EXTI_EMR_MR22
 
#define EXTI_EMR_EM23   EXTI_EMR_MR23
 
#define EXTI_RTSR_TR0_Pos   (0U)
 
#define EXTI_RTSR_TR0_Msk   (0x1U << EXTI_RTSR_TR0_Pos)
 
#define EXTI_RTSR_TR0   EXTI_RTSR_TR0_Msk
 
#define EXTI_RTSR_TR1_Pos   (1U)
 
#define EXTI_RTSR_TR1_Msk   (0x1U << EXTI_RTSR_TR1_Pos)
 
#define EXTI_RTSR_TR1   EXTI_RTSR_TR1_Msk
 
#define EXTI_RTSR_TR2_Pos   (2U)
 
#define EXTI_RTSR_TR2_Msk   (0x1U << EXTI_RTSR_TR2_Pos)
 
#define EXTI_RTSR_TR2   EXTI_RTSR_TR2_Msk
 
#define EXTI_RTSR_TR3_Pos   (3U)
 
#define EXTI_RTSR_TR3_Msk   (0x1U << EXTI_RTSR_TR3_Pos)
 
#define EXTI_RTSR_TR3   EXTI_RTSR_TR3_Msk
 
#define EXTI_RTSR_TR4_Pos   (4U)
 
#define EXTI_RTSR_TR4_Msk   (0x1U << EXTI_RTSR_TR4_Pos)
 
#define EXTI_RTSR_TR4   EXTI_RTSR_TR4_Msk
 
#define EXTI_RTSR_TR5_Pos   (5U)
 
#define EXTI_RTSR_TR5_Msk   (0x1U << EXTI_RTSR_TR5_Pos)
 
#define EXTI_RTSR_TR5   EXTI_RTSR_TR5_Msk
 
#define EXTI_RTSR_TR6_Pos   (6U)
 
#define EXTI_RTSR_TR6_Msk   (0x1U << EXTI_RTSR_TR6_Pos)
 
#define EXTI_RTSR_TR6   EXTI_RTSR_TR6_Msk
 
#define EXTI_RTSR_TR7_Pos   (7U)
 
#define EXTI_RTSR_TR7_Msk   (0x1U << EXTI_RTSR_TR7_Pos)
 
#define EXTI_RTSR_TR7   EXTI_RTSR_TR7_Msk
 
#define EXTI_RTSR_TR8_Pos   (8U)
 
#define EXTI_RTSR_TR8_Msk   (0x1U << EXTI_RTSR_TR8_Pos)
 
#define EXTI_RTSR_TR8   EXTI_RTSR_TR8_Msk
 
#define EXTI_RTSR_TR9_Pos   (9U)
 
#define EXTI_RTSR_TR9_Msk   (0x1U << EXTI_RTSR_TR9_Pos)
 
#define EXTI_RTSR_TR9   EXTI_RTSR_TR9_Msk
 
#define EXTI_RTSR_TR10_Pos   (10U)
 
#define EXTI_RTSR_TR10_Msk   (0x1U << EXTI_RTSR_TR10_Pos)
 
#define EXTI_RTSR_TR10   EXTI_RTSR_TR10_Msk
 
#define EXTI_RTSR_TR11_Pos   (11U)
 
#define EXTI_RTSR_TR11_Msk   (0x1U << EXTI_RTSR_TR11_Pos)
 
#define EXTI_RTSR_TR11   EXTI_RTSR_TR11_Msk
 
#define EXTI_RTSR_TR12_Pos   (12U)
 
#define EXTI_RTSR_TR12_Msk   (0x1U << EXTI_RTSR_TR12_Pos)
 
#define EXTI_RTSR_TR12   EXTI_RTSR_TR12_Msk
 
#define EXTI_RTSR_TR13_Pos   (13U)
 
#define EXTI_RTSR_TR13_Msk   (0x1U << EXTI_RTSR_TR13_Pos)
 
#define EXTI_RTSR_TR13   EXTI_RTSR_TR13_Msk
 
#define EXTI_RTSR_TR14_Pos   (14U)
 
#define EXTI_RTSR_TR14_Msk   (0x1U << EXTI_RTSR_TR14_Pos)
 
#define EXTI_RTSR_TR14   EXTI_RTSR_TR14_Msk
 
#define EXTI_RTSR_TR15_Pos   (15U)
 
#define EXTI_RTSR_TR15_Msk   (0x1U << EXTI_RTSR_TR15_Pos)
 
#define EXTI_RTSR_TR15   EXTI_RTSR_TR15_Msk
 
#define EXTI_RTSR_TR16_Pos   (16U)
 
#define EXTI_RTSR_TR16_Msk   (0x1U << EXTI_RTSR_TR16_Pos)
 
#define EXTI_RTSR_TR16   EXTI_RTSR_TR16_Msk
 
#define EXTI_RTSR_TR17_Pos   (17U)
 
#define EXTI_RTSR_TR17_Msk   (0x1U << EXTI_RTSR_TR17_Pos)
 
#define EXTI_RTSR_TR17   EXTI_RTSR_TR17_Msk
 
#define EXTI_RTSR_TR18_Pos   (18U)
 
#define EXTI_RTSR_TR18_Msk   (0x1U << EXTI_RTSR_TR18_Pos)
 
#define EXTI_RTSR_TR18   EXTI_RTSR_TR18_Msk
 
#define EXTI_RTSR_TR19_Pos   (19U)
 
#define EXTI_RTSR_TR19_Msk   (0x1U << EXTI_RTSR_TR19_Pos)
 
#define EXTI_RTSR_TR19   EXTI_RTSR_TR19_Msk
 
#define EXTI_RTSR_TR20_Pos   (20U)
 
#define EXTI_RTSR_TR20_Msk   (0x1U << EXTI_RTSR_TR20_Pos)
 
#define EXTI_RTSR_TR20   EXTI_RTSR_TR20_Msk
 
#define EXTI_RTSR_TR21_Pos   (21U)
 
#define EXTI_RTSR_TR21_Msk   (0x1U << EXTI_RTSR_TR21_Pos)
 
#define EXTI_RTSR_TR21   EXTI_RTSR_TR21_Msk
 
#define EXTI_RTSR_TR22_Pos   (22U)
 
#define EXTI_RTSR_TR22_Msk   (0x1U << EXTI_RTSR_TR22_Pos)
 
#define EXTI_RTSR_TR22   EXTI_RTSR_TR22_Msk
 
#define EXTI_RTSR_TR23_Pos   (23U)
 
#define EXTI_RTSR_TR23_Msk   (0x1U << EXTI_RTSR_TR23_Pos)
 
#define EXTI_RTSR_TR23   EXTI_RTSR_TR23_Msk
 
#define EXTI_RTSR_RT0   EXTI_RTSR_TR0
 
#define EXTI_RTSR_RT1   EXTI_RTSR_TR1
 
#define EXTI_RTSR_RT2   EXTI_RTSR_TR2
 
#define EXTI_RTSR_RT3   EXTI_RTSR_TR3
 
#define EXTI_RTSR_RT4   EXTI_RTSR_TR4
 
#define EXTI_RTSR_RT5   EXTI_RTSR_TR5
 
#define EXTI_RTSR_RT6   EXTI_RTSR_TR6
 
#define EXTI_RTSR_RT7   EXTI_RTSR_TR7
 
#define EXTI_RTSR_RT8   EXTI_RTSR_TR8
 
#define EXTI_RTSR_RT9   EXTI_RTSR_TR9
 
#define EXTI_RTSR_RT10   EXTI_RTSR_TR10
 
#define EXTI_RTSR_RT11   EXTI_RTSR_TR11
 
#define EXTI_RTSR_RT12   EXTI_RTSR_TR12
 
#define EXTI_RTSR_RT13   EXTI_RTSR_TR13
 
#define EXTI_RTSR_RT14   EXTI_RTSR_TR14
 
#define EXTI_RTSR_RT15   EXTI_RTSR_TR15
 
#define EXTI_RTSR_RT16   EXTI_RTSR_TR16
 
#define EXTI_RTSR_RT17   EXTI_RTSR_TR17
 
#define EXTI_RTSR_RT18   EXTI_RTSR_TR18
 
#define EXTI_RTSR_RT19   EXTI_RTSR_TR19
 
#define EXTI_RTSR_RT20   EXTI_RTSR_TR20
 
#define EXTI_RTSR_RT21   EXTI_RTSR_TR21
 
#define EXTI_RTSR_RT22   EXTI_RTSR_TR22
 
#define EXTI_RTSR_RT23   EXTI_RTSR_TR23
 
#define EXTI_FTSR_TR0_Pos   (0U)
 
#define EXTI_FTSR_TR0_Msk   (0x1U << EXTI_FTSR_TR0_Pos)
 
#define EXTI_FTSR_TR0   EXTI_FTSR_TR0_Msk
 
#define EXTI_FTSR_TR1_Pos   (1U)
 
#define EXTI_FTSR_TR1_Msk   (0x1U << EXTI_FTSR_TR1_Pos)
 
#define EXTI_FTSR_TR1   EXTI_FTSR_TR1_Msk
 
#define EXTI_FTSR_TR2_Pos   (2U)
 
#define EXTI_FTSR_TR2_Msk   (0x1U << EXTI_FTSR_TR2_Pos)
 
#define EXTI_FTSR_TR2   EXTI_FTSR_TR2_Msk
 
#define EXTI_FTSR_TR3_Pos   (3U)
 
#define EXTI_FTSR_TR3_Msk   (0x1U << EXTI_FTSR_TR3_Pos)
 
#define EXTI_FTSR_TR3   EXTI_FTSR_TR3_Msk
 
#define EXTI_FTSR_TR4_Pos   (4U)
 
#define EXTI_FTSR_TR4_Msk   (0x1U << EXTI_FTSR_TR4_Pos)
 
#define EXTI_FTSR_TR4   EXTI_FTSR_TR4_Msk
 
#define EXTI_FTSR_TR5_Pos   (5U)
 
#define EXTI_FTSR_TR5_Msk   (0x1U << EXTI_FTSR_TR5_Pos)
 
#define EXTI_FTSR_TR5   EXTI_FTSR_TR5_Msk
 
#define EXTI_FTSR_TR6_Pos   (6U)
 
#define EXTI_FTSR_TR6_Msk   (0x1U << EXTI_FTSR_TR6_Pos)
 
#define EXTI_FTSR_TR6   EXTI_FTSR_TR6_Msk
 
#define EXTI_FTSR_TR7_Pos   (7U)
 
#define EXTI_FTSR_TR7_Msk   (0x1U << EXTI_FTSR_TR7_Pos)
 
#define EXTI_FTSR_TR7   EXTI_FTSR_TR7_Msk
 
#define EXTI_FTSR_TR8_Pos   (8U)
 
#define EXTI_FTSR_TR8_Msk   (0x1U << EXTI_FTSR_TR8_Pos)
 
#define EXTI_FTSR_TR8   EXTI_FTSR_TR8_Msk
 
#define EXTI_FTSR_TR9_Pos   (9U)
 
#define EXTI_FTSR_TR9_Msk   (0x1U << EXTI_FTSR_TR9_Pos)
 
#define EXTI_FTSR_TR9   EXTI_FTSR_TR9_Msk
 
#define EXTI_FTSR_TR10_Pos   (10U)
 
#define EXTI_FTSR_TR10_Msk   (0x1U << EXTI_FTSR_TR10_Pos)
 
#define EXTI_FTSR_TR10   EXTI_FTSR_TR10_Msk
 
#define EXTI_FTSR_TR11_Pos   (11U)
 
#define EXTI_FTSR_TR11_Msk   (0x1U << EXTI_FTSR_TR11_Pos)
 
#define EXTI_FTSR_TR11   EXTI_FTSR_TR11_Msk
 
#define EXTI_FTSR_TR12_Pos   (12U)
 
#define EXTI_FTSR_TR12_Msk   (0x1U << EXTI_FTSR_TR12_Pos)
 
#define EXTI_FTSR_TR12   EXTI_FTSR_TR12_Msk
 
#define EXTI_FTSR_TR13_Pos   (13U)
 
#define EXTI_FTSR_TR13_Msk   (0x1U << EXTI_FTSR_TR13_Pos)
 
#define EXTI_FTSR_TR13   EXTI_FTSR_TR13_Msk
 
#define EXTI_FTSR_TR14_Pos   (14U)
 
#define EXTI_FTSR_TR14_Msk   (0x1U << EXTI_FTSR_TR14_Pos)
 
#define EXTI_FTSR_TR14   EXTI_FTSR_TR14_Msk
 
#define EXTI_FTSR_TR15_Pos   (15U)
 
#define EXTI_FTSR_TR15_Msk   (0x1U << EXTI_FTSR_TR15_Pos)
 
#define EXTI_FTSR_TR15   EXTI_FTSR_TR15_Msk
 
#define EXTI_FTSR_TR16_Pos   (16U)
 
#define EXTI_FTSR_TR16_Msk   (0x1U << EXTI_FTSR_TR16_Pos)
 
#define EXTI_FTSR_TR16   EXTI_FTSR_TR16_Msk
 
#define EXTI_FTSR_TR17_Pos   (17U)
 
#define EXTI_FTSR_TR17_Msk   (0x1U << EXTI_FTSR_TR17_Pos)
 
#define EXTI_FTSR_TR17   EXTI_FTSR_TR17_Msk
 
#define EXTI_FTSR_TR18_Pos   (18U)
 
#define EXTI_FTSR_TR18_Msk   (0x1U << EXTI_FTSR_TR18_Pos)
 
#define EXTI_FTSR_TR18   EXTI_FTSR_TR18_Msk
 
#define EXTI_FTSR_TR19_Pos   (19U)
 
#define EXTI_FTSR_TR19_Msk   (0x1U << EXTI_FTSR_TR19_Pos)
 
#define EXTI_FTSR_TR19   EXTI_FTSR_TR19_Msk
 
#define EXTI_FTSR_TR20_Pos   (20U)
 
#define EXTI_FTSR_TR20_Msk   (0x1U << EXTI_FTSR_TR20_Pos)
 
#define EXTI_FTSR_TR20   EXTI_FTSR_TR20_Msk
 
#define EXTI_FTSR_TR21_Pos   (21U)
 
#define EXTI_FTSR_TR21_Msk   (0x1U << EXTI_FTSR_TR21_Pos)
 
#define EXTI_FTSR_TR21   EXTI_FTSR_TR21_Msk
 
#define EXTI_FTSR_TR22_Pos   (22U)
 
#define EXTI_FTSR_TR22_Msk   (0x1U << EXTI_FTSR_TR22_Pos)
 
#define EXTI_FTSR_TR22   EXTI_FTSR_TR22_Msk
 
#define EXTI_FTSR_TR23_Pos   (23U)
 
#define EXTI_FTSR_TR23_Msk   (0x1U << EXTI_FTSR_TR23_Pos)
 
#define EXTI_FTSR_TR23   EXTI_FTSR_TR23_Msk
 
#define EXTI_FTSR_FT0   EXTI_FTSR_TR0
 
#define EXTI_FTSR_FT1   EXTI_FTSR_TR1
 
#define EXTI_FTSR_FT2   EXTI_FTSR_TR2
 
#define EXTI_FTSR_FT3   EXTI_FTSR_TR3
 
#define EXTI_FTSR_FT4   EXTI_FTSR_TR4
 
#define EXTI_FTSR_FT5   EXTI_FTSR_TR5
 
#define EXTI_FTSR_FT6   EXTI_FTSR_TR6
 
#define EXTI_FTSR_FT7   EXTI_FTSR_TR7
 
#define EXTI_FTSR_FT8   EXTI_FTSR_TR8
 
#define EXTI_FTSR_FT9   EXTI_FTSR_TR9
 
#define EXTI_FTSR_FT10   EXTI_FTSR_TR10
 
#define EXTI_FTSR_FT11   EXTI_FTSR_TR11
 
#define EXTI_FTSR_FT12   EXTI_FTSR_TR12
 
#define EXTI_FTSR_FT13   EXTI_FTSR_TR13
 
#define EXTI_FTSR_FT14   EXTI_FTSR_TR14
 
#define EXTI_FTSR_FT15   EXTI_FTSR_TR15
 
#define EXTI_FTSR_FT16   EXTI_FTSR_TR16
 
#define EXTI_FTSR_FT17   EXTI_FTSR_TR17
 
#define EXTI_FTSR_FT18   EXTI_FTSR_TR18
 
#define EXTI_FTSR_FT19   EXTI_FTSR_TR19
 
#define EXTI_FTSR_FT20   EXTI_FTSR_TR20
 
#define EXTI_FTSR_FT21   EXTI_FTSR_TR21
 
#define EXTI_FTSR_FT22   EXTI_FTSR_TR22
 
#define EXTI_FTSR_FT23   EXTI_FTSR_TR23
 
#define EXTI_SWIER_SWIER0_Pos   (0U)
 
#define EXTI_SWIER_SWIER0_Msk   (0x1U << EXTI_SWIER_SWIER0_Pos)
 
#define EXTI_SWIER_SWIER0   EXTI_SWIER_SWIER0_Msk
 
#define EXTI_SWIER_SWIER1_Pos   (1U)
 
#define EXTI_SWIER_SWIER1_Msk   (0x1U << EXTI_SWIER_SWIER1_Pos)
 
#define EXTI_SWIER_SWIER1   EXTI_SWIER_SWIER1_Msk
 
#define EXTI_SWIER_SWIER2_Pos   (2U)
 
#define EXTI_SWIER_SWIER2_Msk   (0x1U << EXTI_SWIER_SWIER2_Pos)
 
#define EXTI_SWIER_SWIER2   EXTI_SWIER_SWIER2_Msk
 
#define EXTI_SWIER_SWIER3_Pos   (3U)
 
#define EXTI_SWIER_SWIER3_Msk   (0x1U << EXTI_SWIER_SWIER3_Pos)
 
#define EXTI_SWIER_SWIER3   EXTI_SWIER_SWIER3_Msk
 
#define EXTI_SWIER_SWIER4_Pos   (4U)
 
#define EXTI_SWIER_SWIER4_Msk   (0x1U << EXTI_SWIER_SWIER4_Pos)
 
#define EXTI_SWIER_SWIER4   EXTI_SWIER_SWIER4_Msk
 
#define EXTI_SWIER_SWIER5_Pos   (5U)
 
#define EXTI_SWIER_SWIER5_Msk   (0x1U << EXTI_SWIER_SWIER5_Pos)
 
#define EXTI_SWIER_SWIER5   EXTI_SWIER_SWIER5_Msk
 
#define EXTI_SWIER_SWIER6_Pos   (6U)
 
#define EXTI_SWIER_SWIER6_Msk   (0x1U << EXTI_SWIER_SWIER6_Pos)
 
#define EXTI_SWIER_SWIER6   EXTI_SWIER_SWIER6_Msk
 
#define EXTI_SWIER_SWIER7_Pos   (7U)
 
#define EXTI_SWIER_SWIER7_Msk   (0x1U << EXTI_SWIER_SWIER7_Pos)
 
#define EXTI_SWIER_SWIER7   EXTI_SWIER_SWIER7_Msk
 
#define EXTI_SWIER_SWIER8_Pos   (8U)
 
#define EXTI_SWIER_SWIER8_Msk   (0x1U << EXTI_SWIER_SWIER8_Pos)
 
#define EXTI_SWIER_SWIER8   EXTI_SWIER_SWIER8_Msk
 
#define EXTI_SWIER_SWIER9_Pos   (9U)
 
#define EXTI_SWIER_SWIER9_Msk   (0x1U << EXTI_SWIER_SWIER9_Pos)
 
#define EXTI_SWIER_SWIER9   EXTI_SWIER_SWIER9_Msk
 
#define EXTI_SWIER_SWIER10_Pos   (10U)
 
#define EXTI_SWIER_SWIER10_Msk   (0x1U << EXTI_SWIER_SWIER10_Pos)
 
#define EXTI_SWIER_SWIER10   EXTI_SWIER_SWIER10_Msk
 
#define EXTI_SWIER_SWIER11_Pos   (11U)
 
#define EXTI_SWIER_SWIER11_Msk   (0x1U << EXTI_SWIER_SWIER11_Pos)
 
#define EXTI_SWIER_SWIER11   EXTI_SWIER_SWIER11_Msk
 
#define EXTI_SWIER_SWIER12_Pos   (12U)
 
#define EXTI_SWIER_SWIER12_Msk   (0x1U << EXTI_SWIER_SWIER12_Pos)
 
#define EXTI_SWIER_SWIER12   EXTI_SWIER_SWIER12_Msk
 
#define EXTI_SWIER_SWIER13_Pos   (13U)
 
#define EXTI_SWIER_SWIER13_Msk   (0x1U << EXTI_SWIER_SWIER13_Pos)
 
#define EXTI_SWIER_SWIER13   EXTI_SWIER_SWIER13_Msk
 
#define EXTI_SWIER_SWIER14_Pos   (14U)
 
#define EXTI_SWIER_SWIER14_Msk   (0x1U << EXTI_SWIER_SWIER14_Pos)
 
#define EXTI_SWIER_SWIER14   EXTI_SWIER_SWIER14_Msk
 
#define EXTI_SWIER_SWIER15_Pos   (15U)
 
#define EXTI_SWIER_SWIER15_Msk   (0x1U << EXTI_SWIER_SWIER15_Pos)
 
#define EXTI_SWIER_SWIER15   EXTI_SWIER_SWIER15_Msk
 
#define EXTI_SWIER_SWIER16_Pos   (16U)
 
#define EXTI_SWIER_SWIER16_Msk   (0x1U << EXTI_SWIER_SWIER16_Pos)
 
#define EXTI_SWIER_SWIER16   EXTI_SWIER_SWIER16_Msk
 
#define EXTI_SWIER_SWIER17_Pos   (17U)
 
#define EXTI_SWIER_SWIER17_Msk   (0x1U << EXTI_SWIER_SWIER17_Pos)
 
#define EXTI_SWIER_SWIER17   EXTI_SWIER_SWIER17_Msk
 
#define EXTI_SWIER_SWIER18_Pos   (18U)
 
#define EXTI_SWIER_SWIER18_Msk   (0x1U << EXTI_SWIER_SWIER18_Pos)
 
#define EXTI_SWIER_SWIER18   EXTI_SWIER_SWIER18_Msk
 
#define EXTI_SWIER_SWIER19_Pos   (19U)
 
#define EXTI_SWIER_SWIER19_Msk   (0x1U << EXTI_SWIER_SWIER19_Pos)
 
#define EXTI_SWIER_SWIER19   EXTI_SWIER_SWIER19_Msk
 
#define EXTI_SWIER_SWIER20_Pos   (20U)
 
#define EXTI_SWIER_SWIER20_Msk   (0x1U << EXTI_SWIER_SWIER20_Pos)
 
#define EXTI_SWIER_SWIER20   EXTI_SWIER_SWIER20_Msk
 
#define EXTI_SWIER_SWIER21_Pos   (21U)
 
#define EXTI_SWIER_SWIER21_Msk   (0x1U << EXTI_SWIER_SWIER21_Pos)
 
#define EXTI_SWIER_SWIER21   EXTI_SWIER_SWIER21_Msk
 
#define EXTI_SWIER_SWIER22_Pos   (22U)
 
#define EXTI_SWIER_SWIER22_Msk   (0x1U << EXTI_SWIER_SWIER22_Pos)
 
#define EXTI_SWIER_SWIER22   EXTI_SWIER_SWIER22_Msk
 
#define EXTI_SWIER_SWIER23_Pos   (23U)
 
#define EXTI_SWIER_SWIER23_Msk   (0x1U << EXTI_SWIER_SWIER23_Pos)
 
#define EXTI_SWIER_SWIER23   EXTI_SWIER_SWIER23_Msk
 
#define EXTI_SWIER_SWI0   EXTI_SWIER_SWIER0
 
#define EXTI_SWIER_SWI1   EXTI_SWIER_SWIER1
 
#define EXTI_SWIER_SWI2   EXTI_SWIER_SWIER2
 
#define EXTI_SWIER_SWI3   EXTI_SWIER_SWIER3
 
#define EXTI_SWIER_SWI4   EXTI_SWIER_SWIER4
 
#define EXTI_SWIER_SWI5   EXTI_SWIER_SWIER5
 
#define EXTI_SWIER_SWI6   EXTI_SWIER_SWIER6
 
#define EXTI_SWIER_SWI7   EXTI_SWIER_SWIER7
 
#define EXTI_SWIER_SWI8   EXTI_SWIER_SWIER8
 
#define EXTI_SWIER_SWI9   EXTI_SWIER_SWIER9
 
#define EXTI_SWIER_SWI10   EXTI_SWIER_SWIER10
 
#define EXTI_SWIER_SWI11   EXTI_SWIER_SWIER11
 
#define EXTI_SWIER_SWI12   EXTI_SWIER_SWIER12
 
#define EXTI_SWIER_SWI13   EXTI_SWIER_SWIER13
 
#define EXTI_SWIER_SWI14   EXTI_SWIER_SWIER14
 
#define EXTI_SWIER_SWI15   EXTI_SWIER_SWIER15
 
#define EXTI_SWIER_SWI16   EXTI_SWIER_SWIER16
 
#define EXTI_SWIER_SWI17   EXTI_SWIER_SWIER17
 
#define EXTI_SWIER_SWI18   EXTI_SWIER_SWIER18
 
#define EXTI_SWIER_SWI19   EXTI_SWIER_SWIER19
 
#define EXTI_SWIER_SWI20   EXTI_SWIER_SWIER20
 
#define EXTI_SWIER_SWI21   EXTI_SWIER_SWIER21
 
#define EXTI_SWIER_SWI22   EXTI_SWIER_SWIER22
 
#define EXTI_SWIER_SWI23   EXTI_SWIER_SWIER23
 
#define EXTI_PR_PR0_Pos   (0U)
 
#define EXTI_PR_PR0_Msk   (0x1U << EXTI_PR_PR0_Pos)
 
#define EXTI_PR_PR0   EXTI_PR_PR0_Msk
 
#define EXTI_PR_PR1_Pos   (1U)
 
#define EXTI_PR_PR1_Msk   (0x1U << EXTI_PR_PR1_Pos)
 
#define EXTI_PR_PR1   EXTI_PR_PR1_Msk
 
#define EXTI_PR_PR2_Pos   (2U)
 
#define EXTI_PR_PR2_Msk   (0x1U << EXTI_PR_PR2_Pos)
 
#define EXTI_PR_PR2   EXTI_PR_PR2_Msk
 
#define EXTI_PR_PR3_Pos   (3U)
 
#define EXTI_PR_PR3_Msk   (0x1U << EXTI_PR_PR3_Pos)
 
#define EXTI_PR_PR3   EXTI_PR_PR3_Msk
 
#define EXTI_PR_PR4_Pos   (4U)
 
#define EXTI_PR_PR4_Msk   (0x1U << EXTI_PR_PR4_Pos)
 
#define EXTI_PR_PR4   EXTI_PR_PR4_Msk
 
#define EXTI_PR_PR5_Pos   (5U)
 
#define EXTI_PR_PR5_Msk   (0x1U << EXTI_PR_PR5_Pos)
 
#define EXTI_PR_PR5   EXTI_PR_PR5_Msk
 
#define EXTI_PR_PR6_Pos   (6U)
 
#define EXTI_PR_PR6_Msk   (0x1U << EXTI_PR_PR6_Pos)
 
#define EXTI_PR_PR6   EXTI_PR_PR6_Msk
 
#define EXTI_PR_PR7_Pos   (7U)
 
#define EXTI_PR_PR7_Msk   (0x1U << EXTI_PR_PR7_Pos)
 
#define EXTI_PR_PR7   EXTI_PR_PR7_Msk
 
#define EXTI_PR_PR8_Pos   (8U)
 
#define EXTI_PR_PR8_Msk   (0x1U << EXTI_PR_PR8_Pos)
 
#define EXTI_PR_PR8   EXTI_PR_PR8_Msk
 
#define EXTI_PR_PR9_Pos   (9U)
 
#define EXTI_PR_PR9_Msk   (0x1U << EXTI_PR_PR9_Pos)
 
#define EXTI_PR_PR9   EXTI_PR_PR9_Msk
 
#define EXTI_PR_PR10_Pos   (10U)
 
#define EXTI_PR_PR10_Msk   (0x1U << EXTI_PR_PR10_Pos)
 
#define EXTI_PR_PR10   EXTI_PR_PR10_Msk
 
#define EXTI_PR_PR11_Pos   (11U)
 
#define EXTI_PR_PR11_Msk   (0x1U << EXTI_PR_PR11_Pos)
 
#define EXTI_PR_PR11   EXTI_PR_PR11_Msk
 
#define EXTI_PR_PR12_Pos   (12U)
 
#define EXTI_PR_PR12_Msk   (0x1U << EXTI_PR_PR12_Pos)
 
#define EXTI_PR_PR12   EXTI_PR_PR12_Msk
 
#define EXTI_PR_PR13_Pos   (13U)
 
#define EXTI_PR_PR13_Msk   (0x1U << EXTI_PR_PR13_Pos)
 
#define EXTI_PR_PR13   EXTI_PR_PR13_Msk
 
#define EXTI_PR_PR14_Pos   (14U)
 
#define EXTI_PR_PR14_Msk   (0x1U << EXTI_PR_PR14_Pos)
 
#define EXTI_PR_PR14   EXTI_PR_PR14_Msk
 
#define EXTI_PR_PR15_Pos   (15U)
 
#define EXTI_PR_PR15_Msk   (0x1U << EXTI_PR_PR15_Pos)
 
#define EXTI_PR_PR15   EXTI_PR_PR15_Msk
 
#define EXTI_PR_PR16_Pos   (16U)
 
#define EXTI_PR_PR16_Msk   (0x1U << EXTI_PR_PR16_Pos)
 
#define EXTI_PR_PR16   EXTI_PR_PR16_Msk
 
#define EXTI_PR_PR17_Pos   (17U)
 
#define EXTI_PR_PR17_Msk   (0x1U << EXTI_PR_PR17_Pos)
 
#define EXTI_PR_PR17   EXTI_PR_PR17_Msk
 
#define EXTI_PR_PR18_Pos   (18U)
 
#define EXTI_PR_PR18_Msk   (0x1U << EXTI_PR_PR18_Pos)
 
#define EXTI_PR_PR18   EXTI_PR_PR18_Msk
 
#define EXTI_PR_PR19_Pos   (19U)
 
#define EXTI_PR_PR19_Msk   (0x1U << EXTI_PR_PR19_Pos)
 
#define EXTI_PR_PR19   EXTI_PR_PR19_Msk
 
#define EXTI_PR_PR20_Pos   (20U)
 
#define EXTI_PR_PR20_Msk   (0x1U << EXTI_PR_PR20_Pos)
 
#define EXTI_PR_PR20   EXTI_PR_PR20_Msk
 
#define EXTI_PR_PR21_Pos   (21U)
 
#define EXTI_PR_PR21_Msk   (0x1U << EXTI_PR_PR21_Pos)
 
#define EXTI_PR_PR21   EXTI_PR_PR21_Msk
 
#define EXTI_PR_PR22_Pos   (22U)
 
#define EXTI_PR_PR22_Msk   (0x1U << EXTI_PR_PR22_Pos)
 
#define EXTI_PR_PR22   EXTI_PR_PR22_Msk
 
#define EXTI_PR_PR23_Pos   (23U)
 
#define EXTI_PR_PR23_Msk   (0x1U << EXTI_PR_PR23_Pos)
 
#define EXTI_PR_PR23   EXTI_PR_PR23_Msk
 
#define EXTI_PR_PIF0   EXTI_PR_PR0
 
#define EXTI_PR_PIF1   EXTI_PR_PR1
 
#define EXTI_PR_PIF2   EXTI_PR_PR2
 
#define EXTI_PR_PIF3   EXTI_PR_PR3
 
#define EXTI_PR_PIF4   EXTI_PR_PR4
 
#define EXTI_PR_PIF5   EXTI_PR_PR5
 
#define EXTI_PR_PIF6   EXTI_PR_PR6
 
#define EXTI_PR_PIF7   EXTI_PR_PR7
 
#define EXTI_PR_PIF8   EXTI_PR_PR8
 
#define EXTI_PR_PIF9   EXTI_PR_PR9
 
#define EXTI_PR_PIF10   EXTI_PR_PR10
 
#define EXTI_PR_PIF11   EXTI_PR_PR11
 
#define EXTI_PR_PIF12   EXTI_PR_PR12
 
#define EXTI_PR_PIF13   EXTI_PR_PR13
 
#define EXTI_PR_PIF14   EXTI_PR_PR14
 
#define EXTI_PR_PIF15   EXTI_PR_PR15
 
#define EXTI_PR_PIF16   EXTI_PR_PR16
 
#define EXTI_PR_PIF17   EXTI_PR_PR17
 
#define EXTI_PR_PIF18   EXTI_PR_PR18
 
#define EXTI_PR_PIF19   EXTI_PR_PR19
 
#define EXTI_PR_PIF20   EXTI_PR_PR20
 
#define EXTI_PR_PIF21   EXTI_PR_PR21
 
#define EXTI_PR_PIF22   EXTI_PR_PR22
 
#define EXTI_PR_PIF23   EXTI_PR_PR23
 
#define FLASH_ACR_LATENCY_Pos   (0U)
 
#define FLASH_ACR_LATENCY_Msk   (0x1U << FLASH_ACR_LATENCY_Pos)
 
#define FLASH_ACR_LATENCY   FLASH_ACR_LATENCY_Msk
 
#define FLASH_ACR_PRFTEN_Pos   (1U)
 
#define FLASH_ACR_PRFTEN_Msk   (0x1U << FLASH_ACR_PRFTEN_Pos)
 
#define FLASH_ACR_PRFTEN   FLASH_ACR_PRFTEN_Msk
 
#define FLASH_ACR_ACC64_Pos   (2U)
 
#define FLASH_ACR_ACC64_Msk   (0x1U << FLASH_ACR_ACC64_Pos)
 
#define FLASH_ACR_ACC64   FLASH_ACR_ACC64_Msk
 
#define FLASH_ACR_SLEEP_PD_Pos   (3U)
 
#define FLASH_ACR_SLEEP_PD_Msk   (0x1U << FLASH_ACR_SLEEP_PD_Pos)
 
#define FLASH_ACR_SLEEP_PD   FLASH_ACR_SLEEP_PD_Msk
 
#define FLASH_ACR_RUN_PD_Pos   (4U)
 
#define FLASH_ACR_RUN_PD_Msk   (0x1U << FLASH_ACR_RUN_PD_Pos)
 
#define FLASH_ACR_RUN_PD   FLASH_ACR_RUN_PD_Msk
 
#define FLASH_PECR_PELOCK_Pos   (0U)
 
#define FLASH_PECR_PELOCK_Msk   (0x1U << FLASH_PECR_PELOCK_Pos)
 
#define FLASH_PECR_PELOCK   FLASH_PECR_PELOCK_Msk
 
#define FLASH_PECR_PRGLOCK_Pos   (1U)
 
#define FLASH_PECR_PRGLOCK_Msk   (0x1U << FLASH_PECR_PRGLOCK_Pos)
 
#define FLASH_PECR_PRGLOCK   FLASH_PECR_PRGLOCK_Msk
 
#define FLASH_PECR_OPTLOCK_Pos   (2U)
 
#define FLASH_PECR_OPTLOCK_Msk   (0x1U << FLASH_PECR_OPTLOCK_Pos)
 
#define FLASH_PECR_OPTLOCK   FLASH_PECR_OPTLOCK_Msk
 
#define FLASH_PECR_PROG_Pos   (3U)
 
#define FLASH_PECR_PROG_Msk   (0x1U << FLASH_PECR_PROG_Pos)
 
#define FLASH_PECR_PROG   FLASH_PECR_PROG_Msk
 
#define FLASH_PECR_DATA_Pos   (4U)
 
#define FLASH_PECR_DATA_Msk   (0x1U << FLASH_PECR_DATA_Pos)
 
#define FLASH_PECR_DATA   FLASH_PECR_DATA_Msk
 
#define FLASH_PECR_FTDW_Pos   (8U)
 
#define FLASH_PECR_FTDW_Msk   (0x1U << FLASH_PECR_FTDW_Pos)
 
#define FLASH_PECR_FTDW   FLASH_PECR_FTDW_Msk
 
#define FLASH_PECR_ERASE_Pos   (9U)
 
#define FLASH_PECR_ERASE_Msk   (0x1U << FLASH_PECR_ERASE_Pos)
 
#define FLASH_PECR_ERASE   FLASH_PECR_ERASE_Msk
 
#define FLASH_PECR_FPRG_Pos   (10U)
 
#define FLASH_PECR_FPRG_Msk   (0x1U << FLASH_PECR_FPRG_Pos)
 
#define FLASH_PECR_FPRG   FLASH_PECR_FPRG_Msk
 
#define FLASH_PECR_PARALLBANK_Pos   (15U)
 
#define FLASH_PECR_PARALLBANK_Msk   (0x1U << FLASH_PECR_PARALLBANK_Pos)
 
#define FLASH_PECR_PARALLBANK   FLASH_PECR_PARALLBANK_Msk
 
#define FLASH_PECR_EOPIE_Pos   (16U)
 
#define FLASH_PECR_EOPIE_Msk   (0x1U << FLASH_PECR_EOPIE_Pos)
 
#define FLASH_PECR_EOPIE   FLASH_PECR_EOPIE_Msk
 
#define FLASH_PECR_ERRIE_Pos   (17U)
 
#define FLASH_PECR_ERRIE_Msk   (0x1U << FLASH_PECR_ERRIE_Pos)
 
#define FLASH_PECR_ERRIE   FLASH_PECR_ERRIE_Msk
 
#define FLASH_PECR_OBL_LAUNCH_Pos   (18U)
 
#define FLASH_PECR_OBL_LAUNCH_Msk   (0x1U << FLASH_PECR_OBL_LAUNCH_Pos)
 
#define FLASH_PECR_OBL_LAUNCH   FLASH_PECR_OBL_LAUNCH_Msk
 
#define FLASH_PDKEYR_PDKEYR_Pos   (0U)
 
#define FLASH_PDKEYR_PDKEYR_Msk   (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos)
 
#define FLASH_PDKEYR_PDKEYR   FLASH_PDKEYR_PDKEYR_Msk
 
#define FLASH_PEKEYR_PEKEYR_Pos   (0U)
 
#define FLASH_PEKEYR_PEKEYR_Msk   (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos)
 
#define FLASH_PEKEYR_PEKEYR   FLASH_PEKEYR_PEKEYR_Msk
 
#define FLASH_PRGKEYR_PRGKEYR_Pos   (0U)
 
#define FLASH_PRGKEYR_PRGKEYR_Msk   (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos)
 
#define FLASH_PRGKEYR_PRGKEYR   FLASH_PRGKEYR_PRGKEYR_Msk
 
#define FLASH_OPTKEYR_OPTKEYR_Pos   (0U)
 
#define FLASH_OPTKEYR_OPTKEYR_Msk   (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos)
 
#define FLASH_OPTKEYR_OPTKEYR   FLASH_OPTKEYR_OPTKEYR_Msk
 
#define FLASH_SR_BSY_Pos   (0U)
 
#define FLASH_SR_BSY_Msk   (0x1U << FLASH_SR_BSY_Pos)
 
#define FLASH_SR_BSY   FLASH_SR_BSY_Msk
 
#define FLASH_SR_EOP_Pos   (1U)
 
#define FLASH_SR_EOP_Msk   (0x1U << FLASH_SR_EOP_Pos)
 
#define FLASH_SR_EOP   FLASH_SR_EOP_Msk
 
#define FLASH_SR_ENDHV_Pos   (2U)
 
#define FLASH_SR_ENDHV_Msk   (0x1U << FLASH_SR_ENDHV_Pos)
 
#define FLASH_SR_ENDHV   FLASH_SR_ENDHV_Msk
 
#define FLASH_SR_READY_Pos   (3U)
 
#define FLASH_SR_READY_Msk   (0x1U << FLASH_SR_READY_Pos)
 
#define FLASH_SR_READY   FLASH_SR_READY_Msk
 
#define FLASH_SR_WRPERR_Pos   (8U)
 
#define FLASH_SR_WRPERR_Msk   (0x1U << FLASH_SR_WRPERR_Pos)
 
#define FLASH_SR_WRPERR   FLASH_SR_WRPERR_Msk
 
#define FLASH_SR_PGAERR_Pos   (9U)
 
#define FLASH_SR_PGAERR_Msk   (0x1U << FLASH_SR_PGAERR_Pos)
 
#define FLASH_SR_PGAERR   FLASH_SR_PGAERR_Msk
 
#define FLASH_SR_SIZERR_Pos   (10U)
 
#define FLASH_SR_SIZERR_Msk   (0x1U << FLASH_SR_SIZERR_Pos)
 
#define FLASH_SR_SIZERR   FLASH_SR_SIZERR_Msk
 
#define FLASH_SR_OPTVERR_Pos   (11U)
 
#define FLASH_SR_OPTVERR_Msk   (0x1U << FLASH_SR_OPTVERR_Pos)
 
#define FLASH_SR_OPTVERR   FLASH_SR_OPTVERR_Msk
 
#define FLASH_SR_OPTVERRUSR_Pos   (12U)
 
#define FLASH_SR_OPTVERRUSR_Msk   (0x1U << FLASH_SR_OPTVERRUSR_Pos)
 
#define FLASH_SR_OPTVERRUSR   FLASH_SR_OPTVERRUSR_Msk
 
#define FLASH_OBR_RDPRT_Pos   (0U)
 
#define FLASH_OBR_RDPRT_Msk   (0xFFU << FLASH_OBR_RDPRT_Pos)
 
#define FLASH_OBR_RDPRT   FLASH_OBR_RDPRT_Msk
 
#define FLASH_OBR_BOR_LEV_Pos   (16U)
 
#define FLASH_OBR_BOR_LEV_Msk   (0xFU << FLASH_OBR_BOR_LEV_Pos)
 
#define FLASH_OBR_BOR_LEV   FLASH_OBR_BOR_LEV_Msk
 
#define FLASH_OBR_USER_Pos   (20U)
 
#define FLASH_OBR_USER_Msk   (0xFU << FLASH_OBR_USER_Pos)
 
#define FLASH_OBR_USER   FLASH_OBR_USER_Msk
 
#define FLASH_OBR_IWDG_SW_Pos   (20U)
 
#define FLASH_OBR_IWDG_SW_Msk   (0x1U << FLASH_OBR_IWDG_SW_Pos)
 
#define FLASH_OBR_IWDG_SW   FLASH_OBR_IWDG_SW_Msk
 
#define FLASH_OBR_nRST_STOP_Pos   (21U)
 
#define FLASH_OBR_nRST_STOP_Msk   (0x1U << FLASH_OBR_nRST_STOP_Pos)
 
#define FLASH_OBR_nRST_STOP   FLASH_OBR_nRST_STOP_Msk
 
#define FLASH_OBR_nRST_STDBY_Pos   (22U)
 
#define FLASH_OBR_nRST_STDBY_Msk   (0x1U << FLASH_OBR_nRST_STDBY_Pos)
 
#define FLASH_OBR_nRST_STDBY   FLASH_OBR_nRST_STDBY_Msk
 
#define FLASH_OBR_nRST_BFB2_Pos   (23U)
 
#define FLASH_OBR_nRST_BFB2_Msk   (0x1U << FLASH_OBR_nRST_BFB2_Pos)
 
#define FLASH_OBR_nRST_BFB2   FLASH_OBR_nRST_BFB2_Msk
 
#define FLASH_WRPR1_WRP_Pos   (0U)
 
#define FLASH_WRPR1_WRP_Msk   (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos)
 
#define FLASH_WRPR1_WRP   FLASH_WRPR1_WRP_Msk
 
#define FLASH_WRPR2_WRP_Pos   (0U)
 
#define FLASH_WRPR2_WRP_Msk   (0xFFFFFFFFU << FLASH_WRPR2_WRP_Pos)
 
#define FLASH_WRPR2_WRP   FLASH_WRPR2_WRP_Msk
 
#define FLASH_WRPR3_WRP_Pos   (0U)
 
#define FLASH_WRPR3_WRP_Msk   (0xFFFFFFFFU << FLASH_WRPR3_WRP_Pos)
 
#define FLASH_WRPR3_WRP   FLASH_WRPR3_WRP_Msk
 
#define FLASH_WRPR4_WRP_Pos   (0U)
 
#define FLASH_WRPR4_WRP_Msk   (0xFFFFFFFFU << FLASH_WRPR4_WRP_Pos)
 
#define FLASH_WRPR4_WRP   FLASH_WRPR4_WRP_Msk
 
#define GPIO_MODER_MODER0_Pos   (0U)
 
#define GPIO_MODER_MODER0_Msk   (0x3U << GPIO_MODER_MODER0_Pos)
 
#define GPIO_MODER_MODER0   GPIO_MODER_MODER0_Msk
 
#define GPIO_MODER_MODER0_0   (0x1U << GPIO_MODER_MODER0_Pos)
 
#define GPIO_MODER_MODER0_1   (0x2U << GPIO_MODER_MODER0_Pos)
 
#define GPIO_MODER_MODER1_Pos   (2U)
 
#define GPIO_MODER_MODER1_Msk   (0x3U << GPIO_MODER_MODER1_Pos)
 
#define GPIO_MODER_MODER1   GPIO_MODER_MODER1_Msk
 
#define GPIO_MODER_MODER1_0   (0x1U << GPIO_MODER_MODER1_Pos)
 
#define GPIO_MODER_MODER1_1   (0x2U << GPIO_MODER_MODER1_Pos)
 
#define GPIO_MODER_MODER2_Pos   (4U)
 
#define GPIO_MODER_MODER2_Msk   (0x3U << GPIO_MODER_MODER2_Pos)
 
#define GPIO_MODER_MODER2   GPIO_MODER_MODER2_Msk
 
#define GPIO_MODER_MODER2_0   (0x1U << GPIO_MODER_MODER2_Pos)
 
#define GPIO_MODER_MODER2_1   (0x2U << GPIO_MODER_MODER2_Pos)
 
#define GPIO_MODER_MODER3_Pos   (6U)
 
#define GPIO_MODER_MODER3_Msk   (0x3U << GPIO_MODER_MODER3_Pos)
 
#define GPIO_MODER_MODER3   GPIO_MODER_MODER3_Msk
 
#define GPIO_MODER_MODER3_0   (0x1U << GPIO_MODER_MODER3_Pos)
 
#define GPIO_MODER_MODER3_1   (0x2U << GPIO_MODER_MODER3_Pos)
 
#define GPIO_MODER_MODER4_Pos   (8U)
 
#define GPIO_MODER_MODER4_Msk   (0x3U << GPIO_MODER_MODER4_Pos)
 
#define GPIO_MODER_MODER4   GPIO_MODER_MODER4_Msk
 
#define GPIO_MODER_MODER4_0   (0x1U << GPIO_MODER_MODER4_Pos)
 
#define GPIO_MODER_MODER4_1   (0x2U << GPIO_MODER_MODER4_Pos)
 
#define GPIO_MODER_MODER5_Pos   (10U)
 
#define GPIO_MODER_MODER5_Msk   (0x3U << GPIO_MODER_MODER5_Pos)
 
#define GPIO_MODER_MODER5   GPIO_MODER_MODER5_Msk
 
#define GPIO_MODER_MODER5_0   (0x1U << GPIO_MODER_MODER5_Pos)
 
#define GPIO_MODER_MODER5_1   (0x2U << GPIO_MODER_MODER5_Pos)
 
#define GPIO_MODER_MODER6_Pos   (12U)
 
#define GPIO_MODER_MODER6_Msk   (0x3U << GPIO_MODER_MODER6_Pos)
 
#define GPIO_MODER_MODER6   GPIO_MODER_MODER6_Msk
 
#define GPIO_MODER_MODER6_0   (0x1U << GPIO_MODER_MODER6_Pos)
 
#define GPIO_MODER_MODER6_1   (0x2U << GPIO_MODER_MODER6_Pos)
 
#define GPIO_MODER_MODER7_Pos   (14U)
 
#define GPIO_MODER_MODER7_Msk   (0x3U << GPIO_MODER_MODER7_Pos)
 
#define GPIO_MODER_MODER7   GPIO_MODER_MODER7_Msk
 
#define GPIO_MODER_MODER7_0   (0x1U << GPIO_MODER_MODER7_Pos)
 
#define GPIO_MODER_MODER7_1   (0x2U << GPIO_MODER_MODER7_Pos)
 
#define GPIO_MODER_MODER8_Pos   (16U)
 
#define GPIO_MODER_MODER8_Msk   (0x3U << GPIO_MODER_MODER8_Pos)
 
#define GPIO_MODER_MODER8   GPIO_MODER_MODER8_Msk
 
#define GPIO_MODER_MODER8_0   (0x1U << GPIO_MODER_MODER8_Pos)
 
#define GPIO_MODER_MODER8_1   (0x2U << GPIO_MODER_MODER8_Pos)
 
#define GPIO_MODER_MODER9_Pos   (18U)
 
#define GPIO_MODER_MODER9_Msk   (0x3U << GPIO_MODER_MODER9_Pos)
 
#define GPIO_MODER_MODER9   GPIO_MODER_MODER9_Msk
 
#define GPIO_MODER_MODER9_0   (0x1U << GPIO_MODER_MODER9_Pos)
 
#define GPIO_MODER_MODER9_1   (0x2U << GPIO_MODER_MODER9_Pos)
 
#define GPIO_MODER_MODER10_Pos   (20U)
 
#define GPIO_MODER_MODER10_Msk   (0x3U << GPIO_MODER_MODER10_Pos)
 
#define GPIO_MODER_MODER10   GPIO_MODER_MODER10_Msk
 
#define GPIO_MODER_MODER10_0   (0x1U << GPIO_MODER_MODER10_Pos)
 
#define GPIO_MODER_MODER10_1   (0x2U << GPIO_MODER_MODER10_Pos)
 
#define GPIO_MODER_MODER11_Pos   (22U)
 
#define GPIO_MODER_MODER11_Msk   (0x3U << GPIO_MODER_MODER11_Pos)
 
#define GPIO_MODER_MODER11   GPIO_MODER_MODER11_Msk
 
#define GPIO_MODER_MODER11_0   (0x1U << GPIO_MODER_MODER11_Pos)
 
#define GPIO_MODER_MODER11_1   (0x2U << GPIO_MODER_MODER11_Pos)
 
#define GPIO_MODER_MODER12_Pos   (24U)
 
#define GPIO_MODER_MODER12_Msk   (0x3U << GPIO_MODER_MODER12_Pos)
 
#define GPIO_MODER_MODER12   GPIO_MODER_MODER12_Msk
 
#define GPIO_MODER_MODER12_0   (0x1U << GPIO_MODER_MODER12_Pos)
 
#define GPIO_MODER_MODER12_1   (0x2U << GPIO_MODER_MODER12_Pos)
 
#define GPIO_MODER_MODER13_Pos   (26U)
 
#define GPIO_MODER_MODER13_Msk   (0x3U << GPIO_MODER_MODER13_Pos)
 
#define GPIO_MODER_MODER13   GPIO_MODER_MODER13_Msk
 
#define GPIO_MODER_MODER13_0   (0x1U << GPIO_MODER_MODER13_Pos)
 
#define GPIO_MODER_MODER13_1   (0x2U << GPIO_MODER_MODER13_Pos)
 
#define GPIO_MODER_MODER14_Pos   (28U)
 
#define GPIO_MODER_MODER14_Msk   (0x3U << GPIO_MODER_MODER14_Pos)
 
#define GPIO_MODER_MODER14   GPIO_MODER_MODER14_Msk
 
#define GPIO_MODER_MODER14_0   (0x1U << GPIO_MODER_MODER14_Pos)
 
#define GPIO_MODER_MODER14_1   (0x2U << GPIO_MODER_MODER14_Pos)
 
#define GPIO_MODER_MODER15_Pos   (30U)
 
#define GPIO_MODER_MODER15_Msk   (0x3U << GPIO_MODER_MODER15_Pos)
 
#define GPIO_MODER_MODER15   GPIO_MODER_MODER15_Msk
 
#define GPIO_MODER_MODER15_0   (0x1U << GPIO_MODER_MODER15_Pos)
 
#define GPIO_MODER_MODER15_1   (0x2U << GPIO_MODER_MODER15_Pos)
 
#define GPIO_OTYPER_OT_0   (0x00000001U)
 
#define GPIO_OTYPER_OT_1   (0x00000002U)
 
#define GPIO_OTYPER_OT_2   (0x00000004U)
 
#define GPIO_OTYPER_OT_3   (0x00000008U)
 
#define GPIO_OTYPER_OT_4   (0x00000010U)
 
#define GPIO_OTYPER_OT_5   (0x00000020U)
 
#define GPIO_OTYPER_OT_6   (0x00000040U)
 
#define GPIO_OTYPER_OT_7   (0x00000080U)
 
#define GPIO_OTYPER_OT_8   (0x00000100U)
 
#define GPIO_OTYPER_OT_9   (0x00000200U)
 
#define GPIO_OTYPER_OT_10   (0x00000400U)
 
#define GPIO_OTYPER_OT_11   (0x00000800U)
 
#define GPIO_OTYPER_OT_12   (0x00001000U)
 
#define GPIO_OTYPER_OT_13   (0x00002000U)
 
#define GPIO_OTYPER_OT_14   (0x00004000U)
 
#define GPIO_OTYPER_OT_15   (0x00008000U)
 
#define GPIO_OSPEEDER_OSPEEDR0_Pos   (0U)
 
#define GPIO_OSPEEDER_OSPEEDR0_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR0   GPIO_OSPEEDER_OSPEEDR0_Msk
 
#define GPIO_OSPEEDER_OSPEEDR0_0   (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR0_1   (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR1_Pos   (2U)
 
#define GPIO_OSPEEDER_OSPEEDR1_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR1   GPIO_OSPEEDER_OSPEEDR1_Msk
 
#define GPIO_OSPEEDER_OSPEEDR1_0   (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR1_1   (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR2_Pos   (4U)
 
#define GPIO_OSPEEDER_OSPEEDR2_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR2   GPIO_OSPEEDER_OSPEEDR2_Msk
 
#define GPIO_OSPEEDER_OSPEEDR2_0   (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR2_1   (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR3_Pos   (6U)
 
#define GPIO_OSPEEDER_OSPEEDR3_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR3   GPIO_OSPEEDER_OSPEEDR3_Msk
 
#define GPIO_OSPEEDER_OSPEEDR3_0   (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR3_1   (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR4_Pos   (8U)
 
#define GPIO_OSPEEDER_OSPEEDR4_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR4   GPIO_OSPEEDER_OSPEEDR4_Msk
 
#define GPIO_OSPEEDER_OSPEEDR4_0   (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR4_1   (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR5_Pos   (10U)
 
#define GPIO_OSPEEDER_OSPEEDR5_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR5   GPIO_OSPEEDER_OSPEEDR5_Msk
 
#define GPIO_OSPEEDER_OSPEEDR5_0   (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR5_1   (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR6_Pos   (12U)
 
#define GPIO_OSPEEDER_OSPEEDR6_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR6   GPIO_OSPEEDER_OSPEEDR6_Msk
 
#define GPIO_OSPEEDER_OSPEEDR6_0   (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR6_1   (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR7_Pos   (14U)
 
#define GPIO_OSPEEDER_OSPEEDR7_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR7   GPIO_OSPEEDER_OSPEEDR7_Msk
 
#define GPIO_OSPEEDER_OSPEEDR7_0   (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR7_1   (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR8_Pos   (16U)
 
#define GPIO_OSPEEDER_OSPEEDR8_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR8   GPIO_OSPEEDER_OSPEEDR8_Msk
 
#define GPIO_OSPEEDER_OSPEEDR8_0   (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR8_1   (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR9_Pos   (18U)
 
#define GPIO_OSPEEDER_OSPEEDR9_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR9   GPIO_OSPEEDER_OSPEEDR9_Msk
 
#define GPIO_OSPEEDER_OSPEEDR9_0   (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR9_1   (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR10_Pos   (20U)
 
#define GPIO_OSPEEDER_OSPEEDR10_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR10   GPIO_OSPEEDER_OSPEEDR10_Msk
 
#define GPIO_OSPEEDER_OSPEEDR10_0   (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR10_1   (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR11_Pos   (22U)
 
#define GPIO_OSPEEDER_OSPEEDR11_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR11   GPIO_OSPEEDER_OSPEEDR11_Msk
 
#define GPIO_OSPEEDER_OSPEEDR11_0   (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR11_1   (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR12_Pos   (24U)
 
#define GPIO_OSPEEDER_OSPEEDR12_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR12   GPIO_OSPEEDER_OSPEEDR12_Msk
 
#define GPIO_OSPEEDER_OSPEEDR12_0   (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR12_1   (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR13_Pos   (26U)
 
#define GPIO_OSPEEDER_OSPEEDR13_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR13   GPIO_OSPEEDER_OSPEEDR13_Msk
 
#define GPIO_OSPEEDER_OSPEEDR13_0   (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR13_1   (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR14_Pos   (28U)
 
#define GPIO_OSPEEDER_OSPEEDR14_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR14   GPIO_OSPEEDER_OSPEEDR14_Msk
 
#define GPIO_OSPEEDER_OSPEEDR14_0   (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR14_1   (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR15_Pos   (30U)
 
#define GPIO_OSPEEDER_OSPEEDR15_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR15   GPIO_OSPEEDER_OSPEEDR15_Msk
 
#define GPIO_OSPEEDER_OSPEEDR15_0   (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos)
 
#define GPIO_OSPEEDER_OSPEEDR15_1   (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos)
 
#define GPIO_PUPDR_PUPDR0_Pos   (0U)
 
#define GPIO_PUPDR_PUPDR0_Msk   (0x3U << GPIO_PUPDR_PUPDR0_Pos)
 
#define GPIO_PUPDR_PUPDR0   GPIO_PUPDR_PUPDR0_Msk
 
#define GPIO_PUPDR_PUPDR0_0   (0x1U << GPIO_PUPDR_PUPDR0_Pos)
 
#define GPIO_PUPDR_PUPDR0_1   (0x2U << GPIO_PUPDR_PUPDR0_Pos)
 
#define GPIO_PUPDR_PUPDR1_Pos   (2U)
 
#define GPIO_PUPDR_PUPDR1_Msk   (0x3U << GPIO_PUPDR_PUPDR1_Pos)
 
#define GPIO_PUPDR_PUPDR1   GPIO_PUPDR_PUPDR1_Msk
 
#define GPIO_PUPDR_PUPDR1_0   (0x1U << GPIO_PUPDR_PUPDR1_Pos)
 
#define GPIO_PUPDR_PUPDR1_1   (0x2U << GPIO_PUPDR_PUPDR1_Pos)
 
#define GPIO_PUPDR_PUPDR2_Pos   (4U)
 
#define GPIO_PUPDR_PUPDR2_Msk   (0x3U << GPIO_PUPDR_PUPDR2_Pos)
 
#define GPIO_PUPDR_PUPDR2   GPIO_PUPDR_PUPDR2_Msk
 
#define GPIO_PUPDR_PUPDR2_0   (0x1U << GPIO_PUPDR_PUPDR2_Pos)
 
#define GPIO_PUPDR_PUPDR2_1   (0x2U << GPIO_PUPDR_PUPDR2_Pos)
 
#define GPIO_PUPDR_PUPDR3_Pos   (6U)
 
#define GPIO_PUPDR_PUPDR3_Msk   (0x3U << GPIO_PUPDR_PUPDR3_Pos)
 
#define GPIO_PUPDR_PUPDR3   GPIO_PUPDR_PUPDR3_Msk
 
#define GPIO_PUPDR_PUPDR3_0   (0x1U << GPIO_PUPDR_PUPDR3_Pos)
 
#define GPIO_PUPDR_PUPDR3_1   (0x2U << GPIO_PUPDR_PUPDR3_Pos)
 
#define GPIO_PUPDR_PUPDR4_Pos   (8U)
 
#define GPIO_PUPDR_PUPDR4_Msk   (0x3U << GPIO_PUPDR_PUPDR4_Pos)
 
#define GPIO_PUPDR_PUPDR4   GPIO_PUPDR_PUPDR4_Msk
 
#define GPIO_PUPDR_PUPDR4_0   (0x1U << GPIO_PUPDR_PUPDR4_Pos)
 
#define GPIO_PUPDR_PUPDR4_1   (0x2U << GPIO_PUPDR_PUPDR4_Pos)
 
#define GPIO_PUPDR_PUPDR5_Pos   (10U)
 
#define GPIO_PUPDR_PUPDR5_Msk   (0x3U << GPIO_PUPDR_PUPDR5_Pos)
 
#define GPIO_PUPDR_PUPDR5   GPIO_PUPDR_PUPDR5_Msk
 
#define GPIO_PUPDR_PUPDR5_0   (0x1U << GPIO_PUPDR_PUPDR5_Pos)
 
#define GPIO_PUPDR_PUPDR5_1   (0x2U << GPIO_PUPDR_PUPDR5_Pos)
 
#define GPIO_PUPDR_PUPDR6_Pos   (12U)
 
#define GPIO_PUPDR_PUPDR6_Msk   (0x3U << GPIO_PUPDR_PUPDR6_Pos)
 
#define GPIO_PUPDR_PUPDR6   GPIO_PUPDR_PUPDR6_Msk
 
#define GPIO_PUPDR_PUPDR6_0   (0x1U << GPIO_PUPDR_PUPDR6_Pos)
 
#define GPIO_PUPDR_PUPDR6_1   (0x2U << GPIO_PUPDR_PUPDR6_Pos)
 
#define GPIO_PUPDR_PUPDR7_Pos   (14U)
 
#define GPIO_PUPDR_PUPDR7_Msk   (0x3U << GPIO_PUPDR_PUPDR7_Pos)
 
#define GPIO_PUPDR_PUPDR7   GPIO_PUPDR_PUPDR7_Msk
 
#define GPIO_PUPDR_PUPDR7_0   (0x1U << GPIO_PUPDR_PUPDR7_Pos)
 
#define GPIO_PUPDR_PUPDR7_1   (0x2U << GPIO_PUPDR_PUPDR7_Pos)
 
#define GPIO_PUPDR_PUPDR8_Pos   (16U)
 
#define GPIO_PUPDR_PUPDR8_Msk   (0x3U << GPIO_PUPDR_PUPDR8_Pos)
 
#define GPIO_PUPDR_PUPDR8   GPIO_PUPDR_PUPDR8_Msk
 
#define GPIO_PUPDR_PUPDR8_0   (0x1U << GPIO_PUPDR_PUPDR8_Pos)
 
#define GPIO_PUPDR_PUPDR8_1   (0x2U << GPIO_PUPDR_PUPDR8_Pos)
 
#define GPIO_PUPDR_PUPDR9_Pos   (18U)
 
#define GPIO_PUPDR_PUPDR9_Msk   (0x3U << GPIO_PUPDR_PUPDR9_Pos)
 
#define GPIO_PUPDR_PUPDR9   GPIO_PUPDR_PUPDR9_Msk
 
#define GPIO_PUPDR_PUPDR9_0   (0x1U << GPIO_PUPDR_PUPDR9_Pos)
 
#define GPIO_PUPDR_PUPDR9_1   (0x2U << GPIO_PUPDR_PUPDR9_Pos)
 
#define GPIO_PUPDR_PUPDR10_Pos   (20U)
 
#define GPIO_PUPDR_PUPDR10_Msk   (0x3U << GPIO_PUPDR_PUPDR10_Pos)
 
#define GPIO_PUPDR_PUPDR10   GPIO_PUPDR_PUPDR10_Msk
 
#define GPIO_PUPDR_PUPDR10_0   (0x1U << GPIO_PUPDR_PUPDR10_Pos)
 
#define GPIO_PUPDR_PUPDR10_1   (0x2U << GPIO_PUPDR_PUPDR10_Pos)
 
#define GPIO_PUPDR_PUPDR11_Pos   (22U)
 
#define GPIO_PUPDR_PUPDR11_Msk   (0x3U << GPIO_PUPDR_PUPDR11_Pos)
 
#define GPIO_PUPDR_PUPDR11   GPIO_PUPDR_PUPDR11_Msk
 
#define GPIO_PUPDR_PUPDR11_0   (0x1U << GPIO_PUPDR_PUPDR11_Pos)
 
#define GPIO_PUPDR_PUPDR11_1   (0x2U << GPIO_PUPDR_PUPDR11_Pos)
 
#define GPIO_PUPDR_PUPDR12_Pos   (24U)
 
#define GPIO_PUPDR_PUPDR12_Msk   (0x3U << GPIO_PUPDR_PUPDR12_Pos)
 
#define GPIO_PUPDR_PUPDR12   GPIO_PUPDR_PUPDR12_Msk
 
#define GPIO_PUPDR_PUPDR12_0   (0x1U << GPIO_PUPDR_PUPDR12_Pos)
 
#define GPIO_PUPDR_PUPDR12_1   (0x2U << GPIO_PUPDR_PUPDR12_Pos)
 
#define GPIO_PUPDR_PUPDR13_Pos   (26U)
 
#define GPIO_PUPDR_PUPDR13_Msk   (0x3U << GPIO_PUPDR_PUPDR13_Pos)
 
#define GPIO_PUPDR_PUPDR13   GPIO_PUPDR_PUPDR13_Msk
 
#define GPIO_PUPDR_PUPDR13_0   (0x1U << GPIO_PUPDR_PUPDR13_Pos)
 
#define GPIO_PUPDR_PUPDR13_1   (0x2U << GPIO_PUPDR_PUPDR13_Pos)
 
#define GPIO_PUPDR_PUPDR14_Pos   (28U)
 
#define GPIO_PUPDR_PUPDR14_Msk   (0x3U << GPIO_PUPDR_PUPDR14_Pos)
 
#define GPIO_PUPDR_PUPDR14   GPIO_PUPDR_PUPDR14_Msk
 
#define GPIO_PUPDR_PUPDR14_0   (0x1U << GPIO_PUPDR_PUPDR14_Pos)
 
#define GPIO_PUPDR_PUPDR14_1   (0x2U << GPIO_PUPDR_PUPDR14_Pos)
 
#define GPIO_PUPDR_PUPDR15_Pos   (30U)
 
#define GPIO_PUPDR_PUPDR15_Msk   (0x3U << GPIO_PUPDR_PUPDR15_Pos)
 
#define GPIO_PUPDR_PUPDR15   GPIO_PUPDR_PUPDR15_Msk
 
#define GPIO_PUPDR_PUPDR15_0   (0x1U << GPIO_PUPDR_PUPDR15_Pos)
 
#define GPIO_PUPDR_PUPDR15_1   (0x2U << GPIO_PUPDR_PUPDR15_Pos)
 
#define GPIO_IDR_IDR_0   (0x00000001U)
 
#define GPIO_IDR_IDR_1   (0x00000002U)
 
#define GPIO_IDR_IDR_2   (0x00000004U)
 
#define GPIO_IDR_IDR_3   (0x00000008U)
 
#define GPIO_IDR_IDR_4   (0x00000010U)
 
#define GPIO_IDR_IDR_5   (0x00000020U)
 
#define GPIO_IDR_IDR_6   (0x00000040U)
 
#define GPIO_IDR_IDR_7   (0x00000080U)
 
#define GPIO_IDR_IDR_8   (0x00000100U)
 
#define GPIO_IDR_IDR_9   (0x00000200U)
 
#define GPIO_IDR_IDR_10   (0x00000400U)
 
#define GPIO_IDR_IDR_11   (0x00000800U)
 
#define GPIO_IDR_IDR_12   (0x00001000U)
 
#define GPIO_IDR_IDR_13   (0x00002000U)
 
#define GPIO_IDR_IDR_14   (0x00004000U)
 
#define GPIO_IDR_IDR_15   (0x00008000U)
 
#define GPIO_ODR_ODR_0   (0x00000001U)
 
#define GPIO_ODR_ODR_1   (0x00000002U)
 
#define GPIO_ODR_ODR_2   (0x00000004U)
 
#define GPIO_ODR_ODR_3   (0x00000008U)
 
#define GPIO_ODR_ODR_4   (0x00000010U)
 
#define GPIO_ODR_ODR_5   (0x00000020U)
 
#define GPIO_ODR_ODR_6   (0x00000040U)
 
#define GPIO_ODR_ODR_7   (0x00000080U)
 
#define GPIO_ODR_ODR_8   (0x00000100U)
 
#define GPIO_ODR_ODR_9   (0x00000200U)
 
#define GPIO_ODR_ODR_10   (0x00000400U)
 
#define GPIO_ODR_ODR_11   (0x00000800U)
 
#define GPIO_ODR_ODR_12   (0x00001000U)
 
#define GPIO_ODR_ODR_13   (0x00002000U)
 
#define GPIO_ODR_ODR_14   (0x00004000U)
 
#define GPIO_ODR_ODR_15   (0x00008000U)
 
#define GPIO_BSRR_BS_0   (0x00000001U)
 
#define GPIO_BSRR_BS_1   (0x00000002U)
 
#define GPIO_BSRR_BS_2   (0x00000004U)
 
#define GPIO_BSRR_BS_3   (0x00000008U)
 
#define GPIO_BSRR_BS_4   (0x00000010U)
 
#define GPIO_BSRR_BS_5   (0x00000020U)
 
#define GPIO_BSRR_BS_6   (0x00000040U)
 
#define GPIO_BSRR_BS_7   (0x00000080U)
 
#define GPIO_BSRR_BS_8   (0x00000100U)
 
#define GPIO_BSRR_BS_9   (0x00000200U)
 
#define GPIO_BSRR_BS_10   (0x00000400U)
 
#define GPIO_BSRR_BS_11   (0x00000800U)
 
#define GPIO_BSRR_BS_12   (0x00001000U)
 
#define GPIO_BSRR_BS_13   (0x00002000U)
 
#define GPIO_BSRR_BS_14   (0x00004000U)
 
#define GPIO_BSRR_BS_15   (0x00008000U)
 
#define GPIO_BSRR_BR_0   (0x00010000U)
 
#define GPIO_BSRR_BR_1   (0x00020000U)
 
#define GPIO_BSRR_BR_2   (0x00040000U)
 
#define GPIO_BSRR_BR_3   (0x00080000U)
 
#define GPIO_BSRR_BR_4   (0x00100000U)
 
#define GPIO_BSRR_BR_5   (0x00200000U)
 
#define GPIO_BSRR_BR_6   (0x00400000U)
 
#define GPIO_BSRR_BR_7   (0x00800000U)
 
#define GPIO_BSRR_BR_8   (0x01000000U)
 
#define GPIO_BSRR_BR_9   (0x02000000U)
 
#define GPIO_BSRR_BR_10   (0x04000000U)
 
#define GPIO_BSRR_BR_11   (0x08000000U)
 
#define GPIO_BSRR_BR_12   (0x10000000U)
 
#define GPIO_BSRR_BR_13   (0x20000000U)
 
#define GPIO_BSRR_BR_14   (0x40000000U)
 
#define GPIO_BSRR_BR_15   (0x80000000U)
 
#define GPIO_LCKR_LCK0_Pos   (0U)
 
#define GPIO_LCKR_LCK0_Msk   (0x1U << GPIO_LCKR_LCK0_Pos)
 
#define GPIO_LCKR_LCK0   GPIO_LCKR_LCK0_Msk
 
#define GPIO_LCKR_LCK1_Pos   (1U)
 
#define GPIO_LCKR_LCK1_Msk   (0x1U << GPIO_LCKR_LCK1_Pos)
 
#define GPIO_LCKR_LCK1   GPIO_LCKR_LCK1_Msk
 
#define GPIO_LCKR_LCK2_Pos   (2U)
 
#define GPIO_LCKR_LCK2_Msk   (0x1U << GPIO_LCKR_LCK2_Pos)
 
#define GPIO_LCKR_LCK2   GPIO_LCKR_LCK2_Msk
 
#define GPIO_LCKR_LCK3_Pos   (3U)
 
#define GPIO_LCKR_LCK3_Msk   (0x1U << GPIO_LCKR_LCK3_Pos)
 
#define GPIO_LCKR_LCK3   GPIO_LCKR_LCK3_Msk
 
#define GPIO_LCKR_LCK4_Pos   (4U)
 
#define GPIO_LCKR_LCK4_Msk   (0x1U << GPIO_LCKR_LCK4_Pos)
 
#define GPIO_LCKR_LCK4   GPIO_LCKR_LCK4_Msk
 
#define GPIO_LCKR_LCK5_Pos   (5U)
 
#define GPIO_LCKR_LCK5_Msk   (0x1U << GPIO_LCKR_LCK5_Pos)
 
#define GPIO_LCKR_LCK5   GPIO_LCKR_LCK5_Msk
 
#define GPIO_LCKR_LCK6_Pos   (6U)
 
#define GPIO_LCKR_LCK6_Msk   (0x1U << GPIO_LCKR_LCK6_Pos)
 
#define GPIO_LCKR_LCK6   GPIO_LCKR_LCK6_Msk
 
#define GPIO_LCKR_LCK7_Pos   (7U)
 
#define GPIO_LCKR_LCK7_Msk   (0x1U << GPIO_LCKR_LCK7_Pos)
 
#define GPIO_LCKR_LCK7   GPIO_LCKR_LCK7_Msk
 
#define GPIO_LCKR_LCK8_Pos   (8U)
 
#define GPIO_LCKR_LCK8_Msk   (0x1U << GPIO_LCKR_LCK8_Pos)
 
#define GPIO_LCKR_LCK8   GPIO_LCKR_LCK8_Msk
 
#define GPIO_LCKR_LCK9_Pos   (9U)
 
#define GPIO_LCKR_LCK9_Msk   (0x1U << GPIO_LCKR_LCK9_Pos)
 
#define GPIO_LCKR_LCK9   GPIO_LCKR_LCK9_Msk
 
#define GPIO_LCKR_LCK10_Pos   (10U)
 
#define GPIO_LCKR_LCK10_Msk   (0x1U << GPIO_LCKR_LCK10_Pos)
 
#define GPIO_LCKR_LCK10   GPIO_LCKR_LCK10_Msk
 
#define GPIO_LCKR_LCK11_Pos   (11U)
 
#define GPIO_LCKR_LCK11_Msk   (0x1U << GPIO_LCKR_LCK11_Pos)
 
#define GPIO_LCKR_LCK11   GPIO_LCKR_LCK11_Msk
 
#define GPIO_LCKR_LCK12_Pos   (12U)
 
#define GPIO_LCKR_LCK12_Msk   (0x1U << GPIO_LCKR_LCK12_Pos)
 
#define GPIO_LCKR_LCK12   GPIO_LCKR_LCK12_Msk
 
#define GPIO_LCKR_LCK13_Pos   (13U)
 
#define GPIO_LCKR_LCK13_Msk   (0x1U << GPIO_LCKR_LCK13_Pos)
 
#define GPIO_LCKR_LCK13   GPIO_LCKR_LCK13_Msk
 
#define GPIO_LCKR_LCK14_Pos   (14U)
 
#define GPIO_LCKR_LCK14_Msk   (0x1U << GPIO_LCKR_LCK14_Pos)
 
#define GPIO_LCKR_LCK14   GPIO_LCKR_LCK14_Msk
 
#define GPIO_LCKR_LCK15_Pos   (15U)
 
#define GPIO_LCKR_LCK15_Msk   (0x1U << GPIO_LCKR_LCK15_Pos)
 
#define GPIO_LCKR_LCK15   GPIO_LCKR_LCK15_Msk
 
#define GPIO_LCKR_LCKK_Pos   (16U)
 
#define GPIO_LCKR_LCKK_Msk   (0x1U << GPIO_LCKR_LCKK_Pos)
 
#define GPIO_LCKR_LCKK   GPIO_LCKR_LCKK_Msk
 
#define GPIO_AFRL_AFSEL0_Pos   (0U)
 
#define GPIO_AFRL_AFSEL0_Msk   (0xFU << GPIO_AFRL_AFSEL0_Pos)
 
#define GPIO_AFRL_AFSEL0   GPIO_AFRL_AFSEL0_Msk
 
#define GPIO_AFRL_AFSEL1_Pos   (4U)
 
#define GPIO_AFRL_AFSEL1_Msk   (0xFU << GPIO_AFRL_AFSEL1_Pos)
 
#define GPIO_AFRL_AFSEL1   GPIO_AFRL_AFSEL1_Msk
 
#define GPIO_AFRL_AFSEL2_Pos   (8U)
 
#define GPIO_AFRL_AFSEL2_Msk   (0xFU << GPIO_AFRL_AFSEL2_Pos)
 
#define GPIO_AFRL_AFSEL2   GPIO_AFRL_AFSEL2_Msk
 
#define GPIO_AFRL_AFSEL3_Pos   (12U)
 
#define GPIO_AFRL_AFSEL3_Msk   (0xFU << GPIO_AFRL_AFSEL3_Pos)
 
#define GPIO_AFRL_AFSEL3   GPIO_AFRL_AFSEL3_Msk
 
#define GPIO_AFRL_AFSEL4_Pos   (16U)
 
#define GPIO_AFRL_AFSEL4_Msk   (0xFU << GPIO_AFRL_AFSEL4_Pos)
 
#define GPIO_AFRL_AFSEL4   GPIO_AFRL_AFSEL4_Msk
 
#define GPIO_AFRL_AFSEL5_Pos   (20U)
 
#define GPIO_AFRL_AFSEL5_Msk   (0xFU << GPIO_AFRL_AFSEL5_Pos)
 
#define GPIO_AFRL_AFSEL5   GPIO_AFRL_AFSEL5_Msk
 
#define GPIO_AFRL_AFSEL6_Pos   (24U)
 
#define GPIO_AFRL_AFSEL6_Msk   (0xFU << GPIO_AFRL_AFSEL6_Pos)
 
#define GPIO_AFRL_AFSEL6   GPIO_AFRL_AFSEL6_Msk
 
#define GPIO_AFRL_AFSEL7_Pos   (28U)
 
#define GPIO_AFRL_AFSEL7_Msk   (0xFU << GPIO_AFRL_AFSEL7_Pos)
 
#define GPIO_AFRL_AFSEL7   GPIO_AFRL_AFSEL7_Msk
 
#define GPIO_AFRH_AFSEL8_Pos   (0U)
 
#define GPIO_AFRH_AFSEL8_Msk   (0xFU << GPIO_AFRH_AFSEL8_Pos)
 
#define GPIO_AFRH_AFSEL8   GPIO_AFRH_AFSEL8_Msk
 
#define GPIO_AFRH_AFSEL9_Pos   (4U)
 
#define GPIO_AFRH_AFSEL9_Msk   (0xFU << GPIO_AFRH_AFSEL9_Pos)
 
#define GPIO_AFRH_AFSEL9   GPIO_AFRH_AFSEL9_Msk
 
#define GPIO_AFRH_AFSEL10_Pos   (8U)
 
#define GPIO_AFRH_AFSEL10_Msk   (0xFU << GPIO_AFRH_AFSEL10_Pos)
 
#define GPIO_AFRH_AFSEL10   GPIO_AFRH_AFSEL10_Msk
 
#define GPIO_AFRH_AFSEL11_Pos   (12U)
 
#define GPIO_AFRH_AFSEL11_Msk   (0xFU << GPIO_AFRH_AFSEL11_Pos)
 
#define GPIO_AFRH_AFSEL11   GPIO_AFRH_AFSEL11_Msk
 
#define GPIO_AFRH_AFSEL12_Pos   (16U)
 
#define GPIO_AFRH_AFSEL12_Msk   (0xFU << GPIO_AFRH_AFSEL12_Pos)
 
#define GPIO_AFRH_AFSEL12   GPIO_AFRH_AFSEL12_Msk
 
#define GPIO_AFRH_AFSEL13_Pos   (20U)
 
#define GPIO_AFRH_AFSEL13_Msk   (0xFU << GPIO_AFRH_AFSEL13_Pos)
 
#define GPIO_AFRH_AFSEL13   GPIO_AFRH_AFSEL13_Msk
 
#define GPIO_AFRH_AFSEL14_Pos   (24U)
 
#define GPIO_AFRH_AFSEL14_Msk   (0xFU << GPIO_AFRH_AFSEL14_Pos)
 
#define GPIO_AFRH_AFSEL14   GPIO_AFRH_AFSEL14_Msk
 
#define GPIO_AFRH_AFSEL15_Pos   (28U)
 
#define GPIO_AFRH_AFSEL15_Msk   (0xFU << GPIO_AFRH_AFSEL15_Pos)
 
#define GPIO_AFRH_AFSEL15   GPIO_AFRH_AFSEL15_Msk
 
#define GPIO_BRR_BR_0   (0x00000001U)
 
#define GPIO_BRR_BR_1   (0x00000002U)
 
#define GPIO_BRR_BR_2   (0x00000004U)
 
#define GPIO_BRR_BR_3   (0x00000008U)
 
#define GPIO_BRR_BR_4   (0x00000010U)
 
#define GPIO_BRR_BR_5   (0x00000020U)
 
#define GPIO_BRR_BR_6   (0x00000040U)
 
#define GPIO_BRR_BR_7   (0x00000080U)
 
#define GPIO_BRR_BR_8   (0x00000100U)
 
#define GPIO_BRR_BR_9   (0x00000200U)
 
#define GPIO_BRR_BR_10   (0x00000400U)
 
#define GPIO_BRR_BR_11   (0x00000800U)
 
#define GPIO_BRR_BR_12   (0x00001000U)
 
#define GPIO_BRR_BR_13   (0x00002000U)
 
#define GPIO_BRR_BR_14   (0x00004000U)
 
#define GPIO_BRR_BR_15   (0x00008000U)
 
#define I2C_CR1_PE_Pos   (0U)
 
#define I2C_CR1_PE_Msk   (0x1U << I2C_CR1_PE_Pos)
 
#define I2C_CR1_PE   I2C_CR1_PE_Msk
 
#define I2C_CR1_SMBUS_Pos   (1U)
 
#define I2C_CR1_SMBUS_Msk   (0x1U << I2C_CR1_SMBUS_Pos)
 
#define I2C_CR1_SMBUS   I2C_CR1_SMBUS_Msk
 
#define I2C_CR1_SMBTYPE_Pos   (3U)
 
#define I2C_CR1_SMBTYPE_Msk   (0x1U << I2C_CR1_SMBTYPE_Pos)
 
#define I2C_CR1_SMBTYPE   I2C_CR1_SMBTYPE_Msk
 
#define I2C_CR1_ENARP_Pos   (4U)
 
#define I2C_CR1_ENARP_Msk   (0x1U << I2C_CR1_ENARP_Pos)
 
#define I2C_CR1_ENARP   I2C_CR1_ENARP_Msk
 
#define I2C_CR1_ENPEC_Pos   (5U)
 
#define I2C_CR1_ENPEC_Msk   (0x1U << I2C_CR1_ENPEC_Pos)
 
#define I2C_CR1_ENPEC   I2C_CR1_ENPEC_Msk
 
#define I2C_CR1_ENGC_Pos   (6U)
 
#define I2C_CR1_ENGC_Msk   (0x1U << I2C_CR1_ENGC_Pos)
 
#define I2C_CR1_ENGC   I2C_CR1_ENGC_Msk
 
#define I2C_CR1_NOSTRETCH_Pos   (7U)
 
#define I2C_CR1_NOSTRETCH_Msk   (0x1U << I2C_CR1_NOSTRETCH_Pos)
 
#define I2C_CR1_NOSTRETCH   I2C_CR1_NOSTRETCH_Msk
 
#define I2C_CR1_START_Pos   (8U)
 
#define I2C_CR1_START_Msk   (0x1U << I2C_CR1_START_Pos)
 
#define I2C_CR1_START   I2C_CR1_START_Msk
 
#define I2C_CR1_STOP_Pos   (9U)
 
#define I2C_CR1_STOP_Msk   (0x1U << I2C_CR1_STOP_Pos)
 
#define I2C_CR1_STOP   I2C_CR1_STOP_Msk
 
#define I2C_CR1_ACK_Pos   (10U)
 
#define I2C_CR1_ACK_Msk   (0x1U << I2C_CR1_ACK_Pos)
 
#define I2C_CR1_ACK   I2C_CR1_ACK_Msk
 
#define I2C_CR1_POS_Pos   (11U)
 
#define I2C_CR1_POS_Msk   (0x1U << I2C_CR1_POS_Pos)
 
#define I2C_CR1_POS   I2C_CR1_POS_Msk
 
#define I2C_CR1_PEC_Pos   (12U)
 
#define I2C_CR1_PEC_Msk   (0x1U << I2C_CR1_PEC_Pos)
 
#define I2C_CR1_PEC   I2C_CR1_PEC_Msk
 
#define I2C_CR1_ALERT_Pos   (13U)
 
#define I2C_CR1_ALERT_Msk   (0x1U << I2C_CR1_ALERT_Pos)
 
#define I2C_CR1_ALERT   I2C_CR1_ALERT_Msk
 
#define I2C_CR1_SWRST_Pos   (15U)
 
#define I2C_CR1_SWRST_Msk   (0x1U << I2C_CR1_SWRST_Pos)
 
#define I2C_CR1_SWRST   I2C_CR1_SWRST_Msk
 
#define I2C_CR2_FREQ_Pos   (0U)
 
#define I2C_CR2_FREQ_Msk   (0x3FU << I2C_CR2_FREQ_Pos)
 
#define I2C_CR2_FREQ   I2C_CR2_FREQ_Msk
 
#define I2C_CR2_FREQ_0   (0x01U << I2C_CR2_FREQ_Pos)
 
#define I2C_CR2_FREQ_1   (0x02U << I2C_CR2_FREQ_Pos)
 
#define I2C_CR2_FREQ_2   (0x04U << I2C_CR2_FREQ_Pos)
 
#define I2C_CR2_FREQ_3   (0x08U << I2C_CR2_FREQ_Pos)
 
#define I2C_CR2_FREQ_4   (0x10U << I2C_CR2_FREQ_Pos)
 
#define I2C_CR2_FREQ_5   (0x20U << I2C_CR2_FREQ_Pos)
 
#define I2C_CR2_ITERREN_Pos   (8U)
 
#define I2C_CR2_ITERREN_Msk   (0x1U << I2C_CR2_ITERREN_Pos)
 
#define I2C_CR2_ITERREN   I2C_CR2_ITERREN_Msk
 
#define I2C_CR2_ITEVTEN_Pos   (9U)
 
#define I2C_CR2_ITEVTEN_Msk   (0x1U << I2C_CR2_ITEVTEN_Pos)
 
#define I2C_CR2_ITEVTEN   I2C_CR2_ITEVTEN_Msk
 
#define I2C_CR2_ITBUFEN_Pos   (10U)
 
#define I2C_CR2_ITBUFEN_Msk   (0x1U << I2C_CR2_ITBUFEN_Pos)
 
#define I2C_CR2_ITBUFEN   I2C_CR2_ITBUFEN_Msk
 
#define I2C_CR2_DMAEN_Pos   (11U)
 
#define I2C_CR2_DMAEN_Msk   (0x1U << I2C_CR2_DMAEN_Pos)
 
#define I2C_CR2_DMAEN   I2C_CR2_DMAEN_Msk
 
#define I2C_CR2_LAST_Pos   (12U)
 
#define I2C_CR2_LAST_Msk   (0x1U << I2C_CR2_LAST_Pos)
 
#define I2C_CR2_LAST   I2C_CR2_LAST_Msk
 
#define I2C_OAR1_ADD1_7   (0x000000FEU)
 
#define I2C_OAR1_ADD8_9   (0x00000300U)
 
#define I2C_OAR1_ADD0_Pos   (0U)
 
#define I2C_OAR1_ADD0_Msk   (0x1U << I2C_OAR1_ADD0_Pos)
 
#define I2C_OAR1_ADD0   I2C_OAR1_ADD0_Msk
 
#define I2C_OAR1_ADD1_Pos   (1U)
 
#define I2C_OAR1_ADD1_Msk   (0x1U << I2C_OAR1_ADD1_Pos)
 
#define I2C_OAR1_ADD1   I2C_OAR1_ADD1_Msk
 
#define I2C_OAR1_ADD2_Pos   (2U)
 
#define I2C_OAR1_ADD2_Msk   (0x1U << I2C_OAR1_ADD2_Pos)
 
#define I2C_OAR1_ADD2   I2C_OAR1_ADD2_Msk
 
#define I2C_OAR1_ADD3_Pos   (3U)
 
#define I2C_OAR1_ADD3_Msk   (0x1U << I2C_OAR1_ADD3_Pos)
 
#define I2C_OAR1_ADD3   I2C_OAR1_ADD3_Msk
 
#define I2C_OAR1_ADD4_Pos   (4U)
 
#define I2C_OAR1_ADD4_Msk   (0x1U << I2C_OAR1_ADD4_Pos)
 
#define I2C_OAR1_ADD4   I2C_OAR1_ADD4_Msk
 
#define I2C_OAR1_ADD5_Pos   (5U)
 
#define I2C_OAR1_ADD5_Msk   (0x1U << I2C_OAR1_ADD5_Pos)
 
#define I2C_OAR1_ADD5   I2C_OAR1_ADD5_Msk
 
#define I2C_OAR1_ADD6_Pos   (6U)
 
#define I2C_OAR1_ADD6_Msk   (0x1U << I2C_OAR1_ADD6_Pos)
 
#define I2C_OAR1_ADD6   I2C_OAR1_ADD6_Msk
 
#define I2C_OAR1_ADD7_Pos   (7U)
 
#define I2C_OAR1_ADD7_Msk   (0x1U << I2C_OAR1_ADD7_Pos)
 
#define I2C_OAR1_ADD7   I2C_OAR1_ADD7_Msk
 
#define I2C_OAR1_ADD8_Pos   (8U)
 
#define I2C_OAR1_ADD8_Msk   (0x1U << I2C_OAR1_ADD8_Pos)
 
#define I2C_OAR1_ADD8   I2C_OAR1_ADD8_Msk
 
#define I2C_OAR1_ADD9_Pos   (9U)
 
#define I2C_OAR1_ADD9_Msk   (0x1U << I2C_OAR1_ADD9_Pos)
 
#define I2C_OAR1_ADD9   I2C_OAR1_ADD9_Msk
 
#define I2C_OAR1_ADDMODE_Pos   (15U)
 
#define I2C_OAR1_ADDMODE_Msk   (0x1U << I2C_OAR1_ADDMODE_Pos)
 
#define I2C_OAR1_ADDMODE   I2C_OAR1_ADDMODE_Msk
 
#define I2C_OAR2_ENDUAL_Pos   (0U)
 
#define I2C_OAR2_ENDUAL_Msk   (0x1U << I2C_OAR2_ENDUAL_Pos)
 
#define I2C_OAR2_ENDUAL   I2C_OAR2_ENDUAL_Msk
 
#define I2C_OAR2_ADD2_Pos   (1U)
 
#define I2C_OAR2_ADD2_Msk   (0x7FU << I2C_OAR2_ADD2_Pos)
 
#define I2C_OAR2_ADD2   I2C_OAR2_ADD2_Msk
 
#define I2C_DR_DR_Pos   (0U)
 
#define I2C_DR_DR_Msk   (0xFFU << I2C_DR_DR_Pos)
 
#define I2C_DR_DR   I2C_DR_DR_Msk
 
#define I2C_SR1_SB_Pos   (0U)
 
#define I2C_SR1_SB_Msk   (0x1U << I2C_SR1_SB_Pos)
 
#define I2C_SR1_SB   I2C_SR1_SB_Msk
 
#define I2C_SR1_ADDR_Pos   (1U)
 
#define I2C_SR1_ADDR_Msk   (0x1U << I2C_SR1_ADDR_Pos)
 
#define I2C_SR1_ADDR   I2C_SR1_ADDR_Msk
 
#define I2C_SR1_BTF_Pos   (2U)
 
#define I2C_SR1_BTF_Msk   (0x1U << I2C_SR1_BTF_Pos)
 
#define I2C_SR1_BTF   I2C_SR1_BTF_Msk
 
#define I2C_SR1_ADD10_Pos   (3U)
 
#define I2C_SR1_ADD10_Msk   (0x1U << I2C_SR1_ADD10_Pos)
 
#define I2C_SR1_ADD10   I2C_SR1_ADD10_Msk
 
#define I2C_SR1_STOPF_Pos   (4U)
 
#define I2C_SR1_STOPF_Msk   (0x1U << I2C_SR1_STOPF_Pos)
 
#define I2C_SR1_STOPF   I2C_SR1_STOPF_Msk
 
#define I2C_SR1_RXNE_Pos   (6U)
 
#define I2C_SR1_RXNE_Msk   (0x1U << I2C_SR1_RXNE_Pos)
 
#define I2C_SR1_RXNE   I2C_SR1_RXNE_Msk
 
#define I2C_SR1_TXE_Pos   (7U)
 
#define I2C_SR1_TXE_Msk   (0x1U << I2C_SR1_TXE_Pos)
 
#define I2C_SR1_TXE   I2C_SR1_TXE_Msk
 
#define I2C_SR1_BERR_Pos   (8U)
 
#define I2C_SR1_BERR_Msk   (0x1U << I2C_SR1_BERR_Pos)
 
#define I2C_SR1_BERR   I2C_SR1_BERR_Msk
 
#define I2C_SR1_ARLO_Pos   (9U)
 
#define I2C_SR1_ARLO_Msk   (0x1U << I2C_SR1_ARLO_Pos)
 
#define I2C_SR1_ARLO   I2C_SR1_ARLO_Msk
 
#define I2C_SR1_AF_Pos   (10U)
 
#define I2C_SR1_AF_Msk   (0x1U << I2C_SR1_AF_Pos)
 
#define I2C_SR1_AF   I2C_SR1_AF_Msk
 
#define I2C_SR1_OVR_Pos   (11U)
 
#define I2C_SR1_OVR_Msk   (0x1U << I2C_SR1_OVR_Pos)
 
#define I2C_SR1_OVR   I2C_SR1_OVR_Msk
 
#define I2C_SR1_PECERR_Pos   (12U)
 
#define I2C_SR1_PECERR_Msk   (0x1U << I2C_SR1_PECERR_Pos)
 
#define I2C_SR1_PECERR   I2C_SR1_PECERR_Msk
 
#define I2C_SR1_TIMEOUT_Pos   (14U)
 
#define I2C_SR1_TIMEOUT_Msk   (0x1U << I2C_SR1_TIMEOUT_Pos)
 
#define I2C_SR1_TIMEOUT   I2C_SR1_TIMEOUT_Msk
 
#define I2C_SR1_SMBALERT_Pos   (15U)
 
#define I2C_SR1_SMBALERT_Msk   (0x1U << I2C_SR1_SMBALERT_Pos)
 
#define I2C_SR1_SMBALERT   I2C_SR1_SMBALERT_Msk
 
#define I2C_SR2_MSL_Pos   (0U)
 
#define I2C_SR2_MSL_Msk   (0x1U << I2C_SR2_MSL_Pos)
 
#define I2C_SR2_MSL   I2C_SR2_MSL_Msk
 
#define I2C_SR2_BUSY_Pos   (1U)
 
#define I2C_SR2_BUSY_Msk   (0x1U << I2C_SR2_BUSY_Pos)
 
#define I2C_SR2_BUSY   I2C_SR2_BUSY_Msk
 
#define I2C_SR2_TRA_Pos   (2U)
 
#define I2C_SR2_TRA_Msk   (0x1U << I2C_SR2_TRA_Pos)
 
#define I2C_SR2_TRA   I2C_SR2_TRA_Msk
 
#define I2C_SR2_GENCALL_Pos   (4U)
 
#define I2C_SR2_GENCALL_Msk   (0x1U << I2C_SR2_GENCALL_Pos)
 
#define I2C_SR2_GENCALL   I2C_SR2_GENCALL_Msk
 
#define I2C_SR2_SMBDEFAULT_Pos   (5U)
 
#define I2C_SR2_SMBDEFAULT_Msk   (0x1U << I2C_SR2_SMBDEFAULT_Pos)
 
#define I2C_SR2_SMBDEFAULT   I2C_SR2_SMBDEFAULT_Msk
 
#define I2C_SR2_SMBHOST_Pos   (6U)
 
#define I2C_SR2_SMBHOST_Msk   (0x1U << I2C_SR2_SMBHOST_Pos)
 
#define I2C_SR2_SMBHOST   I2C_SR2_SMBHOST_Msk
 
#define I2C_SR2_DUALF_Pos   (7U)
 
#define I2C_SR2_DUALF_Msk   (0x1U << I2C_SR2_DUALF_Pos)
 
#define I2C_SR2_DUALF   I2C_SR2_DUALF_Msk
 
#define I2C_SR2_PEC_Pos   (8U)
 
#define I2C_SR2_PEC_Msk   (0xFFU << I2C_SR2_PEC_Pos)
 
#define I2C_SR2_PEC   I2C_SR2_PEC_Msk
 
#define I2C_CCR_CCR_Pos   (0U)
 
#define I2C_CCR_CCR_Msk   (0xFFFU << I2C_CCR_CCR_Pos)
 
#define I2C_CCR_CCR   I2C_CCR_CCR_Msk
 
#define I2C_CCR_DUTY_Pos   (14U)
 
#define I2C_CCR_DUTY_Msk   (0x1U << I2C_CCR_DUTY_Pos)
 
#define I2C_CCR_DUTY   I2C_CCR_DUTY_Msk
 
#define I2C_CCR_FS_Pos   (15U)
 
#define I2C_CCR_FS_Msk   (0x1U << I2C_CCR_FS_Pos)
 
#define I2C_CCR_FS   I2C_CCR_FS_Msk
 
#define I2C_TRISE_TRISE_Pos   (0U)
 
#define I2C_TRISE_TRISE_Msk   (0x3FU << I2C_TRISE_TRISE_Pos)
 
#define I2C_TRISE_TRISE   I2C_TRISE_TRISE_Msk
 
#define IWDG_KR_KEY_Pos   (0U)
 
#define IWDG_KR_KEY_Msk   (0xFFFFU << IWDG_KR_KEY_Pos)
 
#define IWDG_KR_KEY   IWDG_KR_KEY_Msk
 
#define IWDG_PR_PR_Pos   (0U)
 
#define IWDG_PR_PR_Msk   (0x7U << IWDG_PR_PR_Pos)
 
#define IWDG_PR_PR   IWDG_PR_PR_Msk
 
#define IWDG_PR_PR_0   (0x1U << IWDG_PR_PR_Pos)
 
#define IWDG_PR_PR_1   (0x2U << IWDG_PR_PR_Pos)
 
#define IWDG_PR_PR_2   (0x4U << IWDG_PR_PR_Pos)
 
#define IWDG_RLR_RL_Pos   (0U)
 
#define IWDG_RLR_RL_Msk   (0xFFFU << IWDG_RLR_RL_Pos)
 
#define IWDG_RLR_RL   IWDG_RLR_RL_Msk
 
#define IWDG_SR_PVU_Pos   (0U)
 
#define IWDG_SR_PVU_Msk   (0x1U << IWDG_SR_PVU_Pos)
 
#define IWDG_SR_PVU   IWDG_SR_PVU_Msk
 
#define IWDG_SR_RVU_Pos   (1U)
 
#define IWDG_SR_RVU_Msk   (0x1U << IWDG_SR_RVU_Pos)
 
#define IWDG_SR_RVU   IWDG_SR_RVU_Msk
 
#define LCD_CR_LCDEN_Pos   (0U)
 
#define LCD_CR_LCDEN_Msk   (0x1U << LCD_CR_LCDEN_Pos)
 
#define LCD_CR_LCDEN   LCD_CR_LCDEN_Msk
 
#define LCD_CR_VSEL_Pos   (1U)
 
#define LCD_CR_VSEL_Msk   (0x1U << LCD_CR_VSEL_Pos)
 
#define LCD_CR_VSEL   LCD_CR_VSEL_Msk
 
#define LCD_CR_DUTY_Pos   (2U)
 
#define LCD_CR_DUTY_Msk   (0x7U << LCD_CR_DUTY_Pos)
 
#define LCD_CR_DUTY   LCD_CR_DUTY_Msk
 
#define LCD_CR_DUTY_0   (0x1U << LCD_CR_DUTY_Pos)
 
#define LCD_CR_DUTY_1   (0x2U << LCD_CR_DUTY_Pos)
 
#define LCD_CR_DUTY_2   (0x4U << LCD_CR_DUTY_Pos)
 
#define LCD_CR_BIAS_Pos   (5U)
 
#define LCD_CR_BIAS_Msk   (0x3U << LCD_CR_BIAS_Pos)
 
#define LCD_CR_BIAS   LCD_CR_BIAS_Msk
 
#define LCD_CR_BIAS_0   (0x1U << LCD_CR_BIAS_Pos)
 
#define LCD_CR_BIAS_1   (0x2U << LCD_CR_BIAS_Pos)
 
#define LCD_CR_MUX_SEG_Pos   (7U)
 
#define LCD_CR_MUX_SEG_Msk   (0x1U << LCD_CR_MUX_SEG_Pos)
 
#define LCD_CR_MUX_SEG   LCD_CR_MUX_SEG_Msk
 
#define LCD_FCR_HD_Pos   (0U)
 
#define LCD_FCR_HD_Msk   (0x1U << LCD_FCR_HD_Pos)
 
#define LCD_FCR_HD   LCD_FCR_HD_Msk
 
#define LCD_FCR_SOFIE_Pos   (1U)
 
#define LCD_FCR_SOFIE_Msk   (0x1U << LCD_FCR_SOFIE_Pos)
 
#define LCD_FCR_SOFIE   LCD_FCR_SOFIE_Msk
 
#define LCD_FCR_UDDIE_Pos   (3U)
 
#define LCD_FCR_UDDIE_Msk   (0x1U << LCD_FCR_UDDIE_Pos)
 
#define LCD_FCR_UDDIE   LCD_FCR_UDDIE_Msk
 
#define LCD_FCR_PON_Pos   (4U)
 
#define LCD_FCR_PON_Msk   (0x7U << LCD_FCR_PON_Pos)
 
#define LCD_FCR_PON   LCD_FCR_PON_Msk
 
#define LCD_FCR_PON_0   (0x1U << LCD_FCR_PON_Pos)
 
#define LCD_FCR_PON_1   (0x2U << LCD_FCR_PON_Pos)
 
#define LCD_FCR_PON_2   (0x4U << LCD_FCR_PON_Pos)
 
#define LCD_FCR_DEAD_Pos   (7U)
 
#define LCD_FCR_DEAD_Msk   (0x7U << LCD_FCR_DEAD_Pos)
 
#define LCD_FCR_DEAD   LCD_FCR_DEAD_Msk
 
#define LCD_FCR_DEAD_0   (0x1U << LCD_FCR_DEAD_Pos)
 
#define LCD_FCR_DEAD_1   (0x2U << LCD_FCR_DEAD_Pos)
 
#define LCD_FCR_DEAD_2   (0x4U << LCD_FCR_DEAD_Pos)
 
#define LCD_FCR_CC_Pos   (10U)
 
#define LCD_FCR_CC_Msk   (0x7U << LCD_FCR_CC_Pos)
 
#define LCD_FCR_CC   LCD_FCR_CC_Msk
 
#define LCD_FCR_CC_0   (0x1U << LCD_FCR_CC_Pos)
 
#define LCD_FCR_CC_1   (0x2U << LCD_FCR_CC_Pos)
 
#define LCD_FCR_CC_2   (0x4U << LCD_FCR_CC_Pos)
 
#define LCD_FCR_BLINKF_Pos   (13U)
 
#define LCD_FCR_BLINKF_Msk   (0x7U << LCD_FCR_BLINKF_Pos)
 
#define LCD_FCR_BLINKF   LCD_FCR_BLINKF_Msk
 
#define LCD_FCR_BLINKF_0   (0x1U << LCD_FCR_BLINKF_Pos)
 
#define LCD_FCR_BLINKF_1   (0x2U << LCD_FCR_BLINKF_Pos)
 
#define LCD_FCR_BLINKF_2   (0x4U << LCD_FCR_BLINKF_Pos)
 
#define LCD_FCR_BLINK_Pos   (16U)
 
#define LCD_FCR_BLINK_Msk   (0x3U << LCD_FCR_BLINK_Pos)
 
#define LCD_FCR_BLINK   LCD_FCR_BLINK_Msk
 
#define LCD_FCR_BLINK_0   (0x1U << LCD_FCR_BLINK_Pos)
 
#define LCD_FCR_BLINK_1   (0x2U << LCD_FCR_BLINK_Pos)
 
#define LCD_FCR_DIV_Pos   (18U)
 
#define LCD_FCR_DIV_Msk   (0xFU << LCD_FCR_DIV_Pos)
 
#define LCD_FCR_DIV   LCD_FCR_DIV_Msk
 
#define LCD_FCR_PS_Pos   (22U)
 
#define LCD_FCR_PS_Msk   (0xFU << LCD_FCR_PS_Pos)
 
#define LCD_FCR_PS   LCD_FCR_PS_Msk
 
#define LCD_SR_ENS_Pos   (0U)
 
#define LCD_SR_ENS_Msk   (0x1U << LCD_SR_ENS_Pos)
 
#define LCD_SR_ENS   LCD_SR_ENS_Msk
 
#define LCD_SR_SOF_Pos   (1U)
 
#define LCD_SR_SOF_Msk   (0x1U << LCD_SR_SOF_Pos)
 
#define LCD_SR_SOF   LCD_SR_SOF_Msk
 
#define LCD_SR_UDR_Pos   (2U)
 
#define LCD_SR_UDR_Msk   (0x1U << LCD_SR_UDR_Pos)
 
#define LCD_SR_UDR   LCD_SR_UDR_Msk
 
#define LCD_SR_UDD_Pos   (3U)
 
#define LCD_SR_UDD_Msk   (0x1U << LCD_SR_UDD_Pos)
 
#define LCD_SR_UDD   LCD_SR_UDD_Msk
 
#define LCD_SR_RDY_Pos   (4U)
 
#define LCD_SR_RDY_Msk   (0x1U << LCD_SR_RDY_Pos)
 
#define LCD_SR_RDY   LCD_SR_RDY_Msk
 
#define LCD_SR_FCRSR_Pos   (5U)
 
#define LCD_SR_FCRSR_Msk   (0x1U << LCD_SR_FCRSR_Pos)
 
#define LCD_SR_FCRSR   LCD_SR_FCRSR_Msk
 
#define LCD_CLR_SOFC_Pos   (1U)
 
#define LCD_CLR_SOFC_Msk   (0x1U << LCD_CLR_SOFC_Pos)
 
#define LCD_CLR_SOFC   LCD_CLR_SOFC_Msk
 
#define LCD_CLR_UDDC_Pos   (3U)
 
#define LCD_CLR_UDDC_Msk   (0x1U << LCD_CLR_UDDC_Pos)
 
#define LCD_CLR_UDDC   LCD_CLR_UDDC_Msk
 
#define LCD_RAM_SEGMENT_DATA_Pos   (0U)
 
#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)
 
#define LCD_RAM_SEGMENT_DATA   LCD_RAM_SEGMENT_DATA_Msk
 
#define PWR_PVD_SUPPORT
 
#define PWR_CR_LPSDSR_Pos   (0U)
 
#define PWR_CR_LPSDSR_Msk   (0x1U << PWR_CR_LPSDSR_Pos)
 
#define PWR_CR_LPSDSR   PWR_CR_LPSDSR_Msk
 
#define PWR_CR_PDDS_Pos   (1U)
 
#define PWR_CR_PDDS_Msk   (0x1U << PWR_CR_PDDS_Pos)
 
#define PWR_CR_PDDS   PWR_CR_PDDS_Msk
 
#define PWR_CR_CWUF_Pos   (2U)
 
#define PWR_CR_CWUF_Msk   (0x1U << PWR_CR_CWUF_Pos)
 
#define PWR_CR_CWUF   PWR_CR_CWUF_Msk
 
#define PWR_CR_CSBF_Pos   (3U)
 
#define PWR_CR_CSBF_Msk   (0x1U << PWR_CR_CSBF_Pos)
 
#define PWR_CR_CSBF   PWR_CR_CSBF_Msk
 
#define PWR_CR_PVDE_Pos   (4U)
 
#define PWR_CR_PVDE_Msk   (0x1U << PWR_CR_PVDE_Pos)
 
#define PWR_CR_PVDE   PWR_CR_PVDE_Msk
 
#define PWR_CR_PLS_Pos   (5U)
 
#define PWR_CR_PLS_Msk   (0x7U << PWR_CR_PLS_Pos)
 
#define PWR_CR_PLS   PWR_CR_PLS_Msk
 
#define PWR_CR_PLS_0   (0x1U << PWR_CR_PLS_Pos)
 
#define PWR_CR_PLS_1   (0x2U << PWR_CR_PLS_Pos)
 
#define PWR_CR_PLS_2   (0x4U << PWR_CR_PLS_Pos)
 
#define PWR_CR_PLS_LEV0   (0x00000000U)
 
#define PWR_CR_PLS_LEV1   (0x00000020U)
 
#define PWR_CR_PLS_LEV2   (0x00000040U)
 
#define PWR_CR_PLS_LEV3   (0x00000060U)
 
#define PWR_CR_PLS_LEV4   (0x00000080U)
 
#define PWR_CR_PLS_LEV5   (0x000000A0U)
 
#define PWR_CR_PLS_LEV6   (0x000000C0U)
 
#define PWR_CR_PLS_LEV7   (0x000000E0U)
 
#define PWR_CR_DBP_Pos   (8U)
 
#define PWR_CR_DBP_Msk   (0x1U << PWR_CR_DBP_Pos)
 
#define PWR_CR_DBP   PWR_CR_DBP_Msk
 
#define PWR_CR_ULP_Pos   (9U)
 
#define PWR_CR_ULP_Msk   (0x1U << PWR_CR_ULP_Pos)
 
#define PWR_CR_ULP   PWR_CR_ULP_Msk
 
#define PWR_CR_FWU_Pos   (10U)
 
#define PWR_CR_FWU_Msk   (0x1U << PWR_CR_FWU_Pos)
 
#define PWR_CR_FWU   PWR_CR_FWU_Msk
 
#define PWR_CR_VOS_Pos   (11U)
 
#define PWR_CR_VOS_Msk   (0x3U << PWR_CR_VOS_Pos)
 
#define PWR_CR_VOS   PWR_CR_VOS_Msk
 
#define PWR_CR_VOS_0   (0x1U << PWR_CR_VOS_Pos)
 
#define PWR_CR_VOS_1   (0x2U << PWR_CR_VOS_Pos)
 
#define PWR_CR_LPRUN_Pos   (14U)
 
#define PWR_CR_LPRUN_Msk   (0x1U << PWR_CR_LPRUN_Pos)
 
#define PWR_CR_LPRUN   PWR_CR_LPRUN_Msk
 
#define PWR_CSR_WUF_Pos   (0U)
 
#define PWR_CSR_WUF_Msk   (0x1U << PWR_CSR_WUF_Pos)
 
#define PWR_CSR_WUF   PWR_CSR_WUF_Msk
 
#define PWR_CSR_SBF_Pos   (1U)
 
#define PWR_CSR_SBF_Msk   (0x1U << PWR_CSR_SBF_Pos)
 
#define PWR_CSR_SBF   PWR_CSR_SBF_Msk
 
#define PWR_CSR_PVDO_Pos   (2U)
 
#define PWR_CSR_PVDO_Msk   (0x1U << PWR_CSR_PVDO_Pos)
 
#define PWR_CSR_PVDO   PWR_CSR_PVDO_Msk
 
#define PWR_CSR_VREFINTRDYF_Pos   (3U)
 
#define PWR_CSR_VREFINTRDYF_Msk   (0x1U << PWR_CSR_VREFINTRDYF_Pos)
 
#define PWR_CSR_VREFINTRDYF   PWR_CSR_VREFINTRDYF_Msk
 
#define PWR_CSR_VOSF_Pos   (4U)
 
#define PWR_CSR_VOSF_Msk   (0x1U << PWR_CSR_VOSF_Pos)
 
#define PWR_CSR_VOSF   PWR_CSR_VOSF_Msk
 
#define PWR_CSR_REGLPF_Pos   (5U)
 
#define PWR_CSR_REGLPF_Msk   (0x1U << PWR_CSR_REGLPF_Pos)
 
#define PWR_CSR_REGLPF   PWR_CSR_REGLPF_Msk
 
#define PWR_CSR_EWUP1_Pos   (8U)
 
#define PWR_CSR_EWUP1_Msk   (0x1U << PWR_CSR_EWUP1_Pos)
 
#define PWR_CSR_EWUP1   PWR_CSR_EWUP1_Msk
 
#define PWR_CSR_EWUP2_Pos   (9U)
 
#define PWR_CSR_EWUP2_Msk   (0x1U << PWR_CSR_EWUP2_Pos)
 
#define PWR_CSR_EWUP2   PWR_CSR_EWUP2_Msk
 
#define PWR_CSR_EWUP3_Pos   (10U)
 
#define PWR_CSR_EWUP3_Msk   (0x1U << PWR_CSR_EWUP3_Pos)
 
#define PWR_CSR_EWUP3   PWR_CSR_EWUP3_Msk
 
#define RCC_LSECSS_SUPPORT
 
#define RCC_CR_HSION_Pos   (0U)
 
#define RCC_CR_HSION_Msk   (0x1U << RCC_CR_HSION_Pos)
 
#define RCC_CR_HSION   RCC_CR_HSION_Msk
 
#define RCC_CR_HSIRDY_Pos   (1U)
 
#define RCC_CR_HSIRDY_Msk   (0x1U << RCC_CR_HSIRDY_Pos)
 
#define RCC_CR_HSIRDY   RCC_CR_HSIRDY_Msk
 
#define RCC_CR_MSION_Pos   (8U)
 
#define RCC_CR_MSION_Msk   (0x1U << RCC_CR_MSION_Pos)
 
#define RCC_CR_MSION   RCC_CR_MSION_Msk
 
#define RCC_CR_MSIRDY_Pos   (9U)
 
#define RCC_CR_MSIRDY_Msk   (0x1U << RCC_CR_MSIRDY_Pos)
 
#define RCC_CR_MSIRDY   RCC_CR_MSIRDY_Msk
 
#define RCC_CR_HSEON_Pos   (16U)
 
#define RCC_CR_HSEON_Msk   (0x1U << RCC_CR_HSEON_Pos)
 
#define RCC_CR_HSEON   RCC_CR_HSEON_Msk
 
#define RCC_CR_HSERDY_Pos   (17U)
 
#define RCC_CR_HSERDY_Msk   (0x1U << RCC_CR_HSERDY_Pos)
 
#define RCC_CR_HSERDY   RCC_CR_HSERDY_Msk
 
#define RCC_CR_HSEBYP_Pos   (18U)
 
#define RCC_CR_HSEBYP_Msk   (0x1U << RCC_CR_HSEBYP_Pos)
 
#define RCC_CR_HSEBYP   RCC_CR_HSEBYP_Msk
 
#define RCC_CR_PLLON_Pos   (24U)
 
#define RCC_CR_PLLON_Msk   (0x1U << RCC_CR_PLLON_Pos)
 
#define RCC_CR_PLLON   RCC_CR_PLLON_Msk
 
#define RCC_CR_PLLRDY_Pos   (25U)
 
#define RCC_CR_PLLRDY_Msk   (0x1U << RCC_CR_PLLRDY_Pos)
 
#define RCC_CR_PLLRDY   RCC_CR_PLLRDY_Msk
 
#define RCC_CR_CSSON_Pos   (28U)
 
#define RCC_CR_CSSON_Msk   (0x1U << RCC_CR_CSSON_Pos)
 
#define RCC_CR_CSSON   RCC_CR_CSSON_Msk
 
#define RCC_CR_RTCPRE_Pos   (29U)
 
#define RCC_CR_RTCPRE_Msk   (0x3U << RCC_CR_RTCPRE_Pos)
 
#define RCC_CR_RTCPRE   RCC_CR_RTCPRE_Msk
 
#define RCC_CR_RTCPRE_0   (0x20000000U)
 
#define RCC_CR_RTCPRE_1   (0x40000000U)
 
#define RCC_ICSCR_HSICAL_Pos   (0U)
 
#define RCC_ICSCR_HSICAL_Msk   (0xFFU << RCC_ICSCR_HSICAL_Pos)
 
#define RCC_ICSCR_HSICAL   RCC_ICSCR_HSICAL_Msk
 
#define RCC_ICSCR_HSITRIM_Pos   (8U)
 
#define RCC_ICSCR_HSITRIM_Msk   (0x1FU << RCC_ICSCR_HSITRIM_Pos)
 
#define RCC_ICSCR_HSITRIM   RCC_ICSCR_HSITRIM_Msk
 
#define RCC_ICSCR_MSIRANGE_Pos   (13U)
 
#define RCC_ICSCR_MSIRANGE_Msk   (0x7U << RCC_ICSCR_MSIRANGE_Pos)
 
#define RCC_ICSCR_MSIRANGE   RCC_ICSCR_MSIRANGE_Msk
 
#define RCC_ICSCR_MSIRANGE_0   (0x0U << RCC_ICSCR_MSIRANGE_Pos)
 
#define RCC_ICSCR_MSIRANGE_1   (0x1U << RCC_ICSCR_MSIRANGE_Pos)
 
#define RCC_ICSCR_MSIRANGE_2   (0x2U << RCC_ICSCR_MSIRANGE_Pos)
 
#define RCC_ICSCR_MSIRANGE_3   (0x3U << RCC_ICSCR_MSIRANGE_Pos)
 
#define RCC_ICSCR_MSIRANGE_4   (0x4U << RCC_ICSCR_MSIRANGE_Pos)
 
#define RCC_ICSCR_MSIRANGE_5   (0x5U << RCC_ICSCR_MSIRANGE_Pos)
 
#define RCC_ICSCR_MSIRANGE_6   (0x6U << RCC_ICSCR_MSIRANGE_Pos)
 
#define RCC_ICSCR_MSICAL_Pos   (16U)
 
#define RCC_ICSCR_MSICAL_Msk   (0xFFU << RCC_ICSCR_MSICAL_Pos)
 
#define RCC_ICSCR_MSICAL   RCC_ICSCR_MSICAL_Msk
 
#define RCC_ICSCR_MSITRIM_Pos   (24U)
 
#define RCC_ICSCR_MSITRIM_Msk   (0xFFU << RCC_ICSCR_MSITRIM_Pos)
 
#define RCC_ICSCR_MSITRIM   RCC_ICSCR_MSITRIM_Msk
 
#define RCC_CFGR_SW_Pos   (0U)
 
#define RCC_CFGR_SW_Msk   (0x3U << RCC_CFGR_SW_Pos)
 
#define RCC_CFGR_SW   RCC_CFGR_SW_Msk
 
#define RCC_CFGR_SW_0   (0x1U << RCC_CFGR_SW_Pos)
 
#define RCC_CFGR_SW_1   (0x2U << RCC_CFGR_SW_Pos)
 
#define RCC_CFGR_SW_MSI   (0x00000000U)
 
#define RCC_CFGR_SW_HSI   (0x00000001U)
 
#define RCC_CFGR_SW_HSE   (0x00000002U)
 
#define RCC_CFGR_SW_PLL   (0x00000003U)
 
#define RCC_CFGR_SWS_Pos   (2U)
 
#define RCC_CFGR_SWS_Msk   (0x3U << RCC_CFGR_SWS_Pos)
 
#define RCC_CFGR_SWS   RCC_CFGR_SWS_Msk
 
#define RCC_CFGR_SWS_0   (0x1U << RCC_CFGR_SWS_Pos)
 
#define RCC_CFGR_SWS_1   (0x2U << RCC_CFGR_SWS_Pos)
 
#define RCC_CFGR_SWS_MSI   (0x00000000U)
 
#define RCC_CFGR_SWS_HSI   (0x00000004U)
 
#define RCC_CFGR_SWS_HSE   (0x00000008U)
 
#define RCC_CFGR_SWS_PLL   (0x0000000CU)
 
#define RCC_CFGR_HPRE_Pos   (4U)
 
#define RCC_CFGR_HPRE_Msk   (0xFU << RCC_CFGR_HPRE_Pos)
 
#define RCC_CFGR_HPRE   RCC_CFGR_HPRE_Msk
 
#define RCC_CFGR_HPRE_0   (0x1U << RCC_CFGR_HPRE_Pos)
 
#define RCC_CFGR_HPRE_1   (0x2U << RCC_CFGR_HPRE_Pos)
 
#define RCC_CFGR_HPRE_2   (0x4U << RCC_CFGR_HPRE_Pos)
 
#define RCC_CFGR_HPRE_3   (0x8U << RCC_CFGR_HPRE_Pos)
 
#define RCC_CFGR_HPRE_DIV1   (0x00000000U)
 
#define RCC_CFGR_HPRE_DIV2   (0x00000080U)
 
#define RCC_CFGR_HPRE_DIV4   (0x00000090U)
 
#define RCC_CFGR_HPRE_DIV8   (0x000000A0U)
 
#define RCC_CFGR_HPRE_DIV16   (0x000000B0U)
 
#define RCC_CFGR_HPRE_DIV64   (0x000000C0U)
 
#define RCC_CFGR_HPRE_DIV128   (0x000000D0U)
 
#define RCC_CFGR_HPRE_DIV256   (0x000000E0U)
 
#define RCC_CFGR_HPRE_DIV512   (0x000000F0U)
 
#define RCC_CFGR_PPRE1_Pos   (8U)
 
#define RCC_CFGR_PPRE1_Msk   (0x7U << RCC_CFGR_PPRE1_Pos)
 
#define RCC_CFGR_PPRE1   RCC_CFGR_PPRE1_Msk
 
#define RCC_CFGR_PPRE1_0   (0x1U << RCC_CFGR_PPRE1_Pos)
 
#define RCC_CFGR_PPRE1_1   (0x2U << RCC_CFGR_PPRE1_Pos)
 
#define RCC_CFGR_PPRE1_2   (0x4U << RCC_CFGR_PPRE1_Pos)
 
#define RCC_CFGR_PPRE1_DIV1   (0x00000000U)
 
#define RCC_CFGR_PPRE1_DIV2   (0x00000400U)
 
#define RCC_CFGR_PPRE1_DIV4   (0x00000500U)
 
#define RCC_CFGR_PPRE1_DIV8   (0x00000600U)
 
#define RCC_CFGR_PPRE1_DIV16   (0x00000700U)
 
#define RCC_CFGR_PPRE2_Pos   (11U)
 
#define RCC_CFGR_PPRE2_Msk   (0x7U << RCC_CFGR_PPRE2_Pos)
 
#define RCC_CFGR_PPRE2   RCC_CFGR_PPRE2_Msk
 
#define RCC_CFGR_PPRE2_0   (0x1U << RCC_CFGR_PPRE2_Pos)
 
#define RCC_CFGR_PPRE2_1   (0x2U << RCC_CFGR_PPRE2_Pos)
 
#define RCC_CFGR_PPRE2_2   (0x4U << RCC_CFGR_PPRE2_Pos)
 
#define RCC_CFGR_PPRE2_DIV1   (0x00000000U)
 
#define RCC_CFGR_PPRE2_DIV2   (0x00002000U)
 
#define RCC_CFGR_PPRE2_DIV4   (0x00002800U)
 
#define RCC_CFGR_PPRE2_DIV8   (0x00003000U)
 
#define RCC_CFGR_PPRE2_DIV16   (0x00003800U)
 
#define RCC_CFGR_PLLSRC_Pos   (16U)
 
#define RCC_CFGR_PLLSRC_Msk   (0x1U << RCC_CFGR_PLLSRC_Pos)
 
#define RCC_CFGR_PLLSRC   RCC_CFGR_PLLSRC_Msk
 
#define RCC_CFGR_PLLSRC_HSI   (0x00000000U)
 
#define RCC_CFGR_PLLSRC_HSE   (0x00010000U)
 
#define RCC_CFGR_PLLMUL_Pos   (18U)
 
#define RCC_CFGR_PLLMUL_Msk   (0xFU << RCC_CFGR_PLLMUL_Pos)
 
#define RCC_CFGR_PLLMUL   RCC_CFGR_PLLMUL_Msk
 
#define RCC_CFGR_PLLMUL_0   (0x1U << RCC_CFGR_PLLMUL_Pos)
 
#define RCC_CFGR_PLLMUL_1   (0x2U << RCC_CFGR_PLLMUL_Pos)
 
#define RCC_CFGR_PLLMUL_2   (0x4U << RCC_CFGR_PLLMUL_Pos)
 
#define RCC_CFGR_PLLMUL_3   (0x8U << RCC_CFGR_PLLMUL_Pos)
 
#define RCC_CFGR_PLLMUL3   (0x00000000U)
 
#define RCC_CFGR_PLLMUL4   (0x00040000U)
 
#define RCC_CFGR_PLLMUL6   (0x00080000U)
 
#define RCC_CFGR_PLLMUL8   (0x000C0000U)
 
#define RCC_CFGR_PLLMUL12   (0x00100000U)
 
#define RCC_CFGR_PLLMUL16   (0x00140000U)
 
#define RCC_CFGR_PLLMUL24   (0x00180000U)
 
#define RCC_CFGR_PLLMUL32   (0x001C0000U)
 
#define RCC_CFGR_PLLMUL48   (0x00200000U)
 
#define RCC_CFGR_PLLDIV_Pos   (22U)
 
#define RCC_CFGR_PLLDIV_Msk   (0x3U << RCC_CFGR_PLLDIV_Pos)
 
#define RCC_CFGR_PLLDIV   RCC_CFGR_PLLDIV_Msk
 
#define RCC_CFGR_PLLDIV_0   (0x1U << RCC_CFGR_PLLDIV_Pos)
 
#define RCC_CFGR_PLLDIV_1   (0x2U << RCC_CFGR_PLLDIV_Pos)
 
#define RCC_CFGR_PLLDIV1   (0x00000000U)
 
#define RCC_CFGR_PLLDIV2_Pos   (22U)
 
#define RCC_CFGR_PLLDIV2_Msk   (0x1U << RCC_CFGR_PLLDIV2_Pos)
 
#define RCC_CFGR_PLLDIV2   RCC_CFGR_PLLDIV2_Msk
 
#define RCC_CFGR_PLLDIV3_Pos   (23U)
 
#define RCC_CFGR_PLLDIV3_Msk   (0x1U << RCC_CFGR_PLLDIV3_Pos)
 
#define RCC_CFGR_PLLDIV3   RCC_CFGR_PLLDIV3_Msk
 
#define RCC_CFGR_PLLDIV4_Pos   (22U)
 
#define RCC_CFGR_PLLDIV4_Msk   (0x3U << RCC_CFGR_PLLDIV4_Pos)
 
#define RCC_CFGR_PLLDIV4   RCC_CFGR_PLLDIV4_Msk
 
#define RCC_CFGR_MCOSEL_Pos   (24U)
 
#define RCC_CFGR_MCOSEL_Msk   (0x7U << RCC_CFGR_MCOSEL_Pos)
 
#define RCC_CFGR_MCOSEL   RCC_CFGR_MCOSEL_Msk
 
#define RCC_CFGR_MCOSEL_0   (0x1U << RCC_CFGR_MCOSEL_Pos)
 
#define RCC_CFGR_MCOSEL_1   (0x2U << RCC_CFGR_MCOSEL_Pos)
 
#define RCC_CFGR_MCOSEL_2   (0x4U << RCC_CFGR_MCOSEL_Pos)
 
#define RCC_CFGR_MCOSEL_NOCLOCK   (0x00000000U)
 
#define RCC_CFGR_MCOSEL_SYSCLK_Pos   (24U)
 
#define RCC_CFGR_MCOSEL_SYSCLK_Msk   (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos)
 
#define RCC_CFGR_MCOSEL_SYSCLK   RCC_CFGR_MCOSEL_SYSCLK_Msk
 
#define RCC_CFGR_MCOSEL_HSI_Pos   (25U)
 
#define RCC_CFGR_MCOSEL_HSI_Msk   (0x1U << RCC_CFGR_MCOSEL_HSI_Pos)
 
#define RCC_CFGR_MCOSEL_HSI   RCC_CFGR_MCOSEL_HSI_Msk
 
#define RCC_CFGR_MCOSEL_MSI_Pos   (24U)
 
#define RCC_CFGR_MCOSEL_MSI_Msk   (0x3U << RCC_CFGR_MCOSEL_MSI_Pos)
 
#define RCC_CFGR_MCOSEL_MSI   RCC_CFGR_MCOSEL_MSI_Msk
 
#define RCC_CFGR_MCOSEL_HSE_Pos   (26U)
 
#define RCC_CFGR_MCOSEL_HSE_Msk   (0x1U << RCC_CFGR_MCOSEL_HSE_Pos)
 
#define RCC_CFGR_MCOSEL_HSE   RCC_CFGR_MCOSEL_HSE_Msk
 
#define RCC_CFGR_MCOSEL_PLL_Pos   (24U)
 
#define RCC_CFGR_MCOSEL_PLL_Msk   (0x5U << RCC_CFGR_MCOSEL_PLL_Pos)
 
#define RCC_CFGR_MCOSEL_PLL   RCC_CFGR_MCOSEL_PLL_Msk
 
#define RCC_CFGR_MCOSEL_LSI_Pos   (25U)
 
#define RCC_CFGR_MCOSEL_LSI_Msk   (0x3U << RCC_CFGR_MCOSEL_LSI_Pos)
 
#define RCC_CFGR_MCOSEL_LSI   RCC_CFGR_MCOSEL_LSI_Msk
 
#define RCC_CFGR_MCOSEL_LSE_Pos   (24U)
 
#define RCC_CFGR_MCOSEL_LSE_Msk   (0x7U << RCC_CFGR_MCOSEL_LSE_Pos)
 
#define RCC_CFGR_MCOSEL_LSE   RCC_CFGR_MCOSEL_LSE_Msk
 
#define RCC_CFGR_MCOPRE_Pos   (28U)
 
#define RCC_CFGR_MCOPRE_Msk   (0x7U << RCC_CFGR_MCOPRE_Pos)
 
#define RCC_CFGR_MCOPRE   RCC_CFGR_MCOPRE_Msk
 
#define RCC_CFGR_MCOPRE_0   (0x1U << RCC_CFGR_MCOPRE_Pos)
 
#define RCC_CFGR_MCOPRE_1   (0x2U << RCC_CFGR_MCOPRE_Pos)
 
#define RCC_CFGR_MCOPRE_2   (0x4U << RCC_CFGR_MCOPRE_Pos)
 
#define RCC_CFGR_MCOPRE_DIV1   (0x00000000U)
 
#define RCC_CFGR_MCOPRE_DIV2   (0x10000000U)
 
#define RCC_CFGR_MCOPRE_DIV4   (0x20000000U)
 
#define RCC_CFGR_MCOPRE_DIV8   (0x30000000U)
 
#define RCC_CFGR_MCOPRE_DIV16   (0x40000000U)
 
#define RCC_CFGR_MCO_DIV1   RCC_CFGR_MCOPRE_DIV1
 
#define RCC_CFGR_MCO_DIV2   RCC_CFGR_MCOPRE_DIV2
 
#define RCC_CFGR_MCO_DIV4   RCC_CFGR_MCOPRE_DIV4
 
#define RCC_CFGR_MCO_DIV8   RCC_CFGR_MCOPRE_DIV8
 
#define RCC_CFGR_MCO_DIV16   RCC_CFGR_MCOPRE_DIV16
 
#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK
 
#define RCC_CFGR_MCO_SYSCLK   RCC_CFGR_MCOSEL_SYSCLK
 
#define RCC_CFGR_MCO_HSI   RCC_CFGR_MCOSEL_HSI
 
#define RCC_CFGR_MCO_MSI   RCC_CFGR_MCOSEL_MSI
 
#define RCC_CFGR_MCO_HSE   RCC_CFGR_MCOSEL_HSE
 
#define RCC_CFGR_MCO_PLL   RCC_CFGR_MCOSEL_PLL
 
#define RCC_CFGR_MCO_LSI   RCC_CFGR_MCOSEL_LSI
 
#define RCC_CFGR_MCO_LSE   RCC_CFGR_MCOSEL_LSE
 
#define RCC_CIR_LSIRDYF_Pos   (0U)
 
#define RCC_CIR_LSIRDYF_Msk   (0x1U << RCC_CIR_LSIRDYF_Pos)
 
#define RCC_CIR_LSIRDYF   RCC_CIR_LSIRDYF_Msk
 
#define RCC_CIR_LSERDYF_Pos   (1U)
 
#define RCC_CIR_LSERDYF_Msk   (0x1U << RCC_CIR_LSERDYF_Pos)
 
#define RCC_CIR_LSERDYF   RCC_CIR_LSERDYF_Msk
 
#define RCC_CIR_HSIRDYF_Pos   (2U)
 
#define RCC_CIR_HSIRDYF_Msk   (0x1U << RCC_CIR_HSIRDYF_Pos)
 
#define RCC_CIR_HSIRDYF   RCC_CIR_HSIRDYF_Msk
 
#define RCC_CIR_HSERDYF_Pos   (3U)
 
#define RCC_CIR_HSERDYF_Msk   (0x1U << RCC_CIR_HSERDYF_Pos)
 
#define RCC_CIR_HSERDYF   RCC_CIR_HSERDYF_Msk
 
#define RCC_CIR_PLLRDYF_Pos   (4U)
 
#define RCC_CIR_PLLRDYF_Msk   (0x1U << RCC_CIR_PLLRDYF_Pos)
 
#define RCC_CIR_PLLRDYF   RCC_CIR_PLLRDYF_Msk
 
#define RCC_CIR_MSIRDYF_Pos   (5U)
 
#define RCC_CIR_MSIRDYF_Msk   (0x1U << RCC_CIR_MSIRDYF_Pos)
 
#define RCC_CIR_MSIRDYF   RCC_CIR_MSIRDYF_Msk
 
#define RCC_CIR_LSECSSF_Pos   (6U)
 
#define RCC_CIR_LSECSSF_Msk   (0x1U << RCC_CIR_LSECSSF_Pos)
 
#define RCC_CIR_LSECSSF   RCC_CIR_LSECSSF_Msk
 
#define RCC_CIR_CSSF_Pos   (7U)
 
#define RCC_CIR_CSSF_Msk   (0x1U << RCC_CIR_CSSF_Pos)
 
#define RCC_CIR_CSSF   RCC_CIR_CSSF_Msk
 
#define RCC_CIR_LSIRDYIE_Pos   (8U)
 
#define RCC_CIR_LSIRDYIE_Msk   (0x1U << RCC_CIR_LSIRDYIE_Pos)
 
#define RCC_CIR_LSIRDYIE   RCC_CIR_LSIRDYIE_Msk
 
#define RCC_CIR_LSERDYIE_Pos   (9U)
 
#define RCC_CIR_LSERDYIE_Msk   (0x1U << RCC_CIR_LSERDYIE_Pos)
 
#define RCC_CIR_LSERDYIE   RCC_CIR_LSERDYIE_Msk
 
#define RCC_CIR_HSIRDYIE_Pos   (10U)
 
#define RCC_CIR_HSIRDYIE_Msk   (0x1U << RCC_CIR_HSIRDYIE_Pos)
 
#define RCC_CIR_HSIRDYIE   RCC_CIR_HSIRDYIE_Msk
 
#define RCC_CIR_HSERDYIE_Pos   (11U)
 
#define RCC_CIR_HSERDYIE_Msk   (0x1U << RCC_CIR_HSERDYIE_Pos)
 
#define RCC_CIR_HSERDYIE   RCC_CIR_HSERDYIE_Msk
 
#define RCC_CIR_PLLRDYIE_Pos   (12U)
 
#define RCC_CIR_PLLRDYIE_Msk   (0x1U << RCC_CIR_PLLRDYIE_Pos)
 
#define RCC_CIR_PLLRDYIE   RCC_CIR_PLLRDYIE_Msk
 
#define RCC_CIR_MSIRDYIE_Pos   (13U)
 
#define RCC_CIR_MSIRDYIE_Msk   (0x1U << RCC_CIR_MSIRDYIE_Pos)
 
#define RCC_CIR_MSIRDYIE   RCC_CIR_MSIRDYIE_Msk
 
#define RCC_CIR_LSECSSIE_Pos   (14U)
 
#define RCC_CIR_LSECSSIE_Msk   (0x1U << RCC_CIR_LSECSSIE_Pos)
 
#define RCC_CIR_LSECSSIE   RCC_CIR_LSECSSIE_Msk
 
#define RCC_CIR_LSIRDYC_Pos   (16U)
 
#define RCC_CIR_LSIRDYC_Msk   (0x1U << RCC_CIR_LSIRDYC_Pos)
 
#define RCC_CIR_LSIRDYC   RCC_CIR_LSIRDYC_Msk
 
#define RCC_CIR_LSERDYC_Pos   (17U)
 
#define RCC_CIR_LSERDYC_Msk   (0x1U << RCC_CIR_LSERDYC_Pos)
 
#define RCC_CIR_LSERDYC   RCC_CIR_LSERDYC_Msk
 
#define RCC_CIR_HSIRDYC_Pos   (18U)
 
#define RCC_CIR_HSIRDYC_Msk   (0x1U << RCC_CIR_HSIRDYC_Pos)
 
#define RCC_CIR_HSIRDYC   RCC_CIR_HSIRDYC_Msk
 
#define RCC_CIR_HSERDYC_Pos   (19U)
 
#define RCC_CIR_HSERDYC_Msk   (0x1U << RCC_CIR_HSERDYC_Pos)
 
#define RCC_CIR_HSERDYC   RCC_CIR_HSERDYC_Msk
 
#define RCC_CIR_PLLRDYC_Pos   (20U)
 
#define RCC_CIR_PLLRDYC_Msk   (0x1U << RCC_CIR_PLLRDYC_Pos)
 
#define RCC_CIR_PLLRDYC   RCC_CIR_PLLRDYC_Msk
 
#define RCC_CIR_MSIRDYC_Pos   (21U)
 
#define RCC_CIR_MSIRDYC_Msk   (0x1U << RCC_CIR_MSIRDYC_Pos)
 
#define RCC_CIR_MSIRDYC   RCC_CIR_MSIRDYC_Msk
 
#define RCC_CIR_LSECSSC_Pos   (22U)
 
#define RCC_CIR_LSECSSC_Msk   (0x1U << RCC_CIR_LSECSSC_Pos)
 
#define RCC_CIR_LSECSSC   RCC_CIR_LSECSSC_Msk
 
#define RCC_CIR_CSSC_Pos   (23U)
 
#define RCC_CIR_CSSC_Msk   (0x1U << RCC_CIR_CSSC_Pos)
 
#define RCC_CIR_CSSC   RCC_CIR_CSSC_Msk
 
#define RCC_AHBRSTR_GPIOARST_Pos   (0U)
 
#define RCC_AHBRSTR_GPIOARST_Msk   (0x1U << RCC_AHBRSTR_GPIOARST_Pos)
 
#define RCC_AHBRSTR_GPIOARST   RCC_AHBRSTR_GPIOARST_Msk
 
#define RCC_AHBRSTR_GPIOBRST_Pos   (1U)
 
#define RCC_AHBRSTR_GPIOBRST_Msk   (0x1U << RCC_AHBRSTR_GPIOBRST_Pos)
 
#define RCC_AHBRSTR_GPIOBRST   RCC_AHBRSTR_GPIOBRST_Msk
 
#define RCC_AHBRSTR_GPIOCRST_Pos   (2U)
 
#define RCC_AHBRSTR_GPIOCRST_Msk   (0x1U << RCC_AHBRSTR_GPIOCRST_Pos)
 
#define RCC_AHBRSTR_GPIOCRST   RCC_AHBRSTR_GPIOCRST_Msk
 
#define RCC_AHBRSTR_GPIODRST_Pos   (3U)
 
#define RCC_AHBRSTR_GPIODRST_Msk   (0x1U << RCC_AHBRSTR_GPIODRST_Pos)
 
#define RCC_AHBRSTR_GPIODRST   RCC_AHBRSTR_GPIODRST_Msk
 
#define RCC_AHBRSTR_GPIOERST_Pos   (4U)
 
#define RCC_AHBRSTR_GPIOERST_Msk   (0x1U << RCC_AHBRSTR_GPIOERST_Pos)
 
#define RCC_AHBRSTR_GPIOERST   RCC_AHBRSTR_GPIOERST_Msk
 
#define RCC_AHBRSTR_GPIOHRST_Pos   (5U)
 
#define RCC_AHBRSTR_GPIOHRST_Msk   (0x1U << RCC_AHBRSTR_GPIOHRST_Pos)
 
#define RCC_AHBRSTR_GPIOHRST   RCC_AHBRSTR_GPIOHRST_Msk
 
#define RCC_AHBRSTR_GPIOFRST_Pos   (6U)
 
#define RCC_AHBRSTR_GPIOFRST_Msk   (0x1U << RCC_AHBRSTR_GPIOFRST_Pos)
 
#define RCC_AHBRSTR_GPIOFRST   RCC_AHBRSTR_GPIOFRST_Msk
 
#define RCC_AHBRSTR_GPIOGRST_Pos   (7U)
 
#define RCC_AHBRSTR_GPIOGRST_Msk   (0x1U << RCC_AHBRSTR_GPIOGRST_Pos)
 
#define RCC_AHBRSTR_GPIOGRST   RCC_AHBRSTR_GPIOGRST_Msk
 
#define RCC_AHBRSTR_CRCRST_Pos   (12U)
 
#define RCC_AHBRSTR_CRCRST_Msk   (0x1U << RCC_AHBRSTR_CRCRST_Pos)
 
#define RCC_AHBRSTR_CRCRST   RCC_AHBRSTR_CRCRST_Msk
 
#define RCC_AHBRSTR_FLITFRST_Pos   (15U)
 
#define RCC_AHBRSTR_FLITFRST_Msk   (0x1U << RCC_AHBRSTR_FLITFRST_Pos)
 
#define RCC_AHBRSTR_FLITFRST   RCC_AHBRSTR_FLITFRST_Msk
 
#define RCC_AHBRSTR_DMA1RST_Pos   (24U)
 
#define RCC_AHBRSTR_DMA1RST_Msk   (0x1U << RCC_AHBRSTR_DMA1RST_Pos)
 
#define RCC_AHBRSTR_DMA1RST   RCC_AHBRSTR_DMA1RST_Msk
 
#define RCC_AHBRSTR_DMA2RST_Pos   (25U)
 
#define RCC_AHBRSTR_DMA2RST_Msk   (0x1U << RCC_AHBRSTR_DMA2RST_Pos)
 
#define RCC_AHBRSTR_DMA2RST   RCC_AHBRSTR_DMA2RST_Msk
 
#define RCC_APB2RSTR_SYSCFGRST_Pos   (0U)
 
#define RCC_APB2RSTR_SYSCFGRST_Msk   (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos)
 
#define RCC_APB2RSTR_SYSCFGRST   RCC_APB2RSTR_SYSCFGRST_Msk
 
#define RCC_APB2RSTR_TIM9RST_Pos   (2U)
 
#define RCC_APB2RSTR_TIM9RST_Msk   (0x1U << RCC_APB2RSTR_TIM9RST_Pos)
 
#define RCC_APB2RSTR_TIM9RST   RCC_APB2RSTR_TIM9RST_Msk
 
#define RCC_APB2RSTR_TIM10RST_Pos   (3U)
 
#define RCC_APB2RSTR_TIM10RST_Msk   (0x1U << RCC_APB2RSTR_TIM10RST_Pos)
 
#define RCC_APB2RSTR_TIM10RST   RCC_APB2RSTR_TIM10RST_Msk
 
#define RCC_APB2RSTR_TIM11RST_Pos   (4U)
 
#define RCC_APB2RSTR_TIM11RST_Msk   (0x1U << RCC_APB2RSTR_TIM11RST_Pos)
 
#define RCC_APB2RSTR_TIM11RST   RCC_APB2RSTR_TIM11RST_Msk
 
#define RCC_APB2RSTR_ADC1RST_Pos   (9U)
 
#define RCC_APB2RSTR_ADC1RST_Msk   (0x1U << RCC_APB2RSTR_ADC1RST_Pos)
 
#define RCC_APB2RSTR_ADC1RST   RCC_APB2RSTR_ADC1RST_Msk
 
#define RCC_APB2RSTR_SPI1RST_Pos   (12U)
 
#define RCC_APB2RSTR_SPI1RST_Msk   (0x1U << RCC_APB2RSTR_SPI1RST_Pos)
 
#define RCC_APB2RSTR_SPI1RST   RCC_APB2RSTR_SPI1RST_Msk
 
#define RCC_APB2RSTR_USART1RST_Pos   (14U)
 
#define RCC_APB2RSTR_USART1RST_Msk   (0x1U << RCC_APB2RSTR_USART1RST_Pos)
 
#define RCC_APB2RSTR_USART1RST   RCC_APB2RSTR_USART1RST_Msk
 
#define RCC_APB1RSTR_TIM2RST_Pos   (0U)
 
#define RCC_APB1RSTR_TIM2RST_Msk   (0x1U << RCC_APB1RSTR_TIM2RST_Pos)
 
#define RCC_APB1RSTR_TIM2RST   RCC_APB1RSTR_TIM2RST_Msk
 
#define RCC_APB1RSTR_TIM3RST_Pos   (1U)
 
#define RCC_APB1RSTR_TIM3RST_Msk   (0x1U << RCC_APB1RSTR_TIM3RST_Pos)
 
#define RCC_APB1RSTR_TIM3RST   RCC_APB1RSTR_TIM3RST_Msk
 
#define RCC_APB1RSTR_TIM4RST_Pos   (2U)
 
#define RCC_APB1RSTR_TIM4RST_Msk   (0x1U << RCC_APB1RSTR_TIM4RST_Pos)
 
#define RCC_APB1RSTR_TIM4RST   RCC_APB1RSTR_TIM4RST_Msk
 
#define RCC_APB1RSTR_TIM5RST_Pos   (3U)
 
#define RCC_APB1RSTR_TIM5RST_Msk   (0x1U << RCC_APB1RSTR_TIM5RST_Pos)
 
#define RCC_APB1RSTR_TIM5RST   RCC_APB1RSTR_TIM5RST_Msk
 
#define RCC_APB1RSTR_TIM6RST_Pos   (4U)
 
#define RCC_APB1RSTR_TIM6RST_Msk   (0x1U << RCC_APB1RSTR_TIM6RST_Pos)
 
#define RCC_APB1RSTR_TIM6RST   RCC_APB1RSTR_TIM6RST_Msk
 
#define RCC_APB1RSTR_TIM7RST_Pos   (5U)
 
#define RCC_APB1RSTR_TIM7RST_Msk   (0x1U << RCC_APB1RSTR_TIM7RST_Pos)
 
#define RCC_APB1RSTR_TIM7RST   RCC_APB1RSTR_TIM7RST_Msk
 
#define RCC_APB1RSTR_LCDRST_Pos   (9U)
 
#define RCC_APB1RSTR_LCDRST_Msk   (0x1U << RCC_APB1RSTR_LCDRST_Pos)
 
#define RCC_APB1RSTR_LCDRST   RCC_APB1RSTR_LCDRST_Msk
 
#define RCC_APB1RSTR_WWDGRST_Pos   (11U)
 
#define RCC_APB1RSTR_WWDGRST_Msk   (0x1U << RCC_APB1RSTR_WWDGRST_Pos)
 
#define RCC_APB1RSTR_WWDGRST   RCC_APB1RSTR_WWDGRST_Msk
 
#define RCC_APB1RSTR_SPI2RST_Pos   (14U)
 
#define RCC_APB1RSTR_SPI2RST_Msk   (0x1U << RCC_APB1RSTR_SPI2RST_Pos)
 
#define RCC_APB1RSTR_SPI2RST   RCC_APB1RSTR_SPI2RST_Msk
 
#define RCC_APB1RSTR_SPI3RST_Pos   (15U)
 
#define RCC_APB1RSTR_SPI3RST_Msk   (0x1U << RCC_APB1RSTR_SPI3RST_Pos)
 
#define RCC_APB1RSTR_SPI3RST   RCC_APB1RSTR_SPI3RST_Msk
 
#define RCC_APB1RSTR_USART2RST_Pos   (17U)
 
#define RCC_APB1RSTR_USART2RST_Msk   (0x1U << RCC_APB1RSTR_USART2RST_Pos)
 
#define RCC_APB1RSTR_USART2RST   RCC_APB1RSTR_USART2RST_Msk
 
#define RCC_APB1RSTR_USART3RST_Pos   (18U)
 
#define RCC_APB1RSTR_USART3RST_Msk   (0x1U << RCC_APB1RSTR_USART3RST_Pos)
 
#define RCC_APB1RSTR_USART3RST   RCC_APB1RSTR_USART3RST_Msk
 
#define RCC_APB1RSTR_UART4RST_Pos   (19U)
 
#define RCC_APB1RSTR_UART4RST_Msk   (0x1U << RCC_APB1RSTR_UART4RST_Pos)
 
#define RCC_APB1RSTR_UART4RST   RCC_APB1RSTR_UART4RST_Msk
 
#define RCC_APB1RSTR_UART5RST_Pos   (20U)
 
#define RCC_APB1RSTR_UART5RST_Msk   (0x1U << RCC_APB1RSTR_UART5RST_Pos)
 
#define RCC_APB1RSTR_UART5RST   RCC_APB1RSTR_UART5RST_Msk
 
#define RCC_APB1RSTR_I2C1RST_Pos   (21U)
 
#define RCC_APB1RSTR_I2C1RST_Msk   (0x1U << RCC_APB1RSTR_I2C1RST_Pos)
 
#define RCC_APB1RSTR_I2C1RST   RCC_APB1RSTR_I2C1RST_Msk
 
#define RCC_APB1RSTR_I2C2RST_Pos   (22U)
 
#define RCC_APB1RSTR_I2C2RST_Msk   (0x1U << RCC_APB1RSTR_I2C2RST_Pos)
 
#define RCC_APB1RSTR_I2C2RST   RCC_APB1RSTR_I2C2RST_Msk
 
#define RCC_APB1RSTR_USBRST_Pos   (23U)
 
#define RCC_APB1RSTR_USBRST_Msk   (0x1U << RCC_APB1RSTR_USBRST_Pos)
 
#define RCC_APB1RSTR_USBRST   RCC_APB1RSTR_USBRST_Msk
 
#define RCC_APB1RSTR_PWRRST_Pos   (28U)
 
#define RCC_APB1RSTR_PWRRST_Msk   (0x1U << RCC_APB1RSTR_PWRRST_Pos)
 
#define RCC_APB1RSTR_PWRRST   RCC_APB1RSTR_PWRRST_Msk
 
#define RCC_APB1RSTR_DACRST_Pos   (29U)
 
#define RCC_APB1RSTR_DACRST_Msk   (0x1U << RCC_APB1RSTR_DACRST_Pos)
 
#define RCC_APB1RSTR_DACRST   RCC_APB1RSTR_DACRST_Msk
 
#define RCC_APB1RSTR_COMPRST_Pos   (31U)
 
#define RCC_APB1RSTR_COMPRST_Msk   (0x1U << RCC_APB1RSTR_COMPRST_Pos)
 
#define RCC_APB1RSTR_COMPRST   RCC_APB1RSTR_COMPRST_Msk
 
#define RCC_AHBENR_GPIOAEN_Pos   (0U)
 
#define RCC_AHBENR_GPIOAEN_Msk   (0x1U << RCC_AHBENR_GPIOAEN_Pos)
 
#define RCC_AHBENR_GPIOAEN   RCC_AHBENR_GPIOAEN_Msk
 
#define RCC_AHBENR_GPIOBEN_Pos   (1U)
 
#define RCC_AHBENR_GPIOBEN_Msk   (0x1U << RCC_AHBENR_GPIOBEN_Pos)
 
#define RCC_AHBENR_GPIOBEN   RCC_AHBENR_GPIOBEN_Msk
 
#define RCC_AHBENR_GPIOCEN_Pos   (2U)
 
#define RCC_AHBENR_GPIOCEN_Msk   (0x1U << RCC_AHBENR_GPIOCEN_Pos)
 
#define RCC_AHBENR_GPIOCEN   RCC_AHBENR_GPIOCEN_Msk
 
#define RCC_AHBENR_GPIODEN_Pos   (3U)
 
#define RCC_AHBENR_GPIODEN_Msk   (0x1U << RCC_AHBENR_GPIODEN_Pos)
 
#define RCC_AHBENR_GPIODEN   RCC_AHBENR_GPIODEN_Msk
 
#define RCC_AHBENR_GPIOEEN_Pos   (4U)
 
#define RCC_AHBENR_GPIOEEN_Msk   (0x1U << RCC_AHBENR_GPIOEEN_Pos)
 
#define RCC_AHBENR_GPIOEEN   RCC_AHBENR_GPIOEEN_Msk
 
#define RCC_AHBENR_GPIOHEN_Pos   (5U)
 
#define RCC_AHBENR_GPIOHEN_Msk   (0x1U << RCC_AHBENR_GPIOHEN_Pos)
 
#define RCC_AHBENR_GPIOHEN   RCC_AHBENR_GPIOHEN_Msk
 
#define RCC_AHBENR_GPIOFEN_Pos   (6U)
 
#define RCC_AHBENR_GPIOFEN_Msk   (0x1U << RCC_AHBENR_GPIOFEN_Pos)
 
#define RCC_AHBENR_GPIOFEN   RCC_AHBENR_GPIOFEN_Msk
 
#define RCC_AHBENR_GPIOGEN_Pos   (7U)
 
#define RCC_AHBENR_GPIOGEN_Msk   (0x1U << RCC_AHBENR_GPIOGEN_Pos)
 
#define RCC_AHBENR_GPIOGEN   RCC_AHBENR_GPIOGEN_Msk
 
#define RCC_AHBENR_CRCEN_Pos   (12U)
 
#define RCC_AHBENR_CRCEN_Msk   (0x1U << RCC_AHBENR_CRCEN_Pos)
 
#define RCC_AHBENR_CRCEN   RCC_AHBENR_CRCEN_Msk
 
#define RCC_AHBENR_FLITFEN_Pos   (15U)
 
#define RCC_AHBENR_FLITFEN_Msk   (0x1U << RCC_AHBENR_FLITFEN_Pos)
 
#define RCC_AHBENR_FLITFEN   RCC_AHBENR_FLITFEN_Msk
 
#define RCC_AHBENR_DMA1EN_Pos   (24U)
 
#define RCC_AHBENR_DMA1EN_Msk   (0x1U << RCC_AHBENR_DMA1EN_Pos)
 
#define RCC_AHBENR_DMA1EN   RCC_AHBENR_DMA1EN_Msk
 
#define RCC_AHBENR_DMA2EN_Pos   (25U)
 
#define RCC_AHBENR_DMA2EN_Msk   (0x1U << RCC_AHBENR_DMA2EN_Pos)
 
#define RCC_AHBENR_DMA2EN   RCC_AHBENR_DMA2EN_Msk
 
#define RCC_APB2ENR_SYSCFGEN_Pos   (0U)
 
#define RCC_APB2ENR_SYSCFGEN_Msk   (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)
 
#define RCC_APB2ENR_SYSCFGEN   RCC_APB2ENR_SYSCFGEN_Msk
 
#define RCC_APB2ENR_TIM9EN_Pos   (2U)
 
#define RCC_APB2ENR_TIM9EN_Msk   (0x1U << RCC_APB2ENR_TIM9EN_Pos)
 
#define RCC_APB2ENR_TIM9EN   RCC_APB2ENR_TIM9EN_Msk
 
#define RCC_APB2ENR_TIM10EN_Pos   (3U)
 
#define RCC_APB2ENR_TIM10EN_Msk   (0x1U << RCC_APB2ENR_TIM10EN_Pos)
 
#define RCC_APB2ENR_TIM10EN   RCC_APB2ENR_TIM10EN_Msk
 
#define RCC_APB2ENR_TIM11EN_Pos   (4U)
 
#define RCC_APB2ENR_TIM11EN_Msk   (0x1U << RCC_APB2ENR_TIM11EN_Pos)
 
#define RCC_APB2ENR_TIM11EN   RCC_APB2ENR_TIM11EN_Msk
 
#define RCC_APB2ENR_ADC1EN_Pos   (9U)
 
#define RCC_APB2ENR_ADC1EN_Msk   (0x1U << RCC_APB2ENR_ADC1EN_Pos)
 
#define RCC_APB2ENR_ADC1EN   RCC_APB2ENR_ADC1EN_Msk
 
#define RCC_APB2ENR_SPI1EN_Pos   (12U)
 
#define RCC_APB2ENR_SPI1EN_Msk   (0x1U << RCC_APB2ENR_SPI1EN_Pos)
 
#define RCC_APB2ENR_SPI1EN   RCC_APB2ENR_SPI1EN_Msk
 
#define RCC_APB2ENR_USART1EN_Pos   (14U)
 
#define RCC_APB2ENR_USART1EN_Msk   (0x1U << RCC_APB2ENR_USART1EN_Pos)
 
#define RCC_APB2ENR_USART1EN   RCC_APB2ENR_USART1EN_Msk
 
#define RCC_APB1ENR_TIM2EN_Pos   (0U)
 
#define RCC_APB1ENR_TIM2EN_Msk   (0x1U << RCC_APB1ENR_TIM2EN_Pos)
 
#define RCC_APB1ENR_TIM2EN   RCC_APB1ENR_TIM2EN_Msk
 
#define RCC_APB1ENR_TIM3EN_Pos   (1U)
 
#define RCC_APB1ENR_TIM3EN_Msk   (0x1U << RCC_APB1ENR_TIM3EN_Pos)
 
#define RCC_APB1ENR_TIM3EN   RCC_APB1ENR_TIM3EN_Msk
 
#define RCC_APB1ENR_TIM4EN_Pos   (2U)
 
#define RCC_APB1ENR_TIM4EN_Msk   (0x1U << RCC_APB1ENR_TIM4EN_Pos)
 
#define RCC_APB1ENR_TIM4EN   RCC_APB1ENR_TIM4EN_Msk
 
#define RCC_APB1ENR_TIM5EN_Pos   (3U)
 
#define RCC_APB1ENR_TIM5EN_Msk   (0x1U << RCC_APB1ENR_TIM5EN_Pos)
 
#define RCC_APB1ENR_TIM5EN   RCC_APB1ENR_TIM5EN_Msk
 
#define RCC_APB1ENR_TIM6EN_Pos   (4U)
 
#define RCC_APB1ENR_TIM6EN_Msk   (0x1U << RCC_APB1ENR_TIM6EN_Pos)
 
#define RCC_APB1ENR_TIM6EN   RCC_APB1ENR_TIM6EN_Msk
 
#define RCC_APB1ENR_TIM7EN_Pos   (5U)
 
#define RCC_APB1ENR_TIM7EN_Msk   (0x1U << RCC_APB1ENR_TIM7EN_Pos)
 
#define RCC_APB1ENR_TIM7EN   RCC_APB1ENR_TIM7EN_Msk
 
#define RCC_APB1ENR_LCDEN_Pos   (9U)
 
#define RCC_APB1ENR_LCDEN_Msk   (0x1U << RCC_APB1ENR_LCDEN_Pos)
 
#define RCC_APB1ENR_LCDEN   RCC_APB1ENR_LCDEN_Msk
 
#define RCC_APB1ENR_WWDGEN_Pos   (11U)
 
#define RCC_APB1ENR_WWDGEN_Msk   (0x1U << RCC_APB1ENR_WWDGEN_Pos)
 
#define RCC_APB1ENR_WWDGEN   RCC_APB1ENR_WWDGEN_Msk
 
#define RCC_APB1ENR_SPI2EN_Pos   (14U)
 
#define RCC_APB1ENR_SPI2EN_Msk   (0x1U << RCC_APB1ENR_SPI2EN_Pos)
 
#define RCC_APB1ENR_SPI2EN   RCC_APB1ENR_SPI2EN_Msk
 
#define RCC_APB1ENR_SPI3EN_Pos   (15U)
 
#define RCC_APB1ENR_SPI3EN_Msk   (0x1U << RCC_APB1ENR_SPI3EN_Pos)
 
#define RCC_APB1ENR_SPI3EN   RCC_APB1ENR_SPI3EN_Msk
 
#define RCC_APB1ENR_USART2EN_Pos   (17U)
 
#define RCC_APB1ENR_USART2EN_Msk   (0x1U << RCC_APB1ENR_USART2EN_Pos)
 
#define RCC_APB1ENR_USART2EN   RCC_APB1ENR_USART2EN_Msk
 
#define RCC_APB1ENR_USART3EN_Pos   (18U)
 
#define RCC_APB1ENR_USART3EN_Msk   (0x1U << RCC_APB1ENR_USART3EN_Pos)
 
#define RCC_APB1ENR_USART3EN   RCC_APB1ENR_USART3EN_Msk
 
#define RCC_APB1ENR_UART4EN_Pos   (19U)
 
#define RCC_APB1ENR_UART4EN_Msk   (0x1U << RCC_APB1ENR_UART4EN_Pos)
 
#define RCC_APB1ENR_UART4EN   RCC_APB1ENR_UART4EN_Msk
 
#define RCC_APB1ENR_UART5EN_Pos   (20U)
 
#define RCC_APB1ENR_UART5EN_Msk   (0x1U << RCC_APB1ENR_UART5EN_Pos)
 
#define RCC_APB1ENR_UART5EN   RCC_APB1ENR_UART5EN_Msk
 
#define RCC_APB1ENR_I2C1EN_Pos   (21U)
 
#define RCC_APB1ENR_I2C1EN_Msk   (0x1U << RCC_APB1ENR_I2C1EN_Pos)
 
#define RCC_APB1ENR_I2C1EN   RCC_APB1ENR_I2C1EN_Msk
 
#define RCC_APB1ENR_I2C2EN_Pos   (22U)
 
#define RCC_APB1ENR_I2C2EN_Msk   (0x1U << RCC_APB1ENR_I2C2EN_Pos)
 
#define RCC_APB1ENR_I2C2EN   RCC_APB1ENR_I2C2EN_Msk
 
#define RCC_APB1ENR_USBEN_Pos   (23U)
 
#define RCC_APB1ENR_USBEN_Msk   (0x1U << RCC_APB1ENR_USBEN_Pos)
 
#define RCC_APB1ENR_USBEN   RCC_APB1ENR_USBEN_Msk
 
#define RCC_APB1ENR_PWREN_Pos   (28U)
 
#define RCC_APB1ENR_PWREN_Msk   (0x1U << RCC_APB1ENR_PWREN_Pos)
 
#define RCC_APB1ENR_PWREN   RCC_APB1ENR_PWREN_Msk
 
#define RCC_APB1ENR_DACEN_Pos   (29U)
 
#define RCC_APB1ENR_DACEN_Msk   (0x1U << RCC_APB1ENR_DACEN_Pos)
 
#define RCC_APB1ENR_DACEN   RCC_APB1ENR_DACEN_Msk
 
#define RCC_APB1ENR_COMPEN_Pos   (31U)
 
#define RCC_APB1ENR_COMPEN_Msk   (0x1U << RCC_APB1ENR_COMPEN_Pos)
 
#define RCC_APB1ENR_COMPEN   RCC_APB1ENR_COMPEN_Msk
 
#define RCC_AHBLPENR_GPIOALPEN_Pos   (0U)
 
#define RCC_AHBLPENR_GPIOALPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos)
 
#define RCC_AHBLPENR_GPIOALPEN   RCC_AHBLPENR_GPIOALPEN_Msk
 
#define RCC_AHBLPENR_GPIOBLPEN_Pos   (1U)
 
#define RCC_AHBLPENR_GPIOBLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos)
 
#define RCC_AHBLPENR_GPIOBLPEN   RCC_AHBLPENR_GPIOBLPEN_Msk
 
#define RCC_AHBLPENR_GPIOCLPEN_Pos   (2U)
 
#define RCC_AHBLPENR_GPIOCLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos)
 
#define RCC_AHBLPENR_GPIOCLPEN   RCC_AHBLPENR_GPIOCLPEN_Msk
 
#define RCC_AHBLPENR_GPIODLPEN_Pos   (3U)
 
#define RCC_AHBLPENR_GPIODLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos)
 
#define RCC_AHBLPENR_GPIODLPEN   RCC_AHBLPENR_GPIODLPEN_Msk
 
#define RCC_AHBLPENR_GPIOELPEN_Pos   (4U)
 
#define RCC_AHBLPENR_GPIOELPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos)
 
#define RCC_AHBLPENR_GPIOELPEN   RCC_AHBLPENR_GPIOELPEN_Msk
 
#define RCC_AHBLPENR_GPIOHLPEN_Pos   (5U)
 
#define RCC_AHBLPENR_GPIOHLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos)
 
#define RCC_AHBLPENR_GPIOHLPEN   RCC_AHBLPENR_GPIOHLPEN_Msk
 
#define RCC_AHBLPENR_GPIOFLPEN_Pos   (6U)
 
#define RCC_AHBLPENR_GPIOFLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOFLPEN_Pos)
 
#define RCC_AHBLPENR_GPIOFLPEN   RCC_AHBLPENR_GPIOFLPEN_Msk
 
#define RCC_AHBLPENR_GPIOGLPEN_Pos   (7U)
 
#define RCC_AHBLPENR_GPIOGLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOGLPEN_Pos)
 
#define RCC_AHBLPENR_GPIOGLPEN   RCC_AHBLPENR_GPIOGLPEN_Msk
 
#define RCC_AHBLPENR_CRCLPEN_Pos   (12U)
 
#define RCC_AHBLPENR_CRCLPEN_Msk   (0x1U << RCC_AHBLPENR_CRCLPEN_Pos)
 
#define RCC_AHBLPENR_CRCLPEN   RCC_AHBLPENR_CRCLPEN_Msk
 
#define RCC_AHBLPENR_FLITFLPEN_Pos   (15U)
 
#define RCC_AHBLPENR_FLITFLPEN_Msk   (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos)
 
#define RCC_AHBLPENR_FLITFLPEN   RCC_AHBLPENR_FLITFLPEN_Msk
 
#define RCC_AHBLPENR_SRAMLPEN_Pos   (16U)
 
#define RCC_AHBLPENR_SRAMLPEN_Msk   (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos)
 
#define RCC_AHBLPENR_SRAMLPEN   RCC_AHBLPENR_SRAMLPEN_Msk
 
#define RCC_AHBLPENR_DMA1LPEN_Pos   (24U)
 
#define RCC_AHBLPENR_DMA1LPEN_Msk   (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos)
 
#define RCC_AHBLPENR_DMA1LPEN   RCC_AHBLPENR_DMA1LPEN_Msk
 
#define RCC_AHBLPENR_DMA2LPEN_Pos   (25U)
 
#define RCC_AHBLPENR_DMA2LPEN_Msk   (0x1U << RCC_AHBLPENR_DMA2LPEN_Pos)
 
#define RCC_AHBLPENR_DMA2LPEN   RCC_AHBLPENR_DMA2LPEN_Msk
 
#define RCC_APB2LPENR_SYSCFGLPEN_Pos   (0U)
 
#define RCC_APB2LPENR_SYSCFGLPEN_Msk   (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos)
 
#define RCC_APB2LPENR_SYSCFGLPEN   RCC_APB2LPENR_SYSCFGLPEN_Msk
 
#define RCC_APB2LPENR_TIM9LPEN_Pos   (2U)
 
#define RCC_APB2LPENR_TIM9LPEN_Msk   (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos)
 
#define RCC_APB2LPENR_TIM9LPEN   RCC_APB2LPENR_TIM9LPEN_Msk
 
#define RCC_APB2LPENR_TIM10LPEN_Pos   (3U)
 
#define RCC_APB2LPENR_TIM10LPEN_Msk   (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos)
 
#define RCC_APB2LPENR_TIM10LPEN   RCC_APB2LPENR_TIM10LPEN_Msk
 
#define RCC_APB2LPENR_TIM11LPEN_Pos   (4U)
 
#define RCC_APB2LPENR_TIM11LPEN_Msk   (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos)
 
#define RCC_APB2LPENR_TIM11LPEN   RCC_APB2LPENR_TIM11LPEN_Msk
 
#define RCC_APB2LPENR_ADC1LPEN_Pos   (9U)
 
#define RCC_APB2LPENR_ADC1LPEN_Msk   (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos)
 
#define RCC_APB2LPENR_ADC1LPEN   RCC_APB2LPENR_ADC1LPEN_Msk
 
#define RCC_APB2LPENR_SPI1LPEN_Pos   (12U)
 
#define RCC_APB2LPENR_SPI1LPEN_Msk   (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos)
 
#define RCC_APB2LPENR_SPI1LPEN   RCC_APB2LPENR_SPI1LPEN_Msk
 
#define RCC_APB2LPENR_USART1LPEN_Pos   (14U)
 
#define RCC_APB2LPENR_USART1LPEN_Msk   (0x1U << RCC_APB2LPENR_USART1LPEN_Pos)
 
#define RCC_APB2LPENR_USART1LPEN   RCC_APB2LPENR_USART1LPEN_Msk
 
#define RCC_APB1LPENR_TIM2LPEN_Pos   (0U)
 
#define RCC_APB1LPENR_TIM2LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos)
 
#define RCC_APB1LPENR_TIM2LPEN   RCC_APB1LPENR_TIM2LPEN_Msk
 
#define RCC_APB1LPENR_TIM3LPEN_Pos   (1U)
 
#define RCC_APB1LPENR_TIM3LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos)
 
#define RCC_APB1LPENR_TIM3LPEN   RCC_APB1LPENR_TIM3LPEN_Msk
 
#define RCC_APB1LPENR_TIM4LPEN_Pos   (2U)
 
#define RCC_APB1LPENR_TIM4LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos)
 
#define RCC_APB1LPENR_TIM4LPEN   RCC_APB1LPENR_TIM4LPEN_Msk
 
#define RCC_APB1LPENR_TIM5LPEN_Pos   (3U)
 
#define RCC_APB1LPENR_TIM5LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos)
 
#define RCC_APB1LPENR_TIM5LPEN   RCC_APB1LPENR_TIM5LPEN_Msk
 
#define RCC_APB1LPENR_TIM6LPEN_Pos   (4U)
 
#define RCC_APB1LPENR_TIM6LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos)
 
#define RCC_APB1LPENR_TIM6LPEN   RCC_APB1LPENR_TIM6LPEN_Msk
 
#define RCC_APB1LPENR_TIM7LPEN_Pos   (5U)
 
#define RCC_APB1LPENR_TIM7LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos)
 
#define RCC_APB1LPENR_TIM7LPEN   RCC_APB1LPENR_TIM7LPEN_Msk
 
#define RCC_APB1LPENR_LCDLPEN_Pos   (9U)
 
#define RCC_APB1LPENR_LCDLPEN_Msk   (0x1U << RCC_APB1LPENR_LCDLPEN_Pos)
 
#define RCC_APB1LPENR_LCDLPEN   RCC_APB1LPENR_LCDLPEN_Msk
 
#define RCC_APB1LPENR_WWDGLPEN_Pos   (11U)
 
#define RCC_APB1LPENR_WWDGLPEN_Msk   (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos)
 
#define RCC_APB1LPENR_WWDGLPEN   RCC_APB1LPENR_WWDGLPEN_Msk
 
#define RCC_APB1LPENR_SPI2LPEN_Pos   (14U)
 
#define RCC_APB1LPENR_SPI2LPEN_Msk   (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos)
 
#define RCC_APB1LPENR_SPI2LPEN   RCC_APB1LPENR_SPI2LPEN_Msk
 
#define RCC_APB1LPENR_SPI3LPEN_Pos   (15U)
 
#define RCC_APB1LPENR_SPI3LPEN_Msk   (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos)
 
#define RCC_APB1LPENR_SPI3LPEN   RCC_APB1LPENR_SPI3LPEN_Msk
 
#define RCC_APB1LPENR_USART2LPEN_Pos   (17U)
 
#define RCC_APB1LPENR_USART2LPEN_Msk   (0x1U << RCC_APB1LPENR_USART2LPEN_Pos)
 
#define RCC_APB1LPENR_USART2LPEN   RCC_APB1LPENR_USART2LPEN_Msk
 
#define RCC_APB1LPENR_USART3LPEN_Pos   (18U)
 
#define RCC_APB1LPENR_USART3LPEN_Msk   (0x1U << RCC_APB1LPENR_USART3LPEN_Pos)
 
#define RCC_APB1LPENR_USART3LPEN   RCC_APB1LPENR_USART3LPEN_Msk
 
#define RCC_APB1LPENR_UART4LPEN_Pos   (19U)
 
#define RCC_APB1LPENR_UART4LPEN_Msk   (0x1U << RCC_APB1LPENR_UART4LPEN_Pos)
 
#define RCC_APB1LPENR_UART4LPEN   RCC_APB1LPENR_UART4LPEN_Msk
 
#define RCC_APB1LPENR_UART5LPEN_Pos   (20U)
 
#define RCC_APB1LPENR_UART5LPEN_Msk   (0x1U << RCC_APB1LPENR_UART5LPEN_Pos)
 
#define RCC_APB1LPENR_UART5LPEN   RCC_APB1LPENR_UART5LPEN_Msk
 
#define RCC_APB1LPENR_I2C1LPEN_Pos   (21U)
 
#define RCC_APB1LPENR_I2C1LPEN_Msk   (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos)
 
#define RCC_APB1LPENR_I2C1LPEN   RCC_APB1LPENR_I2C1LPEN_Msk
 
#define RCC_APB1LPENR_I2C2LPEN_Pos   (22U)
 
#define RCC_APB1LPENR_I2C2LPEN_Msk   (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos)
 
#define RCC_APB1LPENR_I2C2LPEN   RCC_APB1LPENR_I2C2LPEN_Msk
 
#define RCC_APB1LPENR_USBLPEN_Pos   (23U)
 
#define RCC_APB1LPENR_USBLPEN_Msk   (0x1U << RCC_APB1LPENR_USBLPEN_Pos)
 
#define RCC_APB1LPENR_USBLPEN   RCC_APB1LPENR_USBLPEN_Msk
 
#define RCC_APB1LPENR_PWRLPEN_Pos   (28U)
 
#define RCC_APB1LPENR_PWRLPEN_Msk   (0x1U << RCC_APB1LPENR_PWRLPEN_Pos)
 
#define RCC_APB1LPENR_PWRLPEN   RCC_APB1LPENR_PWRLPEN_Msk
 
#define RCC_APB1LPENR_DACLPEN_Pos   (29U)
 
#define RCC_APB1LPENR_DACLPEN_Msk   (0x1U << RCC_APB1LPENR_DACLPEN_Pos)
 
#define RCC_APB1LPENR_DACLPEN   RCC_APB1LPENR_DACLPEN_Msk
 
#define RCC_APB1LPENR_COMPLPEN_Pos   (31U)
 
#define RCC_APB1LPENR_COMPLPEN_Msk   (0x1U << RCC_APB1LPENR_COMPLPEN_Pos)
 
#define RCC_APB1LPENR_COMPLPEN   RCC_APB1LPENR_COMPLPEN_Msk
 
#define RCC_CSR_LSION_Pos   (0U)
 
#define RCC_CSR_LSION_Msk   (0x1U << RCC_CSR_LSION_Pos)
 
#define RCC_CSR_LSION   RCC_CSR_LSION_Msk
 
#define RCC_CSR_LSIRDY_Pos   (1U)
 
#define RCC_CSR_LSIRDY_Msk   (0x1U << RCC_CSR_LSIRDY_Pos)
 
#define RCC_CSR_LSIRDY   RCC_CSR_LSIRDY_Msk
 
#define RCC_CSR_LSEON_Pos   (8U)
 
#define RCC_CSR_LSEON_Msk   (0x1U << RCC_CSR_LSEON_Pos)
 
#define RCC_CSR_LSEON   RCC_CSR_LSEON_Msk
 
#define RCC_CSR_LSERDY_Pos   (9U)
 
#define RCC_CSR_LSERDY_Msk   (0x1U << RCC_CSR_LSERDY_Pos)
 
#define RCC_CSR_LSERDY   RCC_CSR_LSERDY_Msk
 
#define RCC_CSR_LSEBYP_Pos   (10U)
 
#define RCC_CSR_LSEBYP_Msk   (0x1U << RCC_CSR_LSEBYP_Pos)
 
#define RCC_CSR_LSEBYP   RCC_CSR_LSEBYP_Msk
 
#define RCC_CSR_LSECSSON_Pos   (11U)
 
#define RCC_CSR_LSECSSON_Msk   (0x1U << RCC_CSR_LSECSSON_Pos)
 
#define RCC_CSR_LSECSSON   RCC_CSR_LSECSSON_Msk
 
#define RCC_CSR_LSECSSD_Pos   (12U)
 
#define RCC_CSR_LSECSSD_Msk   (0x1U << RCC_CSR_LSECSSD_Pos)
 
#define RCC_CSR_LSECSSD   RCC_CSR_LSECSSD_Msk
 
#define RCC_CSR_RTCSEL_Pos   (16U)
 
#define RCC_CSR_RTCSEL_Msk   (0x3U << RCC_CSR_RTCSEL_Pos)
 
#define RCC_CSR_RTCSEL   RCC_CSR_RTCSEL_Msk
 
#define RCC_CSR_RTCSEL_0   (0x1U << RCC_CSR_RTCSEL_Pos)
 
#define RCC_CSR_RTCSEL_1   (0x2U << RCC_CSR_RTCSEL_Pos)
 
#define RCC_CSR_RTCSEL_NOCLOCK   (0x00000000U)
 
#define RCC_CSR_RTCSEL_LSE_Pos   (16U)
 
#define RCC_CSR_RTCSEL_LSE_Msk   (0x1U << RCC_CSR_RTCSEL_LSE_Pos)
 
#define RCC_CSR_RTCSEL_LSE   RCC_CSR_RTCSEL_LSE_Msk
 
#define RCC_CSR_RTCSEL_LSI_Pos   (17U)
 
#define RCC_CSR_RTCSEL_LSI_Msk   (0x1U << RCC_CSR_RTCSEL_LSI_Pos)
 
#define RCC_CSR_RTCSEL_LSI   RCC_CSR_RTCSEL_LSI_Msk
 
#define RCC_CSR_RTCSEL_HSE_Pos   (16U)
 
#define RCC_CSR_RTCSEL_HSE_Msk   (0x3U << RCC_CSR_RTCSEL_HSE_Pos)
 
#define RCC_CSR_RTCSEL_HSE   RCC_CSR_RTCSEL_HSE_Msk
 
#define RCC_CSR_RTCEN_Pos   (22U)
 
#define RCC_CSR_RTCEN_Msk   (0x1U << RCC_CSR_RTCEN_Pos)
 
#define RCC_CSR_RTCEN   RCC_CSR_RTCEN_Msk
 
#define RCC_CSR_RTCRST_Pos   (23U)
 
#define RCC_CSR_RTCRST_Msk   (0x1U << RCC_CSR_RTCRST_Pos)
 
#define RCC_CSR_RTCRST   RCC_CSR_RTCRST_Msk
 
#define RCC_CSR_RMVF_Pos   (24U)
 
#define RCC_CSR_RMVF_Msk   (0x1U << RCC_CSR_RMVF_Pos)
 
#define RCC_CSR_RMVF   RCC_CSR_RMVF_Msk
 
#define RCC_CSR_OBLRSTF_Pos   (25U)
 
#define RCC_CSR_OBLRSTF_Msk   (0x1U << RCC_CSR_OBLRSTF_Pos)
 
#define RCC_CSR_OBLRSTF   RCC_CSR_OBLRSTF_Msk
 
#define RCC_CSR_PINRSTF_Pos   (26U)
 
#define RCC_CSR_PINRSTF_Msk   (0x1U << RCC_CSR_PINRSTF_Pos)
 
#define RCC_CSR_PINRSTF   RCC_CSR_PINRSTF_Msk
 
#define RCC_CSR_PORRSTF_Pos   (27U)
 
#define RCC_CSR_PORRSTF_Msk   (0x1U << RCC_CSR_PORRSTF_Pos)
 
#define RCC_CSR_PORRSTF   RCC_CSR_PORRSTF_Msk
 
#define RCC_CSR_SFTRSTF_Pos   (28U)
 
#define RCC_CSR_SFTRSTF_Msk   (0x1U << RCC_CSR_SFTRSTF_Pos)
 
#define RCC_CSR_SFTRSTF   RCC_CSR_SFTRSTF_Msk
 
#define RCC_CSR_IWDGRSTF_Pos   (29U)
 
#define RCC_CSR_IWDGRSTF_Msk   (0x1U << RCC_CSR_IWDGRSTF_Pos)
 
#define RCC_CSR_IWDGRSTF   RCC_CSR_IWDGRSTF_Msk
 
#define RCC_CSR_WWDGRSTF_Pos   (30U)
 
#define RCC_CSR_WWDGRSTF_Msk   (0x1U << RCC_CSR_WWDGRSTF_Pos)
 
#define RCC_CSR_WWDGRSTF   RCC_CSR_WWDGRSTF_Msk
 
#define RCC_CSR_LPWRRSTF_Pos   (31U)
 
#define RCC_CSR_LPWRRSTF_Msk   (0x1U << RCC_CSR_LPWRRSTF_Pos)
 
#define RCC_CSR_LPWRRSTF   RCC_CSR_LPWRRSTF_Msk
 
#define RTC_TAMPER1_SUPPORT
 
#define RTC_TAMPER2_SUPPORT
 
#define RTC_TAMPER3_SUPPORT
 
#define RTC_BACKUP_SUPPORT
 
#define RTC_WAKEUP_SUPPORT
 
#define RTC_SMOOTHCALIB_SUPPORT
 
#define RTC_SUBSECOND_SUPPORT
 
#define RTC_TR_PM_Pos   (22U)
 
#define RTC_TR_PM_Msk   (0x1U << RTC_TR_PM_Pos)
 
#define RTC_TR_PM   RTC_TR_PM_Msk
 
#define RTC_TR_HT_Pos   (20U)
 
#define RTC_TR_HT_Msk   (0x3U << RTC_TR_HT_Pos)
 
#define RTC_TR_HT   RTC_TR_HT_Msk
 
#define RTC_TR_HT_0   (0x1U << RTC_TR_HT_Pos)
 
#define RTC_TR_HT_1   (0x2U << RTC_TR_HT_Pos)
 
#define RTC_TR_HU_Pos   (16U)
 
#define RTC_TR_HU_Msk   (0xFU << RTC_TR_HU_Pos)
 
#define RTC_TR_HU   RTC_TR_HU_Msk
 
#define RTC_TR_HU_0   (0x1U << RTC_TR_HU_Pos)
 
#define RTC_TR_HU_1   (0x2U << RTC_TR_HU_Pos)
 
#define RTC_TR_HU_2   (0x4U << RTC_TR_HU_Pos)
 
#define RTC_TR_HU_3   (0x8U << RTC_TR_HU_Pos)
 
#define RTC_TR_MNT_Pos   (12U)
 
#define RTC_TR_MNT_Msk   (0x7U << RTC_TR_MNT_Pos)
 
#define RTC_TR_MNT   RTC_TR_MNT_Msk
 
#define RTC_TR_MNT_0   (0x1U << RTC_TR_MNT_Pos)
 
#define RTC_TR_MNT_1   (0x2U << RTC_TR_MNT_Pos)
 
#define RTC_TR_MNT_2   (0x4U << RTC_TR_MNT_Pos)
 
#define RTC_TR_MNU_Pos   (8U)
 
#define RTC_TR_MNU_Msk   (0xFU << RTC_TR_MNU_Pos)
 
#define RTC_TR_MNU   RTC_TR_MNU_Msk
 
#define RTC_TR_MNU_0   (0x1U << RTC_TR_MNU_Pos)
 
#define RTC_TR_MNU_1   (0x2U << RTC_TR_MNU_Pos)
 
#define RTC_TR_MNU_2   (0x4U << RTC_TR_MNU_Pos)
 
#define RTC_TR_MNU_3   (0x8U << RTC_TR_MNU_Pos)
 
#define RTC_TR_ST_Pos   (4U)
 
#define RTC_TR_ST_Msk   (0x7U << RTC_TR_ST_Pos)
 
#define RTC_TR_ST   RTC_TR_ST_Msk
 
#define RTC_TR_ST_0   (0x1U << RTC_TR_ST_Pos)
 
#define RTC_TR_ST_1   (0x2U << RTC_TR_ST_Pos)
 
#define RTC_TR_ST_2   (0x4U << RTC_TR_ST_Pos)
 
#define RTC_TR_SU_Pos   (0U)
 
#define RTC_TR_SU_Msk   (0xFU << RTC_TR_SU_Pos)
 
#define RTC_TR_SU   RTC_TR_SU_Msk
 
#define RTC_TR_SU_0   (0x1U << RTC_TR_SU_Pos)
 
#define RTC_TR_SU_1   (0x2U << RTC_TR_SU_Pos)
 
#define RTC_TR_SU_2   (0x4U << RTC_TR_SU_Pos)
 
#define RTC_TR_SU_3   (0x8U << RTC_TR_SU_Pos)
 
#define RTC_DR_YT_Pos   (20U)
 
#define RTC_DR_YT_Msk   (0xFU << RTC_DR_YT_Pos)
 
#define RTC_DR_YT   RTC_DR_YT_Msk
 
#define RTC_DR_YT_0   (0x1U << RTC_DR_YT_Pos)
 
#define RTC_DR_YT_1   (0x2U << RTC_DR_YT_Pos)
 
#define RTC_DR_YT_2   (0x4U << RTC_DR_YT_Pos)
 
#define RTC_DR_YT_3   (0x8U << RTC_DR_YT_Pos)
 
#define RTC_DR_YU_Pos   (16U)
 
#define RTC_DR_YU_Msk   (0xFU << RTC_DR_YU_Pos)
 
#define RTC_DR_YU   RTC_DR_YU_Msk
 
#define RTC_DR_YU_0   (0x1U << RTC_DR_YU_Pos)
 
#define RTC_DR_YU_1   (0x2U << RTC_DR_YU_Pos)
 
#define RTC_DR_YU_2   (0x4U << RTC_DR_YU_Pos)
 
#define RTC_DR_YU_3   (0x8U << RTC_DR_YU_Pos)
 
#define RTC_DR_WDU_Pos   (13U)
 
#define RTC_DR_WDU_Msk   (0x7U << RTC_DR_WDU_Pos)
 
#define RTC_DR_WDU   RTC_DR_WDU_Msk
 
#define RTC_DR_WDU_0   (0x1U << RTC_DR_WDU_Pos)
 
#define RTC_DR_WDU_1   (0x2U << RTC_DR_WDU_Pos)
 
#define RTC_DR_WDU_2   (0x4U << RTC_DR_WDU_Pos)
 
#define RTC_DR_MT_Pos   (12U)
 
#define RTC_DR_MT_Msk   (0x1U << RTC_DR_MT_Pos)
 
#define RTC_DR_MT   RTC_DR_MT_Msk
 
#define RTC_DR_MU_Pos   (8U)
 
#define RTC_DR_MU_Msk   (0xFU << RTC_DR_MU_Pos)
 
#define RTC_DR_MU   RTC_DR_MU_Msk
 
#define RTC_DR_MU_0   (0x1U << RTC_DR_MU_Pos)
 
#define RTC_DR_MU_1   (0x2U << RTC_DR_MU_Pos)
 
#define RTC_DR_MU_2   (0x4U << RTC_DR_MU_Pos)
 
#define RTC_DR_MU_3   (0x8U << RTC_DR_MU_Pos)
 
#define RTC_DR_DT_Pos   (4U)
 
#define RTC_DR_DT_Msk   (0x3U << RTC_DR_DT_Pos)
 
#define RTC_DR_DT   RTC_DR_DT_Msk
 
#define RTC_DR_DT_0   (0x1U << RTC_DR_DT_Pos)
 
#define RTC_DR_DT_1   (0x2U << RTC_DR_DT_Pos)
 
#define RTC_DR_DU_Pos   (0U)
 
#define RTC_DR_DU_Msk   (0xFU << RTC_DR_DU_Pos)
 
#define RTC_DR_DU   RTC_DR_DU_Msk
 
#define RTC_DR_DU_0   (0x1U << RTC_DR_DU_Pos)
 
#define RTC_DR_DU_1   (0x2U << RTC_DR_DU_Pos)
 
#define RTC_DR_DU_2   (0x4U << RTC_DR_DU_Pos)
 
#define RTC_DR_DU_3   (0x8U << RTC_DR_DU_Pos)
 
#define RTC_CR_COE_Pos   (23U)
 
#define RTC_CR_COE_Msk   (0x1U << RTC_CR_COE_Pos)
 
#define RTC_CR_COE   RTC_CR_COE_Msk
 
#define RTC_CR_OSEL_Pos   (21U)
 
#define RTC_CR_OSEL_Msk   (0x3U << RTC_CR_OSEL_Pos)
 
#define RTC_CR_OSEL   RTC_CR_OSEL_Msk
 
#define RTC_CR_OSEL_0   (0x1U << RTC_CR_OSEL_Pos)
 
#define RTC_CR_OSEL_1   (0x2U << RTC_CR_OSEL_Pos)
 
#define RTC_CR_POL_Pos   (20U)
 
#define RTC_CR_POL_Msk   (0x1U << RTC_CR_POL_Pos)
 
#define RTC_CR_POL   RTC_CR_POL_Msk
 
#define RTC_CR_COSEL_Pos   (19U)
 
#define RTC_CR_COSEL_Msk   (0x1U << RTC_CR_COSEL_Pos)
 
#define RTC_CR_COSEL   RTC_CR_COSEL_Msk
 
#define RTC_CR_BKP_Pos   (18U)
 
#define RTC_CR_BKP_Msk   (0x1U << RTC_CR_BKP_Pos)
 
#define RTC_CR_BKP   RTC_CR_BKP_Msk
 
#define RTC_CR_SUB1H_Pos   (17U)
 
#define RTC_CR_SUB1H_Msk   (0x1U << RTC_CR_SUB1H_Pos)
 
#define RTC_CR_SUB1H   RTC_CR_SUB1H_Msk
 
#define RTC_CR_ADD1H_Pos   (16U)
 
#define RTC_CR_ADD1H_Msk   (0x1U << RTC_CR_ADD1H_Pos)
 
#define RTC_CR_ADD1H   RTC_CR_ADD1H_Msk
 
#define RTC_CR_TSIE_Pos   (15U)
 
#define RTC_CR_TSIE_Msk   (0x1U << RTC_CR_TSIE_Pos)
 
#define RTC_CR_TSIE   RTC_CR_TSIE_Msk
 
#define RTC_CR_WUTIE_Pos   (14U)
 
#define RTC_CR_WUTIE_Msk   (0x1U << RTC_CR_WUTIE_Pos)
 
#define RTC_CR_WUTIE   RTC_CR_WUTIE_Msk
 
#define RTC_CR_ALRBIE_Pos   (13U)
 
#define RTC_CR_ALRBIE_Msk   (0x1U << RTC_CR_ALRBIE_Pos)
 
#define RTC_CR_ALRBIE   RTC_CR_ALRBIE_Msk
 
#define RTC_CR_ALRAIE_Pos   (12U)
 
#define RTC_CR_ALRAIE_Msk   (0x1U << RTC_CR_ALRAIE_Pos)
 
#define RTC_CR_ALRAIE   RTC_CR_ALRAIE_Msk
 
#define RTC_CR_TSE_Pos   (11U)
 
#define RTC_CR_TSE_Msk   (0x1U << RTC_CR_TSE_Pos)
 
#define RTC_CR_TSE   RTC_CR_TSE_Msk
 
#define RTC_CR_WUTE_Pos   (10U)
 
#define RTC_CR_WUTE_Msk   (0x1U << RTC_CR_WUTE_Pos)
 
#define RTC_CR_WUTE   RTC_CR_WUTE_Msk
 
#define RTC_CR_ALRBE_Pos   (9U)
 
#define RTC_CR_ALRBE_Msk   (0x1U << RTC_CR_ALRBE_Pos)
 
#define RTC_CR_ALRBE   RTC_CR_ALRBE_Msk
 
#define RTC_CR_ALRAE_Pos   (8U)
 
#define RTC_CR_ALRAE_Msk   (0x1U << RTC_CR_ALRAE_Pos)
 
#define RTC_CR_ALRAE   RTC_CR_ALRAE_Msk
 
#define RTC_CR_DCE_Pos   (7U)
 
#define RTC_CR_DCE_Msk   (0x1U << RTC_CR_DCE_Pos)
 
#define RTC_CR_DCE   RTC_CR_DCE_Msk
 
#define RTC_CR_FMT_Pos   (6U)
 
#define RTC_CR_FMT_Msk   (0x1U << RTC_CR_FMT_Pos)
 
#define RTC_CR_FMT   RTC_CR_FMT_Msk
 
#define RTC_CR_BYPSHAD_Pos   (5U)
 
#define RTC_CR_BYPSHAD_Msk   (0x1U << RTC_CR_BYPSHAD_Pos)
 
#define RTC_CR_BYPSHAD   RTC_CR_BYPSHAD_Msk
 
#define RTC_CR_REFCKON_Pos   (4U)
 
#define RTC_CR_REFCKON_Msk   (0x1U << RTC_CR_REFCKON_Pos)
 
#define RTC_CR_REFCKON   RTC_CR_REFCKON_Msk
 
#define RTC_CR_TSEDGE_Pos   (3U)
 
#define RTC_CR_TSEDGE_Msk   (0x1U << RTC_CR_TSEDGE_Pos)
 
#define RTC_CR_TSEDGE   RTC_CR_TSEDGE_Msk
 
#define RTC_CR_WUCKSEL_Pos   (0U)
 
#define RTC_CR_WUCKSEL_Msk   (0x7U << RTC_CR_WUCKSEL_Pos)
 
#define RTC_CR_WUCKSEL   RTC_CR_WUCKSEL_Msk
 
#define RTC_CR_WUCKSEL_0   (0x1U << RTC_CR_WUCKSEL_Pos)
 
#define RTC_CR_WUCKSEL_1   (0x2U << RTC_CR_WUCKSEL_Pos)
 
#define RTC_CR_WUCKSEL_2   (0x4U << RTC_CR_WUCKSEL_Pos)
 
#define RTC_CR_BCK_Pos   RTC_CR_BKP_Pos
 
#define RTC_CR_BCK_Msk   RTC_CR_BKP_Msk
 
#define RTC_CR_BCK   RTC_CR_BKP
 
#define RTC_ISR_RECALPF_Pos   (16U)
 
#define RTC_ISR_RECALPF_Msk   (0x1U << RTC_ISR_RECALPF_Pos)
 
#define RTC_ISR_RECALPF   RTC_ISR_RECALPF_Msk
 
#define RTC_ISR_TAMP3F_Pos   (15U)
 
#define RTC_ISR_TAMP3F_Msk   (0x1U << RTC_ISR_TAMP3F_Pos)
 
#define RTC_ISR_TAMP3F   RTC_ISR_TAMP3F_Msk
 
#define RTC_ISR_TAMP2F_Pos   (14U)
 
#define RTC_ISR_TAMP2F_Msk   (0x1U << RTC_ISR_TAMP2F_Pos)
 
#define RTC_ISR_TAMP2F   RTC_ISR_TAMP2F_Msk
 
#define RTC_ISR_TAMP1F_Pos   (13U)
 
#define RTC_ISR_TAMP1F_Msk   (0x1U << RTC_ISR_TAMP1F_Pos)
 
#define RTC_ISR_TAMP1F   RTC_ISR_TAMP1F_Msk
 
#define RTC_ISR_TSOVF_Pos   (12U)
 
#define RTC_ISR_TSOVF_Msk   (0x1U << RTC_ISR_TSOVF_Pos)
 
#define RTC_ISR_TSOVF   RTC_ISR_TSOVF_Msk
 
#define RTC_ISR_TSF_Pos   (11U)
 
#define RTC_ISR_TSF_Msk   (0x1U << RTC_ISR_TSF_Pos)
 
#define RTC_ISR_TSF   RTC_ISR_TSF_Msk
 
#define RTC_ISR_WUTF_Pos   (10U)
 
#define RTC_ISR_WUTF_Msk   (0x1U << RTC_ISR_WUTF_Pos)
 
#define RTC_ISR_WUTF   RTC_ISR_WUTF_Msk
 
#define RTC_ISR_ALRBF_Pos   (9U)
 
#define RTC_ISR_ALRBF_Msk   (0x1U << RTC_ISR_ALRBF_Pos)
 
#define RTC_ISR_ALRBF   RTC_ISR_ALRBF_Msk
 
#define RTC_ISR_ALRAF_Pos   (8U)
 
#define RTC_ISR_ALRAF_Msk   (0x1U << RTC_ISR_ALRAF_Pos)
 
#define RTC_ISR_ALRAF   RTC_ISR_ALRAF_Msk
 
#define RTC_ISR_INIT_Pos   (7U)
 
#define RTC_ISR_INIT_Msk   (0x1U << RTC_ISR_INIT_Pos)
 
#define RTC_ISR_INIT   RTC_ISR_INIT_Msk
 
#define RTC_ISR_INITF_Pos   (6U)
 
#define RTC_ISR_INITF_Msk   (0x1U << RTC_ISR_INITF_Pos)
 
#define RTC_ISR_INITF   RTC_ISR_INITF_Msk
 
#define RTC_ISR_RSF_Pos   (5U)
 
#define RTC_ISR_RSF_Msk   (0x1U << RTC_ISR_RSF_Pos)
 
#define RTC_ISR_RSF   RTC_ISR_RSF_Msk
 
#define RTC_ISR_INITS_Pos   (4U)
 
#define RTC_ISR_INITS_Msk   (0x1U << RTC_ISR_INITS_Pos)
 
#define RTC_ISR_INITS   RTC_ISR_INITS_Msk
 
#define RTC_ISR_SHPF_Pos   (3U)
 
#define RTC_ISR_SHPF_Msk   (0x1U << RTC_ISR_SHPF_Pos)
 
#define RTC_ISR_SHPF   RTC_ISR_SHPF_Msk
 
#define RTC_ISR_WUTWF_Pos   (2U)
 
#define RTC_ISR_WUTWF_Msk   (0x1U << RTC_ISR_WUTWF_Pos)
 
#define RTC_ISR_WUTWF   RTC_ISR_WUTWF_Msk
 
#define RTC_ISR_ALRBWF_Pos   (1U)
 
#define RTC_ISR_ALRBWF_Msk   (0x1U << RTC_ISR_ALRBWF_Pos)
 
#define RTC_ISR_ALRBWF   RTC_ISR_ALRBWF_Msk
 
#define RTC_ISR_ALRAWF_Pos   (0U)
 
#define RTC_ISR_ALRAWF_Msk   (0x1U << RTC_ISR_ALRAWF_Pos)
 
#define RTC_ISR_ALRAWF   RTC_ISR_ALRAWF_Msk
 
#define RTC_PRER_PREDIV_A_Pos   (16U)
 
#define RTC_PRER_PREDIV_A_Msk   (0x7FU << RTC_PRER_PREDIV_A_Pos)
 
#define RTC_PRER_PREDIV_A   RTC_PRER_PREDIV_A_Msk
 
#define RTC_PRER_PREDIV_S_Pos   (0U)
 
#define RTC_PRER_PREDIV_S_Msk   (0x7FFFU << RTC_PRER_PREDIV_S_Pos)
 
#define RTC_PRER_PREDIV_S   RTC_PRER_PREDIV_S_Msk
 
#define RTC_WUTR_WUT_Pos   (0U)
 
#define RTC_WUTR_WUT_Msk   (0xFFFFU << RTC_WUTR_WUT_Pos)
 
#define RTC_WUTR_WUT   RTC_WUTR_WUT_Msk
 
#define RTC_CALIBR_DCS_Pos   (7U)
 
#define RTC_CALIBR_DCS_Msk   (0x1U << RTC_CALIBR_DCS_Pos)
 
#define RTC_CALIBR_DCS   RTC_CALIBR_DCS_Msk
 
#define RTC_CALIBR_DC_Pos   (0U)
 
#define RTC_CALIBR_DC_Msk   (0x1FU << RTC_CALIBR_DC_Pos)
 
#define RTC_CALIBR_DC   RTC_CALIBR_DC_Msk
 
#define RTC_ALRMAR_MSK4_Pos   (31U)
 
#define RTC_ALRMAR_MSK4_Msk   (0x1U << RTC_ALRMAR_MSK4_Pos)
 
#define RTC_ALRMAR_MSK4   RTC_ALRMAR_MSK4_Msk
 
#define RTC_ALRMAR_WDSEL_Pos   (30U)
 
#define RTC_ALRMAR_WDSEL_Msk   (0x1U << RTC_ALRMAR_WDSEL_Pos)
 
#define RTC_ALRMAR_WDSEL   RTC_ALRMAR_WDSEL_Msk
 
#define RTC_ALRMAR_DT_Pos   (28U)
 
#define RTC_ALRMAR_DT_Msk   (0x3U << RTC_ALRMAR_DT_Pos)
 
#define RTC_ALRMAR_DT   RTC_ALRMAR_DT_Msk
 
#define RTC_ALRMAR_DT_0   (0x1U << RTC_ALRMAR_DT_Pos)
 
#define RTC_ALRMAR_DT_1   (0x2U << RTC_ALRMAR_DT_Pos)
 
#define RTC_ALRMAR_DU_Pos   (24U)
 
#define RTC_ALRMAR_DU_Msk   (0xFU << RTC_ALRMAR_DU_Pos)
 
#define RTC_ALRMAR_DU   RTC_ALRMAR_DU_Msk
 
#define RTC_ALRMAR_DU_0   (0x1U << RTC_ALRMAR_DU_Pos)
 
#define RTC_ALRMAR_DU_1   (0x2U << RTC_ALRMAR_DU_Pos)
 
#define RTC_ALRMAR_DU_2   (0x4U << RTC_ALRMAR_DU_Pos)
 
#define RTC_ALRMAR_DU_3   (0x8U << RTC_ALRMAR_DU_Pos)
 
#define RTC_ALRMAR_MSK3_Pos   (23U)
 
#define RTC_ALRMAR_MSK3_Msk   (0x1U << RTC_ALRMAR_MSK3_Pos)
 
#define RTC_ALRMAR_MSK3   RTC_ALRMAR_MSK3_Msk
 
#define RTC_ALRMAR_PM_Pos   (22U)
 
#define RTC_ALRMAR_PM_Msk   (0x1U << RTC_ALRMAR_PM_Pos)
 
#define RTC_ALRMAR_PM   RTC_ALRMAR_PM_Msk
 
#define RTC_ALRMAR_HT_Pos   (20U)
 
#define RTC_ALRMAR_HT_Msk   (0x3U << RTC_ALRMAR_HT_Pos)
 
#define RTC_ALRMAR_HT   RTC_ALRMAR_HT_Msk
 
#define RTC_ALRMAR_HT_0   (0x1U << RTC_ALRMAR_HT_Pos)
 
#define RTC_ALRMAR_HT_1   (0x2U << RTC_ALRMAR_HT_Pos)
 
#define RTC_ALRMAR_HU_Pos   (16U)
 
#define RTC_ALRMAR_HU_Msk   (0xFU << RTC_ALRMAR_HU_Pos)
 
#define RTC_ALRMAR_HU   RTC_ALRMAR_HU_Msk
 
#define RTC_ALRMAR_HU_0   (0x1U << RTC_ALRMAR_HU_Pos)
 
#define RTC_ALRMAR_HU_1   (0x2U << RTC_ALRMAR_HU_Pos)
 
#define RTC_ALRMAR_HU_2   (0x4U << RTC_ALRMAR_HU_Pos)
 
#define RTC_ALRMAR_HU_3   (0x8U << RTC_ALRMAR_HU_Pos)
 
#define RTC_ALRMAR_MSK2_Pos   (15U)
 
#define RTC_ALRMAR_MSK2_Msk   (0x1U << RTC_ALRMAR_MSK2_Pos)
 
#define RTC_ALRMAR_MSK2   RTC_ALRMAR_MSK2_Msk
 
#define RTC_ALRMAR_MNT_Pos   (12U)
 
#define RTC_ALRMAR_MNT_Msk   (0x7U << RTC_ALRMAR_MNT_Pos)
 
#define RTC_ALRMAR_MNT   RTC_ALRMAR_MNT_Msk
 
#define RTC_ALRMAR_MNT_0   (0x1U << RTC_ALRMAR_MNT_Pos)
 
#define RTC_ALRMAR_MNT_1   (0x2U << RTC_ALRMAR_MNT_Pos)
 
#define RTC_ALRMAR_MNT_2   (0x4U << RTC_ALRMAR_MNT_Pos)
 
#define RTC_ALRMAR_MNU_Pos   (8U)
 
#define RTC_ALRMAR_MNU_Msk   (0xFU << RTC_ALRMAR_MNU_Pos)
 
#define RTC_ALRMAR_MNU   RTC_ALRMAR_MNU_Msk
 
#define RTC_ALRMAR_MNU_0   (0x1U << RTC_ALRMAR_MNU_Pos)
 
#define RTC_ALRMAR_MNU_1   (0x2U << RTC_ALRMAR_MNU_Pos)
 
#define RTC_ALRMAR_MNU_2   (0x4U << RTC_ALRMAR_MNU_Pos)
 
#define RTC_ALRMAR_MNU_3   (0x8U << RTC_ALRMAR_MNU_Pos)
 
#define RTC_ALRMAR_MSK1_Pos   (7U)
 
#define RTC_ALRMAR_MSK1_Msk   (0x1U << RTC_ALRMAR_MSK1_Pos)
 
#define RTC_ALRMAR_MSK1   RTC_ALRMAR_MSK1_Msk
 
#define RTC_ALRMAR_ST_Pos   (4U)
 
#define RTC_ALRMAR_ST_Msk   (0x7U << RTC_ALRMAR_ST_Pos)
 
#define RTC_ALRMAR_ST   RTC_ALRMAR_ST_Msk
 
#define RTC_ALRMAR_ST_0   (0x1U << RTC_ALRMAR_ST_Pos)
 
#define RTC_ALRMAR_ST_1   (0x2U << RTC_ALRMAR_ST_Pos)
 
#define RTC_ALRMAR_ST_2   (0x4U << RTC_ALRMAR_ST_Pos)
 
#define RTC_ALRMAR_SU_Pos   (0U)
 
#define RTC_ALRMAR_SU_Msk   (0xFU << RTC_ALRMAR_SU_Pos)
 
#define RTC_ALRMAR_SU   RTC_ALRMAR_SU_Msk
 
#define RTC_ALRMAR_SU_0   (0x1U << RTC_ALRMAR_SU_Pos)
 
#define RTC_ALRMAR_SU_1   (0x2U << RTC_ALRMAR_SU_Pos)
 
#define RTC_ALRMAR_SU_2   (0x4U << RTC_ALRMAR_SU_Pos)
 
#define RTC_ALRMAR_SU_3   (0x8U << RTC_ALRMAR_SU_Pos)
 
#define RTC_ALRMBR_MSK4_Pos   (31U)
 
#define RTC_ALRMBR_MSK4_Msk   (0x1U << RTC_ALRMBR_MSK4_Pos)
 
#define RTC_ALRMBR_MSK4   RTC_ALRMBR_MSK4_Msk
 
#define RTC_ALRMBR_WDSEL_Pos   (30U)
 
#define RTC_ALRMBR_WDSEL_Msk   (0x1U << RTC_ALRMBR_WDSEL_Pos)
 
#define RTC_ALRMBR_WDSEL   RTC_ALRMBR_WDSEL_Msk
 
#define RTC_ALRMBR_DT_Pos   (28U)
 
#define RTC_ALRMBR_DT_Msk   (0x3U << RTC_ALRMBR_DT_Pos)
 
#define RTC_ALRMBR_DT   RTC_ALRMBR_DT_Msk
 
#define RTC_ALRMBR_DT_0   (0x1U << RTC_ALRMBR_DT_Pos)
 
#define RTC_ALRMBR_DT_1   (0x2U << RTC_ALRMBR_DT_Pos)
 
#define RTC_ALRMBR_DU_Pos   (24U)
 
#define RTC_ALRMBR_DU_Msk   (0xFU << RTC_ALRMBR_DU_Pos)
 
#define RTC_ALRMBR_DU   RTC_ALRMBR_DU_Msk
 
#define RTC_ALRMBR_DU_0   (0x1U << RTC_ALRMBR_DU_Pos)
 
#define RTC_ALRMBR_DU_1   (0x2U << RTC_ALRMBR_DU_Pos)
 
#define RTC_ALRMBR_DU_2   (0x4U << RTC_ALRMBR_DU_Pos)
 
#define RTC_ALRMBR_DU_3   (0x8U << RTC_ALRMBR_DU_Pos)
 
#define RTC_ALRMBR_MSK3_Pos   (23U)
 
#define RTC_ALRMBR_MSK3_Msk   (0x1U << RTC_ALRMBR_MSK3_Pos)
 
#define RTC_ALRMBR_MSK3   RTC_ALRMBR_MSK3_Msk
 
#define RTC_ALRMBR_PM_Pos   (22U)
 
#define RTC_ALRMBR_PM_Msk   (0x1U << RTC_ALRMBR_PM_Pos)
 
#define RTC_ALRMBR_PM   RTC_ALRMBR_PM_Msk
 
#define RTC_ALRMBR_HT_Pos   (20U)
 
#define RTC_ALRMBR_HT_Msk   (0x3U << RTC_ALRMBR_HT_Pos)
 
#define RTC_ALRMBR_HT   RTC_ALRMBR_HT_Msk
 
#define RTC_ALRMBR_HT_0   (0x1U << RTC_ALRMBR_HT_Pos)
 
#define RTC_ALRMBR_HT_1   (0x2U << RTC_ALRMBR_HT_Pos)
 
#define RTC_ALRMBR_HU_Pos   (16U)
 
#define RTC_ALRMBR_HU_Msk   (0xFU << RTC_ALRMBR_HU_Pos)
 
#define RTC_ALRMBR_HU   RTC_ALRMBR_HU_Msk
 
#define RTC_ALRMBR_HU_0   (0x1U << RTC_ALRMBR_HU_Pos)
 
#define RTC_ALRMBR_HU_1   (0x2U << RTC_ALRMBR_HU_Pos)
 
#define RTC_ALRMBR_HU_2   (0x4U << RTC_ALRMBR_HU_Pos)
 
#define RTC_ALRMBR_HU_3   (0x8U << RTC_ALRMBR_HU_Pos)
 
#define RTC_ALRMBR_MSK2_Pos   (15U)
 
#define RTC_ALRMBR_MSK2_Msk   (0x1U << RTC_ALRMBR_MSK2_Pos)
 
#define RTC_ALRMBR_MSK2   RTC_ALRMBR_MSK2_Msk
 
#define RTC_ALRMBR_MNT_Pos   (12U)
 
#define RTC_ALRMBR_MNT_Msk   (0x7U << RTC_ALRMBR_MNT_Pos)
 
#define RTC_ALRMBR_MNT   RTC_ALRMBR_MNT_Msk
 
#define RTC_ALRMBR_MNT_0   (0x1U << RTC_ALRMBR_MNT_Pos)
 
#define RTC_ALRMBR_MNT_1   (0x2U << RTC_ALRMBR_MNT_Pos)
 
#define RTC_ALRMBR_MNT_2   (0x4U << RTC_ALRMBR_MNT_Pos)
 
#define RTC_ALRMBR_MNU_Pos   (8U)
 
#define RTC_ALRMBR_MNU_Msk   (0xFU << RTC_ALRMBR_MNU_Pos)
 
#define RTC_ALRMBR_MNU   RTC_ALRMBR_MNU_Msk
 
#define RTC_ALRMBR_MNU_0   (0x1U << RTC_ALRMBR_MNU_Pos)
 
#define RTC_ALRMBR_MNU_1   (0x2U << RTC_ALRMBR_MNU_Pos)
 
#define RTC_ALRMBR_MNU_2   (0x4U << RTC_ALRMBR_MNU_Pos)
 
#define RTC_ALRMBR_MNU_3   (0x8U << RTC_ALRMBR_MNU_Pos)
 
#define RTC_ALRMBR_MSK1_Pos   (7U)
 
#define RTC_ALRMBR_MSK1_Msk   (0x1U << RTC_ALRMBR_MSK1_Pos)
 
#define RTC_ALRMBR_MSK1   RTC_ALRMBR_MSK1_Msk
 
#define RTC_ALRMBR_ST_Pos   (4U)
 
#define RTC_ALRMBR_ST_Msk   (0x7U << RTC_ALRMBR_ST_Pos)
 
#define RTC_ALRMBR_ST   RTC_ALRMBR_ST_Msk
 
#define RTC_ALRMBR_ST_0   (0x1U << RTC_ALRMBR_ST_Pos)
 
#define RTC_ALRMBR_ST_1   (0x2U << RTC_ALRMBR_ST_Pos)
 
#define RTC_ALRMBR_ST_2   (0x4U << RTC_ALRMBR_ST_Pos)
 
#define RTC_ALRMBR_SU_Pos   (0U)
 
#define RTC_ALRMBR_SU_Msk   (0xFU << RTC_ALRMBR_SU_Pos)
 
#define RTC_ALRMBR_SU   RTC_ALRMBR_SU_Msk
 
#define RTC_ALRMBR_SU_0   (0x1U << RTC_ALRMBR_SU_Pos)
 
#define RTC_ALRMBR_SU_1   (0x2U << RTC_ALRMBR_SU_Pos)
 
#define RTC_ALRMBR_SU_2   (0x4U << RTC_ALRMBR_SU_Pos)
 
#define RTC_ALRMBR_SU_3   (0x8U << RTC_ALRMBR_SU_Pos)
 
#define RTC_WPR_KEY_Pos   (0U)
 
#define RTC_WPR_KEY_Msk   (0xFFU << RTC_WPR_KEY_Pos)
 
#define RTC_WPR_KEY   RTC_WPR_KEY_Msk
 
#define RTC_SSR_SS_Pos   (0U)
 
#define RTC_SSR_SS_Msk   (0xFFFFU << RTC_SSR_SS_Pos)
 
#define RTC_SSR_SS   RTC_SSR_SS_Msk
 
#define RTC_SHIFTR_SUBFS_Pos   (0U)
 
#define RTC_SHIFTR_SUBFS_Msk   (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)
 
#define RTC_SHIFTR_SUBFS   RTC_SHIFTR_SUBFS_Msk
 
#define RTC_SHIFTR_ADD1S_Pos   (31U)
 
#define RTC_SHIFTR_ADD1S_Msk   (0x1U << RTC_SHIFTR_ADD1S_Pos)
 
#define RTC_SHIFTR_ADD1S   RTC_SHIFTR_ADD1S_Msk
 
#define RTC_TSTR_PM_Pos   (22U)
 
#define RTC_TSTR_PM_Msk   (0x1U << RTC_TSTR_PM_Pos)
 
#define RTC_TSTR_PM   RTC_TSTR_PM_Msk
 
#define RTC_TSTR_HT_Pos   (20U)
 
#define RTC_TSTR_HT_Msk   (0x3U << RTC_TSTR_HT_Pos)
 
#define RTC_TSTR_HT   RTC_TSTR_HT_Msk
 
#define RTC_TSTR_HT_0   (0x1U << RTC_TSTR_HT_Pos)
 
#define RTC_TSTR_HT_1   (0x2U << RTC_TSTR_HT_Pos)
 
#define RTC_TSTR_HU_Pos   (16U)
 
#define RTC_TSTR_HU_Msk   (0xFU << RTC_TSTR_HU_Pos)
 
#define RTC_TSTR_HU   RTC_TSTR_HU_Msk
 
#define RTC_TSTR_HU_0   (0x1U << RTC_TSTR_HU_Pos)
 
#define RTC_TSTR_HU_1   (0x2U << RTC_TSTR_HU_Pos)
 
#define RTC_TSTR_HU_2   (0x4U << RTC_TSTR_HU_Pos)
 
#define RTC_TSTR_HU_3   (0x8U << RTC_TSTR_HU_Pos)
 
#define RTC_TSTR_MNT_Pos   (12U)
 
#define RTC_TSTR_MNT_Msk   (0x7U << RTC_TSTR_MNT_Pos)
 
#define RTC_TSTR_MNT   RTC_TSTR_MNT_Msk
 
#define RTC_TSTR_MNT_0   (0x1U << RTC_TSTR_MNT_Pos)
 
#define RTC_TSTR_MNT_1   (0x2U << RTC_TSTR_MNT_Pos)
 
#define RTC_TSTR_MNT_2   (0x4U << RTC_TSTR_MNT_Pos)
 
#define RTC_TSTR_MNU_Pos   (8U)
 
#define RTC_TSTR_MNU_Msk   (0xFU << RTC_TSTR_MNU_Pos)
 
#define RTC_TSTR_MNU   RTC_TSTR_MNU_Msk
 
#define RTC_TSTR_MNU_0   (0x1U << RTC_TSTR_MNU_Pos)
 
#define RTC_TSTR_MNU_1   (0x2U << RTC_TSTR_MNU_Pos)
 
#define RTC_TSTR_MNU_2   (0x4U << RTC_TSTR_MNU_Pos)
 
#define RTC_TSTR_MNU_3   (0x8U << RTC_TSTR_MNU_Pos)
 
#define RTC_TSTR_ST_Pos   (4U)
 
#define RTC_TSTR_ST_Msk   (0x7U << RTC_TSTR_ST_Pos)
 
#define RTC_TSTR_ST   RTC_TSTR_ST_Msk
 
#define RTC_TSTR_ST_0   (0x1U << RTC_TSTR_ST_Pos)
 
#define RTC_TSTR_ST_1   (0x2U << RTC_TSTR_ST_Pos)
 
#define RTC_TSTR_ST_2   (0x4U << RTC_TSTR_ST_Pos)
 
#define RTC_TSTR_SU_Pos   (0U)
 
#define RTC_TSTR_SU_Msk   (0xFU << RTC_TSTR_SU_Pos)
 
#define RTC_TSTR_SU   RTC_TSTR_SU_Msk
 
#define RTC_TSTR_SU_0   (0x1U << RTC_TSTR_SU_Pos)
 
#define RTC_TSTR_SU_1   (0x2U << RTC_TSTR_SU_Pos)
 
#define RTC_TSTR_SU_2   (0x4U << RTC_TSTR_SU_Pos)
 
#define RTC_TSTR_SU_3   (0x8U << RTC_TSTR_SU_Pos)
 
#define RTC_TSDR_WDU_Pos   (13U)
 
#define RTC_TSDR_WDU_Msk   (0x7U << RTC_TSDR_WDU_Pos)
 
#define RTC_TSDR_WDU   RTC_TSDR_WDU_Msk
 
#define RTC_TSDR_WDU_0   (0x1U << RTC_TSDR_WDU_Pos)
 
#define RTC_TSDR_WDU_1   (0x2U << RTC_TSDR_WDU_Pos)
 
#define RTC_TSDR_WDU_2   (0x4U << RTC_TSDR_WDU_Pos)
 
#define RTC_TSDR_MT_Pos   (12U)
 
#define RTC_TSDR_MT_Msk   (0x1U << RTC_TSDR_MT_Pos)
 
#define RTC_TSDR_MT   RTC_TSDR_MT_Msk
 
#define RTC_TSDR_MU_Pos   (8U)
 
#define RTC_TSDR_MU_Msk   (0xFU << RTC_TSDR_MU_Pos)
 
#define RTC_TSDR_MU   RTC_TSDR_MU_Msk
 
#define RTC_TSDR_MU_0   (0x1U << RTC_TSDR_MU_Pos)
 
#define RTC_TSDR_MU_1   (0x2U << RTC_TSDR_MU_Pos)
 
#define RTC_TSDR_MU_2   (0x4U << RTC_TSDR_MU_Pos)
 
#define RTC_TSDR_MU_3   (0x8U << RTC_TSDR_MU_Pos)
 
#define RTC_TSDR_DT_Pos   (4U)
 
#define RTC_TSDR_DT_Msk   (0x3U << RTC_TSDR_DT_Pos)
 
#define RTC_TSDR_DT   RTC_TSDR_DT_Msk
 
#define RTC_TSDR_DT_0   (0x1U << RTC_TSDR_DT_Pos)
 
#define RTC_TSDR_DT_1   (0x2U << RTC_TSDR_DT_Pos)
 
#define RTC_TSDR_DU_Pos   (0U)
 
#define RTC_TSDR_DU_Msk   (0xFU << RTC_TSDR_DU_Pos)
 
#define RTC_TSDR_DU   RTC_TSDR_DU_Msk
 
#define RTC_TSDR_DU_0   (0x1U << RTC_TSDR_DU_Pos)
 
#define RTC_TSDR_DU_1   (0x2U << RTC_TSDR_DU_Pos)
 
#define RTC_TSDR_DU_2   (0x4U << RTC_TSDR_DU_Pos)
 
#define RTC_TSDR_DU_3   (0x8U << RTC_TSDR_DU_Pos)
 
#define RTC_TSSSR_SS_Pos   (0U)
 
#define RTC_TSSSR_SS_Msk   (0xFFFFU << RTC_TSSSR_SS_Pos)
 
#define RTC_TSSSR_SS   RTC_TSSSR_SS_Msk
 
#define RTC_CALR_CALP_Pos   (15U)
 
#define RTC_CALR_CALP_Msk   (0x1U << RTC_CALR_CALP_Pos)
 
#define RTC_CALR_CALP   RTC_CALR_CALP_Msk
 
#define RTC_CALR_CALW8_Pos   (14U)
 
#define RTC_CALR_CALW8_Msk   (0x1U << RTC_CALR_CALW8_Pos)
 
#define RTC_CALR_CALW8   RTC_CALR_CALW8_Msk
 
#define RTC_CALR_CALW16_Pos   (13U)
 
#define RTC_CALR_CALW16_Msk   (0x1U << RTC_CALR_CALW16_Pos)
 
#define RTC_CALR_CALW16   RTC_CALR_CALW16_Msk
 
#define RTC_CALR_CALM_Pos   (0U)
 
#define RTC_CALR_CALM_Msk   (0x1FFU << RTC_CALR_CALM_Pos)
 
#define RTC_CALR_CALM   RTC_CALR_CALM_Msk
 
#define RTC_CALR_CALM_0   (0x001U << RTC_CALR_CALM_Pos)
 
#define RTC_CALR_CALM_1   (0x002U << RTC_CALR_CALM_Pos)
 
#define RTC_CALR_CALM_2   (0x004U << RTC_CALR_CALM_Pos)
 
#define RTC_CALR_CALM_3   (0x008U << RTC_CALR_CALM_Pos)
 
#define RTC_CALR_CALM_4   (0x010U << RTC_CALR_CALM_Pos)
 
#define RTC_CALR_CALM_5   (0x020U << RTC_CALR_CALM_Pos)
 
#define RTC_CALR_CALM_6   (0x040U << RTC_CALR_CALM_Pos)
 
#define RTC_CALR_CALM_7   (0x080U << RTC_CALR_CALM_Pos)
 
#define RTC_CALR_CALM_8   (0x100U << RTC_CALR_CALM_Pos)
 
#define RTC_TAFCR_ALARMOUTTYPE_Pos   (18U)
 
#define RTC_TAFCR_ALARMOUTTYPE_Msk   (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos)
 
#define RTC_TAFCR_ALARMOUTTYPE   RTC_TAFCR_ALARMOUTTYPE_Msk
 
#define RTC_TAFCR_TAMPPUDIS_Pos   (15U)
 
#define RTC_TAFCR_TAMPPUDIS_Msk   (0x1U << RTC_TAFCR_TAMPPUDIS_Pos)
 
#define RTC_TAFCR_TAMPPUDIS   RTC_TAFCR_TAMPPUDIS_Msk
 
#define RTC_TAFCR_TAMPPRCH_Pos   (13U)
 
#define RTC_TAFCR_TAMPPRCH_Msk   (0x3U << RTC_TAFCR_TAMPPRCH_Pos)
 
#define RTC_TAFCR_TAMPPRCH   RTC_TAFCR_TAMPPRCH_Msk
 
#define RTC_TAFCR_TAMPPRCH_0   (0x1U << RTC_TAFCR_TAMPPRCH_Pos)
 
#define RTC_TAFCR_TAMPPRCH_1   (0x2U << RTC_TAFCR_TAMPPRCH_Pos)
 
#define RTC_TAFCR_TAMPFLT_Pos   (11U)
 
#define RTC_TAFCR_TAMPFLT_Msk   (0x3U << RTC_TAFCR_TAMPFLT_Pos)
 
#define RTC_TAFCR_TAMPFLT   RTC_TAFCR_TAMPFLT_Msk
 
#define RTC_TAFCR_TAMPFLT_0   (0x1U << RTC_TAFCR_TAMPFLT_Pos)
 
#define RTC_TAFCR_TAMPFLT_1   (0x2U << RTC_TAFCR_TAMPFLT_Pos)
 
#define RTC_TAFCR_TAMPFREQ_Pos   (8U)
 
#define RTC_TAFCR_TAMPFREQ_Msk   (0x7U << RTC_TAFCR_TAMPFREQ_Pos)
 
#define RTC_TAFCR_TAMPFREQ   RTC_TAFCR_TAMPFREQ_Msk
 
#define RTC_TAFCR_TAMPFREQ_0   (0x1U << RTC_TAFCR_TAMPFREQ_Pos)
 
#define RTC_TAFCR_TAMPFREQ_1   (0x2U << RTC_TAFCR_TAMPFREQ_Pos)
 
#define RTC_TAFCR_TAMPFREQ_2   (0x4U << RTC_TAFCR_TAMPFREQ_Pos)
 
#define RTC_TAFCR_TAMPTS_Pos   (7U)
 
#define RTC_TAFCR_TAMPTS_Msk   (0x1U << RTC_TAFCR_TAMPTS_Pos)
 
#define RTC_TAFCR_TAMPTS   RTC_TAFCR_TAMPTS_Msk
 
#define RTC_TAFCR_TAMP3TRG_Pos   (6U)
 
#define RTC_TAFCR_TAMP3TRG_Msk   (0x1U << RTC_TAFCR_TAMP3TRG_Pos)
 
#define RTC_TAFCR_TAMP3TRG   RTC_TAFCR_TAMP3TRG_Msk
 
#define RTC_TAFCR_TAMP3E_Pos   (5U)
 
#define RTC_TAFCR_TAMP3E_Msk   (0x1U << RTC_TAFCR_TAMP3E_Pos)
 
#define RTC_TAFCR_TAMP3E   RTC_TAFCR_TAMP3E_Msk
 
#define RTC_TAFCR_TAMP2TRG_Pos   (4U)
 
#define RTC_TAFCR_TAMP2TRG_Msk   (0x1U << RTC_TAFCR_TAMP2TRG_Pos)
 
#define RTC_TAFCR_TAMP2TRG   RTC_TAFCR_TAMP2TRG_Msk
 
#define RTC_TAFCR_TAMP2E_Pos   (3U)
 
#define RTC_TAFCR_TAMP2E_Msk   (0x1U << RTC_TAFCR_TAMP2E_Pos)
 
#define RTC_TAFCR_TAMP2E   RTC_TAFCR_TAMP2E_Msk
 
#define RTC_TAFCR_TAMPIE_Pos   (2U)
 
#define RTC_TAFCR_TAMPIE_Msk   (0x1U << RTC_TAFCR_TAMPIE_Pos)
 
#define RTC_TAFCR_TAMPIE   RTC_TAFCR_TAMPIE_Msk
 
#define RTC_TAFCR_TAMP1TRG_Pos   (1U)
 
#define RTC_TAFCR_TAMP1TRG_Msk   (0x1U << RTC_TAFCR_TAMP1TRG_Pos)
 
#define RTC_TAFCR_TAMP1TRG   RTC_TAFCR_TAMP1TRG_Msk
 
#define RTC_TAFCR_TAMP1E_Pos   (0U)
 
#define RTC_TAFCR_TAMP1E_Msk   (0x1U << RTC_TAFCR_TAMP1E_Pos)
 
#define RTC_TAFCR_TAMP1E   RTC_TAFCR_TAMP1E_Msk
 
#define RTC_ALRMASSR_MASKSS_Pos   (24U)
 
#define RTC_ALRMASSR_MASKSS_Msk   (0xFU << RTC_ALRMASSR_MASKSS_Pos)
 
#define RTC_ALRMASSR_MASKSS   RTC_ALRMASSR_MASKSS_Msk
 
#define RTC_ALRMASSR_MASKSS_0   (0x1U << RTC_ALRMASSR_MASKSS_Pos)
 
#define RTC_ALRMASSR_MASKSS_1   (0x2U << RTC_ALRMASSR_MASKSS_Pos)
 
#define RTC_ALRMASSR_MASKSS_2   (0x4U << RTC_ALRMASSR_MASKSS_Pos)
 
#define RTC_ALRMASSR_MASKSS_3   (0x8U << RTC_ALRMASSR_MASKSS_Pos)
 
#define RTC_ALRMASSR_SS_Pos   (0U)
 
#define RTC_ALRMASSR_SS_Msk   (0x7FFFU << RTC_ALRMASSR_SS_Pos)
 
#define RTC_ALRMASSR_SS   RTC_ALRMASSR_SS_Msk
 
#define RTC_ALRMBSSR_MASKSS_Pos   (24U)
 
#define RTC_ALRMBSSR_MASKSS_Msk   (0xFU << RTC_ALRMBSSR_MASKSS_Pos)
 
#define RTC_ALRMBSSR_MASKSS   RTC_ALRMBSSR_MASKSS_Msk
 
#define RTC_ALRMBSSR_MASKSS_0   (0x1U << RTC_ALRMBSSR_MASKSS_Pos)
 
#define RTC_ALRMBSSR_MASKSS_1   (0x2U << RTC_ALRMBSSR_MASKSS_Pos)
 
#define RTC_ALRMBSSR_MASKSS_2   (0x4U << RTC_ALRMBSSR_MASKSS_Pos)
 
#define RTC_ALRMBSSR_MASKSS_3   (0x8U << RTC_ALRMBSSR_MASKSS_Pos)
 
#define RTC_ALRMBSSR_SS_Pos   (0U)
 
#define RTC_ALRMBSSR_SS_Msk   (0x7FFFU << RTC_ALRMBSSR_SS_Pos)
 
#define RTC_ALRMBSSR_SS   RTC_ALRMBSSR_SS_Msk
 
#define RTC_BKP0R_Pos   (0U)
 
#define RTC_BKP0R_Msk   (0xFFFFFFFFU << RTC_BKP0R_Pos)
 
#define RTC_BKP0R   RTC_BKP0R_Msk
 
#define RTC_BKP1R_Pos   (0U)
 
#define RTC_BKP1R_Msk   (0xFFFFFFFFU << RTC_BKP1R_Pos)
 
#define RTC_BKP1R   RTC_BKP1R_Msk
 
#define RTC_BKP2R_Pos   (0U)
 
#define RTC_BKP2R_Msk   (0xFFFFFFFFU << RTC_BKP2R_Pos)
 
#define RTC_BKP2R   RTC_BKP2R_Msk
 
#define RTC_BKP3R_Pos   (0U)
 
#define RTC_BKP3R_Msk   (0xFFFFFFFFU << RTC_BKP3R_Pos)
 
#define RTC_BKP3R   RTC_BKP3R_Msk
 
#define RTC_BKP4R_Pos   (0U)
 
#define RTC_BKP4R_Msk   (0xFFFFFFFFU << RTC_BKP4R_Pos)
 
#define RTC_BKP4R   RTC_BKP4R_Msk
 
#define RTC_BKP5R_Pos   (0U)
 
#define RTC_BKP5R_Msk   (0xFFFFFFFFU << RTC_BKP5R_Pos)
 
#define RTC_BKP5R   RTC_BKP5R_Msk
 
#define RTC_BKP6R_Pos   (0U)
 
#define RTC_BKP6R_Msk   (0xFFFFFFFFU << RTC_BKP6R_Pos)
 
#define RTC_BKP6R   RTC_BKP6R_Msk
 
#define RTC_BKP7R_Pos   (0U)
 
#define RTC_BKP7R_Msk   (0xFFFFFFFFU << RTC_BKP7R_Pos)
 
#define RTC_BKP7R   RTC_BKP7R_Msk
 
#define RTC_BKP8R_Pos   (0U)
 
#define RTC_BKP8R_Msk   (0xFFFFFFFFU << RTC_BKP8R_Pos)
 
#define RTC_BKP8R   RTC_BKP8R_Msk
 
#define RTC_BKP9R_Pos   (0U)
 
#define RTC_BKP9R_Msk   (0xFFFFFFFFU << RTC_BKP9R_Pos)
 
#define RTC_BKP9R   RTC_BKP9R_Msk
 
#define RTC_BKP10R_Pos   (0U)
 
#define RTC_BKP10R_Msk   (0xFFFFFFFFU << RTC_BKP10R_Pos)
 
#define RTC_BKP10R   RTC_BKP10R_Msk
 
#define RTC_BKP11R_Pos   (0U)
 
#define RTC_BKP11R_Msk   (0xFFFFFFFFU << RTC_BKP11R_Pos)
 
#define RTC_BKP11R   RTC_BKP11R_Msk
 
#define RTC_BKP12R_Pos   (0U)
 
#define RTC_BKP12R_Msk   (0xFFFFFFFFU << RTC_BKP12R_Pos)
 
#define RTC_BKP12R   RTC_BKP12R_Msk
 
#define RTC_BKP13R_Pos   (0U)
 
#define RTC_BKP13R_Msk   (0xFFFFFFFFU << RTC_BKP13R_Pos)
 
#define RTC_BKP13R   RTC_BKP13R_Msk
 
#define RTC_BKP14R_Pos   (0U)
 
#define RTC_BKP14R_Msk   (0xFFFFFFFFU << RTC_BKP14R_Pos)
 
#define RTC_BKP14R   RTC_BKP14R_Msk
 
#define RTC_BKP15R_Pos   (0U)
 
#define RTC_BKP15R_Msk   (0xFFFFFFFFU << RTC_BKP15R_Pos)
 
#define RTC_BKP15R   RTC_BKP15R_Msk
 
#define RTC_BKP16R_Pos   (0U)
 
#define RTC_BKP16R_Msk   (0xFFFFFFFFU << RTC_BKP16R_Pos)
 
#define RTC_BKP16R   RTC_BKP16R_Msk
 
#define RTC_BKP17R_Pos   (0U)
 
#define RTC_BKP17R_Msk   (0xFFFFFFFFU << RTC_BKP17R_Pos)
 
#define RTC_BKP17R   RTC_BKP17R_Msk
 
#define RTC_BKP18R_Pos   (0U)
 
#define RTC_BKP18R_Msk   (0xFFFFFFFFU << RTC_BKP18R_Pos)
 
#define RTC_BKP18R   RTC_BKP18R_Msk
 
#define RTC_BKP19R_Pos   (0U)
 
#define RTC_BKP19R_Msk   (0xFFFFFFFFU << RTC_BKP19R_Pos)
 
#define RTC_BKP19R   RTC_BKP19R_Msk
 
#define RTC_BKP20R_Pos   (0U)
 
#define RTC_BKP20R_Msk   (0xFFFFFFFFU << RTC_BKP20R_Pos)
 
#define RTC_BKP20R   RTC_BKP20R_Msk
 
#define RTC_BKP21R_Pos   (0U)
 
#define RTC_BKP21R_Msk   (0xFFFFFFFFU << RTC_BKP21R_Pos)
 
#define RTC_BKP21R   RTC_BKP21R_Msk
 
#define RTC_BKP22R_Pos   (0U)
 
#define RTC_BKP22R_Msk   (0xFFFFFFFFU << RTC_BKP22R_Pos)
 
#define RTC_BKP22R   RTC_BKP22R_Msk
 
#define RTC_BKP23R_Pos   (0U)
 
#define RTC_BKP23R_Msk   (0xFFFFFFFFU << RTC_BKP23R_Pos)
 
#define RTC_BKP23R   RTC_BKP23R_Msk
 
#define RTC_BKP24R_Pos   (0U)
 
#define RTC_BKP24R_Msk   (0xFFFFFFFFU << RTC_BKP24R_Pos)
 
#define RTC_BKP24R   RTC_BKP24R_Msk
 
#define RTC_BKP25R_Pos   (0U)
 
#define RTC_BKP25R_Msk   (0xFFFFFFFFU << RTC_BKP25R_Pos)
 
#define RTC_BKP25R   RTC_BKP25R_Msk
 
#define RTC_BKP26R_Pos   (0U)
 
#define RTC_BKP26R_Msk   (0xFFFFFFFFU << RTC_BKP26R_Pos)
 
#define RTC_BKP26R   RTC_BKP26R_Msk
 
#define RTC_BKP27R_Pos   (0U)
 
#define RTC_BKP27R_Msk   (0xFFFFFFFFU << RTC_BKP27R_Pos)
 
#define RTC_BKP27R   RTC_BKP27R_Msk
 
#define RTC_BKP28R_Pos   (0U)
 
#define RTC_BKP28R_Msk   (0xFFFFFFFFU << RTC_BKP28R_Pos)
 
#define RTC_BKP28R   RTC_BKP28R_Msk
 
#define RTC_BKP29R_Pos   (0U)
 
#define RTC_BKP29R_Msk   (0xFFFFFFFFU << RTC_BKP29R_Pos)
 
#define RTC_BKP29R   RTC_BKP29R_Msk
 
#define RTC_BKP30R_Pos   (0U)
 
#define RTC_BKP30R_Msk   (0xFFFFFFFFU << RTC_BKP30R_Pos)
 
#define RTC_BKP30R   RTC_BKP30R_Msk
 
#define RTC_BKP31R_Pos   (0U)
 
#define RTC_BKP31R_Msk   (0xFFFFFFFFU << RTC_BKP31R_Pos)
 
#define RTC_BKP31R   RTC_BKP31R_Msk
 
#define RTC_BKP_NUMBER   32
 
#define SPI_I2S_SUPPORT
 
#define SPI_CR1_CPHA_Pos   (0U)
 
#define SPI_CR1_CPHA_Msk   (0x1U << SPI_CR1_CPHA_Pos)
 
#define SPI_CR1_CPHA   SPI_CR1_CPHA_Msk
 
#define SPI_CR1_CPOL_Pos   (1U)
 
#define SPI_CR1_CPOL_Msk   (0x1U << SPI_CR1_CPOL_Pos)
 
#define SPI_CR1_CPOL   SPI_CR1_CPOL_Msk
 
#define SPI_CR1_MSTR_Pos   (2U)
 
#define SPI_CR1_MSTR_Msk   (0x1U << SPI_CR1_MSTR_Pos)
 
#define SPI_CR1_MSTR   SPI_CR1_MSTR_Msk
 
#define SPI_CR1_BR_Pos   (3U)
 
#define SPI_CR1_BR_Msk   (0x7U << SPI_CR1_BR_Pos)
 
#define SPI_CR1_BR   SPI_CR1_BR_Msk
 
#define SPI_CR1_BR_0   (0x1U << SPI_CR1_BR_Pos)
 
#define SPI_CR1_BR_1   (0x2U << SPI_CR1_BR_Pos)
 
#define SPI_CR1_BR_2   (0x4U << SPI_CR1_BR_Pos)
 
#define SPI_CR1_SPE_Pos   (6U)
 
#define SPI_CR1_SPE_Msk   (0x1U << SPI_CR1_SPE_Pos)
 
#define SPI_CR1_SPE   SPI_CR1_SPE_Msk
 
#define SPI_CR1_LSBFIRST_Pos   (7U)
 
#define SPI_CR1_LSBFIRST_Msk   (0x1U << SPI_CR1_LSBFIRST_Pos)
 
#define SPI_CR1_LSBFIRST   SPI_CR1_LSBFIRST_Msk
 
#define SPI_CR1_SSI_Pos   (8U)
 
#define SPI_CR1_SSI_Msk   (0x1U << SPI_CR1_SSI_Pos)
 
#define SPI_CR1_SSI   SPI_CR1_SSI_Msk
 
#define SPI_CR1_SSM_Pos   (9U)
 
#define SPI_CR1_SSM_Msk   (0x1U << SPI_CR1_SSM_Pos)
 
#define SPI_CR1_SSM   SPI_CR1_SSM_Msk
 
#define SPI_CR1_RXONLY_Pos   (10U)
 
#define SPI_CR1_RXONLY_Msk   (0x1U << SPI_CR1_RXONLY_Pos)
 
#define SPI_CR1_RXONLY   SPI_CR1_RXONLY_Msk
 
#define SPI_CR1_DFF_Pos   (11U)
 
#define SPI_CR1_DFF_Msk   (0x1U << SPI_CR1_DFF_Pos)
 
#define SPI_CR1_DFF   SPI_CR1_DFF_Msk
 
#define SPI_CR1_CRCNEXT_Pos   (12U)
 
#define SPI_CR1_CRCNEXT_Msk   (0x1U << SPI_CR1_CRCNEXT_Pos)
 
#define SPI_CR1_CRCNEXT   SPI_CR1_CRCNEXT_Msk
 
#define SPI_CR1_CRCEN_Pos   (13U)
 
#define SPI_CR1_CRCEN_Msk   (0x1U << SPI_CR1_CRCEN_Pos)
 
#define SPI_CR1_CRCEN   SPI_CR1_CRCEN_Msk
 
#define SPI_CR1_BIDIOE_Pos   (14U)
 
#define SPI_CR1_BIDIOE_Msk   (0x1U << SPI_CR1_BIDIOE_Pos)
 
#define SPI_CR1_BIDIOE   SPI_CR1_BIDIOE_Msk
 
#define SPI_CR1_BIDIMODE_Pos   (15U)
 
#define SPI_CR1_BIDIMODE_Msk   (0x1U << SPI_CR1_BIDIMODE_Pos)
 
#define SPI_CR1_BIDIMODE   SPI_CR1_BIDIMODE_Msk
 
#define SPI_CR2_RXDMAEN_Pos   (0U)
 
#define SPI_CR2_RXDMAEN_Msk   (0x1U << SPI_CR2_RXDMAEN_Pos)
 
#define SPI_CR2_RXDMAEN   SPI_CR2_RXDMAEN_Msk
 
#define SPI_CR2_TXDMAEN_Pos   (1U)
 
#define SPI_CR2_TXDMAEN_Msk   (0x1U << SPI_CR2_TXDMAEN_Pos)
 
#define SPI_CR2_TXDMAEN   SPI_CR2_TXDMAEN_Msk
 
#define SPI_CR2_SSOE_Pos   (2U)
 
#define SPI_CR2_SSOE_Msk   (0x1U << SPI_CR2_SSOE_Pos)
 
#define SPI_CR2_SSOE   SPI_CR2_SSOE_Msk
 
#define SPI_CR2_FRF_Pos   (4U)
 
#define SPI_CR2_FRF_Msk   (0x1U << SPI_CR2_FRF_Pos)
 
#define SPI_CR2_FRF   SPI_CR2_FRF_Msk
 
#define SPI_CR2_ERRIE_Pos   (5U)
 
#define SPI_CR2_ERRIE_Msk   (0x1U << SPI_CR2_ERRIE_Pos)
 
#define SPI_CR2_ERRIE   SPI_CR2_ERRIE_Msk
 
#define SPI_CR2_RXNEIE_Pos   (6U)
 
#define SPI_CR2_RXNEIE_Msk   (0x1U << SPI_CR2_RXNEIE_Pos)
 
#define SPI_CR2_RXNEIE   SPI_CR2_RXNEIE_Msk
 
#define SPI_CR2_TXEIE_Pos   (7U)
 
#define SPI_CR2_TXEIE_Msk   (0x1U << SPI_CR2_TXEIE_Pos)
 
#define SPI_CR2_TXEIE   SPI_CR2_TXEIE_Msk
 
#define SPI_SR_RXNE_Pos   (0U)
 
#define SPI_SR_RXNE_Msk   (0x1U << SPI_SR_RXNE_Pos)
 
#define SPI_SR_RXNE   SPI_SR_RXNE_Msk
 
#define SPI_SR_TXE_Pos   (1U)
 
#define SPI_SR_TXE_Msk   (0x1U << SPI_SR_TXE_Pos)
 
#define SPI_SR_TXE   SPI_SR_TXE_Msk
 
#define SPI_SR_CHSIDE_Pos   (2U)
 
#define SPI_SR_CHSIDE_Msk   (0x1U << SPI_SR_CHSIDE_Pos)
 
#define SPI_SR_CHSIDE   SPI_SR_CHSIDE_Msk
 
#define SPI_SR_UDR_Pos   (3U)
 
#define SPI_SR_UDR_Msk   (0x1U << SPI_SR_UDR_Pos)
 
#define SPI_SR_UDR   SPI_SR_UDR_Msk
 
#define SPI_SR_CRCERR_Pos   (4U)
 
#define SPI_SR_CRCERR_Msk   (0x1U << SPI_SR_CRCERR_Pos)
 
#define SPI_SR_CRCERR   SPI_SR_CRCERR_Msk
 
#define SPI_SR_MODF_Pos   (5U)
 
#define SPI_SR_MODF_Msk   (0x1U << SPI_SR_MODF_Pos)
 
#define SPI_SR_MODF   SPI_SR_MODF_Msk
 
#define SPI_SR_OVR_Pos   (6U)
 
#define SPI_SR_OVR_Msk   (0x1U << SPI_SR_OVR_Pos)
 
#define SPI_SR_OVR   SPI_SR_OVR_Msk
 
#define SPI_SR_BSY_Pos   (7U)
 
#define SPI_SR_BSY_Msk   (0x1U << SPI_SR_BSY_Pos)
 
#define SPI_SR_BSY   SPI_SR_BSY_Msk
 
#define SPI_SR_FRE_Pos   (8U)
 
#define SPI_SR_FRE_Msk   (0x1U << SPI_SR_FRE_Pos)
 
#define SPI_SR_FRE   SPI_SR_FRE_Msk
 
#define SPI_DR_DR_Pos   (0U)
 
#define SPI_DR_DR_Msk   (0xFFFFU << SPI_DR_DR_Pos)
 
#define SPI_DR_DR   SPI_DR_DR_Msk
 
#define SPI_CRCPR_CRCPOLY_Pos   (0U)
 
#define SPI_CRCPR_CRCPOLY_Msk   (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)
 
#define SPI_CRCPR_CRCPOLY   SPI_CRCPR_CRCPOLY_Msk
 
#define SPI_RXCRCR_RXCRC_Pos   (0U)
 
#define SPI_RXCRCR_RXCRC_Msk   (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)
 
#define SPI_RXCRCR_RXCRC   SPI_RXCRCR_RXCRC_Msk
 
#define SPI_TXCRCR_TXCRC_Pos   (0U)
 
#define SPI_TXCRCR_TXCRC_Msk   (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)
 
#define SPI_TXCRCR_TXCRC   SPI_TXCRCR_TXCRC_Msk
 
#define SPI_I2SCFGR_CHLEN_Pos   (0U)
 
#define SPI_I2SCFGR_CHLEN_Msk   (0x1U << SPI_I2SCFGR_CHLEN_Pos)
 
#define SPI_I2SCFGR_CHLEN   SPI_I2SCFGR_CHLEN_Msk
 
#define SPI_I2SCFGR_DATLEN_Pos   (1U)
 
#define SPI_I2SCFGR_DATLEN_Msk   (0x3U << SPI_I2SCFGR_DATLEN_Pos)
 
#define SPI_I2SCFGR_DATLEN   SPI_I2SCFGR_DATLEN_Msk
 
#define SPI_I2SCFGR_DATLEN_0   (0x1U << SPI_I2SCFGR_DATLEN_Pos)
 
#define SPI_I2SCFGR_DATLEN_1   (0x2U << SPI_I2SCFGR_DATLEN_Pos)
 
#define SPI_I2SCFGR_CKPOL_Pos   (3U)
 
#define SPI_I2SCFGR_CKPOL_Msk   (0x1U << SPI_I2SCFGR_CKPOL_Pos)
 
#define SPI_I2SCFGR_CKPOL   SPI_I2SCFGR_CKPOL_Msk
 
#define SPI_I2SCFGR_I2SSTD_Pos   (4U)
 
#define SPI_I2SCFGR_I2SSTD_Msk   (0x3U << SPI_I2SCFGR_I2SSTD_Pos)
 
#define SPI_I2SCFGR_I2SSTD   SPI_I2SCFGR_I2SSTD_Msk
 
#define SPI_I2SCFGR_I2SSTD_0   (0x1U << SPI_I2SCFGR_I2SSTD_Pos)
 
#define SPI_I2SCFGR_I2SSTD_1   (0x2U << SPI_I2SCFGR_I2SSTD_Pos)
 
#define SPI_I2SCFGR_PCMSYNC_Pos   (7U)
 
#define SPI_I2SCFGR_PCMSYNC_Msk   (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)
 
#define SPI_I2SCFGR_PCMSYNC   SPI_I2SCFGR_PCMSYNC_Msk
 
#define SPI_I2SCFGR_I2SCFG_Pos   (8U)
 
#define SPI_I2SCFGR_I2SCFG_Msk   (0x3U << SPI_I2SCFGR_I2SCFG_Pos)
 
#define SPI_I2SCFGR_I2SCFG   SPI_I2SCFGR_I2SCFG_Msk
 
#define SPI_I2SCFGR_I2SCFG_0   (0x1U << SPI_I2SCFGR_I2SCFG_Pos)
 
#define SPI_I2SCFGR_I2SCFG_1   (0x2U << SPI_I2SCFGR_I2SCFG_Pos)
 
#define SPI_I2SCFGR_I2SE_Pos   (10U)
 
#define SPI_I2SCFGR_I2SE_Msk   (0x1U << SPI_I2SCFGR_I2SE_Pos)
 
#define SPI_I2SCFGR_I2SE   SPI_I2SCFGR_I2SE_Msk
 
#define SPI_I2SCFGR_I2SMOD_Pos   (11U)
 
#define SPI_I2SCFGR_I2SMOD_Msk   (0x1U << SPI_I2SCFGR_I2SMOD_Pos)
 
#define SPI_I2SCFGR_I2SMOD   SPI_I2SCFGR_I2SMOD_Msk
 
#define SPI_I2SPR_I2SDIV_Pos   (0U)
 
#define SPI_I2SPR_I2SDIV_Msk   (0xFFU << SPI_I2SPR_I2SDIV_Pos)
 
#define SPI_I2SPR_I2SDIV   SPI_I2SPR_I2SDIV_Msk
 
#define SPI_I2SPR_ODD_Pos   (8U)
 
#define SPI_I2SPR_ODD_Msk   (0x1U << SPI_I2SPR_ODD_Pos)
 
#define SPI_I2SPR_ODD   SPI_I2SPR_ODD_Msk
 
#define SPI_I2SPR_MCKOE_Pos   (9U)
 
#define SPI_I2SPR_MCKOE_Msk   (0x1U << SPI_I2SPR_MCKOE_Pos)
 
#define SPI_I2SPR_MCKOE   SPI_I2SPR_MCKOE_Msk
 
#define SYSCFG_MEMRMP_MEM_MODE_Pos   (0U)
 
#define SYSCFG_MEMRMP_MEM_MODE_Msk   (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos)
 
#define SYSCFG_MEMRMP_MEM_MODE   SYSCFG_MEMRMP_MEM_MODE_Msk
 
#define SYSCFG_MEMRMP_MEM_MODE_0   (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)
 
#define SYSCFG_MEMRMP_MEM_MODE_1   (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)
 
#define SYSCFG_MEMRMP_BOOT_MODE_Pos   (8U)
 
#define SYSCFG_MEMRMP_BOOT_MODE_Msk   (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos)
 
#define SYSCFG_MEMRMP_BOOT_MODE   SYSCFG_MEMRMP_BOOT_MODE_Msk
 
#define SYSCFG_MEMRMP_BOOT_MODE_0   (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos)
 
#define SYSCFG_MEMRMP_BOOT_MODE_1   (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos)
 
#define SYSCFG_PMC_USB_PU_Pos   (0U)
 
#define SYSCFG_PMC_USB_PU_Msk   (0x1U << SYSCFG_PMC_USB_PU_Pos)
 
#define SYSCFG_PMC_USB_PU   SYSCFG_PMC_USB_PU_Msk
 
#define SYSCFG_PMC_LCD_CAPA_Pos   (1U)
 
#define SYSCFG_PMC_LCD_CAPA_Msk   (0x1FU << SYSCFG_PMC_LCD_CAPA_Pos)
 
#define SYSCFG_PMC_LCD_CAPA   SYSCFG_PMC_LCD_CAPA_Msk
 
#define SYSCFG_PMC_LCD_CAPA_0   (0x01U << SYSCFG_PMC_LCD_CAPA_Pos)
 
#define SYSCFG_PMC_LCD_CAPA_1   (0x02U << SYSCFG_PMC_LCD_CAPA_Pos)
 
#define SYSCFG_PMC_LCD_CAPA_2   (0x04U << SYSCFG_PMC_LCD_CAPA_Pos)
 
#define SYSCFG_PMC_LCD_CAPA_3   (0x08U << SYSCFG_PMC_LCD_CAPA_Pos)
 
#define SYSCFG_PMC_LCD_CAPA_4   (0x10U << SYSCFG_PMC_LCD_CAPA_Pos)
 
#define SYSCFG_EXTICR1_EXTI0_Pos   (0U)
 
#define SYSCFG_EXTICR1_EXTI0_Msk   (0xFU << SYSCFG_EXTICR1_EXTI0_Pos)
 
#define SYSCFG_EXTICR1_EXTI0   SYSCFG_EXTICR1_EXTI0_Msk
 
#define SYSCFG_EXTICR1_EXTI1_Pos   (4U)
 
#define SYSCFG_EXTICR1_EXTI1_Msk   (0xFU << SYSCFG_EXTICR1_EXTI1_Pos)
 
#define SYSCFG_EXTICR1_EXTI1   SYSCFG_EXTICR1_EXTI1_Msk
 
#define SYSCFG_EXTICR1_EXTI2_Pos   (8U)
 
#define SYSCFG_EXTICR1_EXTI2_Msk   (0xFU << SYSCFG_EXTICR1_EXTI2_Pos)
 
#define SYSCFG_EXTICR1_EXTI2   SYSCFG_EXTICR1_EXTI2_Msk
 
#define SYSCFG_EXTICR1_EXTI3_Pos   (12U)
 
#define SYSCFG_EXTICR1_EXTI3_Msk   (0xFU << SYSCFG_EXTICR1_EXTI3_Pos)
 
#define SYSCFG_EXTICR1_EXTI3   SYSCFG_EXTICR1_EXTI3_Msk
 
#define SYSCFG_EXTICR1_EXTI0_PA   (0x00000000U)
 EXTI0 configuration

More...
 
#define SYSCFG_EXTICR1_EXTI0_PB   (0x00000001U)
 
#define SYSCFG_EXTICR1_EXTI0_PC   (0x00000002U)
 
#define SYSCFG_EXTICR1_EXTI0_PD   (0x00000003U)
 
#define SYSCFG_EXTICR1_EXTI0_PE   (0x00000004U)
 
#define SYSCFG_EXTICR1_EXTI0_PH   (0x00000005U)
 
#define SYSCFG_EXTICR1_EXTI0_PF   (0x00000006U)
 
#define SYSCFG_EXTICR1_EXTI0_PG   (0x00000007U)
 
#define SYSCFG_EXTICR1_EXTI1_PA   (0x00000000U)
 EXTI1 configuration

More...
 
#define SYSCFG_EXTICR1_EXTI1_PB   (0x00000010U)
 
#define SYSCFG_EXTICR1_EXTI1_PC   (0x00000020U)
 
#define SYSCFG_EXTICR1_EXTI1_PD   (0x00000030U)
 
#define SYSCFG_EXTICR1_EXTI1_PE   (0x00000040U)
 
#define SYSCFG_EXTICR1_EXTI1_PH   (0x00000050U)
 
#define SYSCFG_EXTICR1_EXTI1_PF   (0x00000060U)
 
#define SYSCFG_EXTICR1_EXTI1_PG   (0x00000070U)
 
#define SYSCFG_EXTICR1_EXTI2_PA   (0x00000000U)
 EXTI2 configuration

More...
 
#define SYSCFG_EXTICR1_EXTI2_PB   (0x00000100U)
 
#define SYSCFG_EXTICR1_EXTI2_PC   (0x00000200U)
 
#define SYSCFG_EXTICR1_EXTI2_PD   (0x00000300U)
 
#define SYSCFG_EXTICR1_EXTI2_PE   (0x00000400U)
 
#define SYSCFG_EXTICR1_EXTI2_PH   (0x00000500U)
 
#define SYSCFG_EXTICR1_EXTI2_PF   (0x00000600U)
 
#define SYSCFG_EXTICR1_EXTI2_PG   (0x00000700U)
 
#define SYSCFG_EXTICR1_EXTI3_PA   (0x00000000U)
 EXTI3 configuration

More...
 
#define SYSCFG_EXTICR1_EXTI3_PB   (0x00001000U)
 
#define SYSCFG_EXTICR1_EXTI3_PC   (0x00002000U)
 
#define SYSCFG_EXTICR1_EXTI3_PD   (0x00003000U)
 
#define SYSCFG_EXTICR1_EXTI3_PE   (0x00004000U)
 
#define SYSCFG_EXTICR1_EXTI3_PF   (0x00003000U)
 
#define SYSCFG_EXTICR1_EXTI3_PG   (0x00004000U)
 
#define SYSCFG_EXTICR2_EXTI4_Pos   (0U)
 
#define SYSCFG_EXTICR2_EXTI4_Msk   (0xFU << SYSCFG_EXTICR2_EXTI4_Pos)
 
#define SYSCFG_EXTICR2_EXTI4   SYSCFG_EXTICR2_EXTI4_Msk
 
#define SYSCFG_EXTICR2_EXTI5_Pos   (4U)
 
#define SYSCFG_EXTICR2_EXTI5_Msk   (0xFU << SYSCFG_EXTICR2_EXTI5_Pos)
 
#define SYSCFG_EXTICR2_EXTI5   SYSCFG_EXTICR2_EXTI5_Msk
 
#define SYSCFG_EXTICR2_EXTI6_Pos   (8U)
 
#define SYSCFG_EXTICR2_EXTI6_Msk   (0xFU << SYSCFG_EXTICR2_EXTI6_Pos)
 
#define SYSCFG_EXTICR2_EXTI6   SYSCFG_EXTICR2_EXTI6_Msk
 
#define SYSCFG_EXTICR2_EXTI7_Pos   (12U)
 
#define SYSCFG_EXTICR2_EXTI7_Msk   (0xFU << SYSCFG_EXTICR2_EXTI7_Pos)
 
#define SYSCFG_EXTICR2_EXTI7   SYSCFG_EXTICR2_EXTI7_Msk
 
#define SYSCFG_EXTICR2_EXTI4_PA   (0x00000000U)
 EXTI4 configuration

More...
 
#define SYSCFG_EXTICR2_EXTI4_PB   (0x00000001U)
 
#define SYSCFG_EXTICR2_EXTI4_PC   (0x00000002U)
 
#define SYSCFG_EXTICR2_EXTI4_PD   (0x00000003U)
 
#define SYSCFG_EXTICR2_EXTI4_PE   (0x00000004U)
 
#define SYSCFG_EXTICR2_EXTI4_PF   (0x00000006U)
 
#define SYSCFG_EXTICR2_EXTI4_PG   (0x00000007U)
 
#define SYSCFG_EXTICR2_EXTI5_PA   (0x00000000U)
 EXTI5 configuration

More...
 
#define SYSCFG_EXTICR2_EXTI5_PB   (0x00000010U)
 
#define SYSCFG_EXTICR2_EXTI5_PC   (0x00000020U)
 
#define SYSCFG_EXTICR2_EXTI5_PD   (0x00000030U)
 
#define SYSCFG_EXTICR2_EXTI5_PE   (0x00000040U)
 
#define SYSCFG_EXTICR2_EXTI5_PF   (0x00000060U)
 
#define SYSCFG_EXTICR2_EXTI5_PG   (0x00000070U)
 
#define SYSCFG_EXTICR2_EXTI6_PA   (0x00000000U)
 EXTI6 configuration

More...
 
#define SYSCFG_EXTICR2_EXTI6_PB   (0x00000100U)
 
#define SYSCFG_EXTICR2_EXTI6_PC   (0x00000200U)
 
#define SYSCFG_EXTICR2_EXTI6_PD   (0x00000300U)
 
#define SYSCFG_EXTICR2_EXTI6_PE   (0x00000400U)
 
#define SYSCFG_EXTICR2_EXTI6_PF   (0x00000600U)
 
#define SYSCFG_EXTICR2_EXTI6_PG   (0x00000700U)
 
#define SYSCFG_EXTICR2_EXTI7_PA   (0x00000000U)
 EXTI7 configuration

More...
 
#define SYSCFG_EXTICR2_EXTI7_PB   (0x00001000U)
 
#define SYSCFG_EXTICR2_EXTI7_PC   (0x00002000U)
 
#define SYSCFG_EXTICR2_EXTI7_PD   (0x00003000U)
 
#define SYSCFG_EXTICR2_EXTI7_PE   (0x00004000U)
 
#define SYSCFG_EXTICR2_EXTI7_PF   (0x00006000U)
 
#define SYSCFG_EXTICR2_EXTI7_PG   (0x00007000U)
 
#define SYSCFG_EXTICR3_EXTI8_Pos   (0U)
 
#define SYSCFG_EXTICR3_EXTI8_Msk   (0xFU << SYSCFG_EXTICR3_EXTI8_Pos)
 
#define SYSCFG_EXTICR3_EXTI8   SYSCFG_EXTICR3_EXTI8_Msk
 
#define SYSCFG_EXTICR3_EXTI9_Pos   (4U)
 
#define SYSCFG_EXTICR3_EXTI9_Msk   (0xFU << SYSCFG_EXTICR3_EXTI9_Pos)
 
#define SYSCFG_EXTICR3_EXTI9   SYSCFG_EXTICR3_EXTI9_Msk
 
#define SYSCFG_EXTICR3_EXTI10_Pos   (8U)
 
#define SYSCFG_EXTICR3_EXTI10_Msk   (0xFU << SYSCFG_EXTICR3_EXTI10_Pos)
 
#define SYSCFG_EXTICR3_EXTI10   SYSCFG_EXTICR3_EXTI10_Msk
 
#define SYSCFG_EXTICR3_EXTI11_Pos   (12U)
 
#define SYSCFG_EXTICR3_EXTI11_Msk   (0xFU << SYSCFG_EXTICR3_EXTI11_Pos)
 
#define SYSCFG_EXTICR3_EXTI11   SYSCFG_EXTICR3_EXTI11_Msk
 
#define SYSCFG_EXTICR3_EXTI8_PA   (0x00000000U)
 EXTI8 configuration

More...
 
#define SYSCFG_EXTICR3_EXTI8_PB   (0x00000001U)
 
#define SYSCFG_EXTICR3_EXTI8_PC   (0x00000002U)
 
#define SYSCFG_EXTICR3_EXTI8_PD   (0x00000003U)
 
#define SYSCFG_EXTICR3_EXTI8_PE   (0x00000004U)
 
#define SYSCFG_EXTICR3_EXTI8_PF   (0x00000006U)
 
#define SYSCFG_EXTICR3_EXTI8_PG   (0x00000007U)
 
#define SYSCFG_EXTICR3_EXTI9_PA   (0x00000000U)
 EXTI9 configuration

More...
 
#define SYSCFG_EXTICR3_EXTI9_PB   (0x00000010U)
 
#define SYSCFG_EXTICR3_EXTI9_PC   (0x00000020U)
 
#define SYSCFG_EXTICR3_EXTI9_PD   (0x00000030U)
 
#define SYSCFG_EXTICR3_EXTI9_PE   (0x00000040U)
 
#define SYSCFG_EXTICR3_EXTI9_PF   (0x00000060U)
 
#define SYSCFG_EXTICR3_EXTI9_PG   (0x00000070U)
 
#define SYSCFG_EXTICR3_EXTI10_PA   (0x00000000U)
 EXTI10 configuration

More...
 
#define SYSCFG_EXTICR3_EXTI10_PB   (0x00000100U)
 
#define SYSCFG_EXTICR3_EXTI10_PC   (0x00000200U)
 
#define SYSCFG_EXTICR3_EXTI10_PD   (0x00000300U)
 
#define SYSCFG_EXTICR3_EXTI10_PE   (0x00000400U)
 
#define SYSCFG_EXTICR3_EXTI10_PF   (0x00000600U)
 
#define SYSCFG_EXTICR3_EXTI10_PG   (0x00000700U)
 
#define SYSCFG_EXTICR3_EXTI11_PA   (0x00000000U)
 EXTI11 configuration

More...
 
#define SYSCFG_EXTICR3_EXTI11_PB   (0x00001000U)
 
#define SYSCFG_EXTICR3_EXTI11_PC   (0x00002000U)
 
#define SYSCFG_EXTICR3_EXTI11_PD   (0x00003000U)
 
#define SYSCFG_EXTICR3_EXTI11_PE   (0x00004000U)
 
#define SYSCFG_EXTICR3_EXTI11_PF   (0x00006000U)
 
#define SYSCFG_EXTICR3_EXTI11_PG   (0x00007000U)
 
#define SYSCFG_EXTICR4_EXTI12_Pos   (0U)
 
#define SYSCFG_EXTICR4_EXTI12_Msk   (0xFU << SYSCFG_EXTICR4_EXTI12_Pos)
 
#define SYSCFG_EXTICR4_EXTI12   SYSCFG_EXTICR4_EXTI12_Msk
 
#define SYSCFG_EXTICR4_EXTI13_Pos   (4U)
 
#define SYSCFG_EXTICR4_EXTI13_Msk   (0xFU << SYSCFG_EXTICR4_EXTI13_Pos)
 
#define SYSCFG_EXTICR4_EXTI13   SYSCFG_EXTICR4_EXTI13_Msk
 
#define SYSCFG_EXTICR4_EXTI14_Pos   (8U)
 
#define SYSCFG_EXTICR4_EXTI14_Msk   (0xFU << SYSCFG_EXTICR4_EXTI14_Pos)
 
#define SYSCFG_EXTICR4_EXTI14   SYSCFG_EXTICR4_EXTI14_Msk
 
#define SYSCFG_EXTICR4_EXTI15_Pos   (12U)
 
#define SYSCFG_EXTICR4_EXTI15_Msk   (0xFU << SYSCFG_EXTICR4_EXTI15_Pos)
 
#define SYSCFG_EXTICR4_EXTI15   SYSCFG_EXTICR4_EXTI15_Msk
 
#define SYSCFG_EXTICR4_EXTI12_PA   (0x00000000U)
 EXTI12 configuration

More...
 
#define SYSCFG_EXTICR4_EXTI12_PB   (0x00000001U)
 
#define SYSCFG_EXTICR4_EXTI12_PC   (0x00000002U)
 
#define SYSCFG_EXTICR4_EXTI12_PD   (0x00000003U)
 
#define SYSCFG_EXTICR4_EXTI12_PE   (0x00000004U)
 
#define SYSCFG_EXTICR4_EXTI12_PF   (0x00000006U)
 
#define SYSCFG_EXTICR4_EXTI12_PG   (0x00000007U)
 
#define SYSCFG_EXTICR4_EXTI13_PA   (0x00000000U)
 EXTI13 configuration

More...
 
#define SYSCFG_EXTICR4_EXTI13_PB   (0x00000010U)
 
#define SYSCFG_EXTICR4_EXTI13_PC   (0x00000020U)
 
#define SYSCFG_EXTICR4_EXTI13_PD   (0x00000030U)
 
#define SYSCFG_EXTICR4_EXTI13_PE   (0x00000040U)
 
#define SYSCFG_EXTICR4_EXTI13_PF   (0x00000060U)
 
#define SYSCFG_EXTICR4_EXTI13_PG   (0x00000070U)
 
#define SYSCFG_EXTICR4_EXTI14_PA   (0x00000000U)
 EXTI14 configuration

More...
 
#define SYSCFG_EXTICR4_EXTI14_PB   (0x00000100U)
 
#define SYSCFG_EXTICR4_EXTI14_PC   (0x00000200U)
 
#define SYSCFG_EXTICR4_EXTI14_PD   (0x00000300U)
 
#define SYSCFG_EXTICR4_EXTI14_PE   (0x00000400U)
 
#define SYSCFG_EXTICR4_EXTI14_PF   (0x00000600U)
 
#define SYSCFG_EXTICR4_EXTI14_PG   (0x00000700U)
 
#define SYSCFG_EXTICR4_EXTI15_PA   (0x00000000U)
 EXTI15 configuration

More...
 
#define SYSCFG_EXTICR4_EXTI15_PB   (0x00001000U)
 
#define SYSCFG_EXTICR4_EXTI15_PC   (0x00002000U)
 
#define SYSCFG_EXTICR4_EXTI15_PD   (0x00003000U)
 
#define SYSCFG_EXTICR4_EXTI15_PE   (0x00004000U)
 
#define SYSCFG_EXTICR4_EXTI15_PF   (0x00006000U)
 
#define SYSCFG_EXTICR4_EXTI15_PG   (0x00007000U)
 
#define RI_ICR_IC1OS_Pos   (0U)
 
#define RI_ICR_IC1OS_Msk   (0xFU << RI_ICR_IC1OS_Pos)
 
#define RI_ICR_IC1OS   RI_ICR_IC1OS_Msk
 
#define RI_ICR_IC1OS_0   (0x1U << RI_ICR_IC1OS_Pos)
 
#define RI_ICR_IC1OS_1   (0x2U << RI_ICR_IC1OS_Pos)
 
#define RI_ICR_IC1OS_2   (0x4U << RI_ICR_IC1OS_Pos)
 
#define RI_ICR_IC1OS_3   (0x8U << RI_ICR_IC1OS_Pos)
 
#define RI_ICR_IC2OS_Pos   (4U)
 
#define RI_ICR_IC2OS_Msk   (0xFU << RI_ICR_IC2OS_Pos)
 
#define RI_ICR_IC2OS   RI_ICR_IC2OS_Msk
 
#define RI_ICR_IC2OS_0   (0x1U << RI_ICR_IC2OS_Pos)
 
#define RI_ICR_IC2OS_1   (0x2U << RI_ICR_IC2OS_Pos)
 
#define RI_ICR_IC2OS_2   (0x4U << RI_ICR_IC2OS_Pos)
 
#define RI_ICR_IC2OS_3   (0x8U << RI_ICR_IC2OS_Pos)
 
#define RI_ICR_IC3OS_Pos   (8U)
 
#define RI_ICR_IC3OS_Msk   (0xFU << RI_ICR_IC3OS_Pos)
 
#define RI_ICR_IC3OS   RI_ICR_IC3OS_Msk
 
#define RI_ICR_IC3OS_0   (0x1U << RI_ICR_IC3OS_Pos)
 
#define RI_ICR_IC3OS_1   (0x2U << RI_ICR_IC3OS_Pos)
 
#define RI_ICR_IC3OS_2   (0x4U << RI_ICR_IC3OS_Pos)
 
#define RI_ICR_IC3OS_3   (0x8U << RI_ICR_IC3OS_Pos)
 
#define RI_ICR_IC4OS_Pos   (12U)
 
#define RI_ICR_IC4OS_Msk   (0xFU << RI_ICR_IC4OS_Pos)
 
#define RI_ICR_IC4OS   RI_ICR_IC4OS_Msk
 
#define RI_ICR_IC4OS_0   (0x1U << RI_ICR_IC4OS_Pos)
 
#define RI_ICR_IC4OS_1   (0x2U << RI_ICR_IC4OS_Pos)
 
#define RI_ICR_IC4OS_2   (0x4U << RI_ICR_IC4OS_Pos)
 
#define RI_ICR_IC4OS_3   (0x8U << RI_ICR_IC4OS_Pos)
 
#define RI_ICR_TIM_Pos   (16U)
 
#define RI_ICR_TIM_Msk   (0x3U << RI_ICR_TIM_Pos)
 
#define RI_ICR_TIM   RI_ICR_TIM_Msk
 
#define RI_ICR_TIM_0   (0x1U << RI_ICR_TIM_Pos)
 
#define RI_ICR_TIM_1   (0x2U << RI_ICR_TIM_Pos)
 
#define RI_ICR_IC1_Pos   (18U)
 
#define RI_ICR_IC1_Msk   (0x1U << RI_ICR_IC1_Pos)
 
#define RI_ICR_IC1   RI_ICR_IC1_Msk
 
#define RI_ICR_IC2_Pos   (19U)
 
#define RI_ICR_IC2_Msk   (0x1U << RI_ICR_IC2_Pos)
 
#define RI_ICR_IC2   RI_ICR_IC2_Msk
 
#define RI_ICR_IC3_Pos   (20U)
 
#define RI_ICR_IC3_Msk   (0x1U << RI_ICR_IC3_Pos)
 
#define RI_ICR_IC3   RI_ICR_IC3_Msk
 
#define RI_ICR_IC4_Pos   (21U)
 
#define RI_ICR_IC4_Msk   (0x1U << RI_ICR_IC4_Pos)
 
#define RI_ICR_IC4   RI_ICR_IC4_Msk
 
#define RI_ASCR1_CH_Pos   (0U)
 
#define RI_ASCR1_CH_Msk   (0x7BFDFFFFU << RI_ASCR1_CH_Pos)
 
#define RI_ASCR1_CH   RI_ASCR1_CH_Msk
 
#define RI_ASCR1_CH_0   (0x00000001U)
 
#define RI_ASCR1_CH_1   (0x00000002U)
 
#define RI_ASCR1_CH_2   (0x00000004U)
 
#define RI_ASCR1_CH_3   (0x00000008U)
 
#define RI_ASCR1_CH_4   (0x00000010U)
 
#define RI_ASCR1_CH_5   (0x00000020U)
 
#define RI_ASCR1_CH_6   (0x00000040U)
 
#define RI_ASCR1_CH_7   (0x00000080U)
 
#define RI_ASCR1_CH_8   (0x00000100U)
 
#define RI_ASCR1_CH_9   (0x00000200U)
 
#define RI_ASCR1_CH_10   (0x00000400U)
 
#define RI_ASCR1_CH_11   (0x00000800U)
 
#define RI_ASCR1_CH_12   (0x00001000U)
 
#define RI_ASCR1_CH_13   (0x00002000U)
 
#define RI_ASCR1_CH_14   (0x00004000U)
 
#define RI_ASCR1_CH_15   (0x00008000U)
 
#define RI_ASCR1_CH_31   (0x00010000U)
 
#define RI_ASCR1_CH_18   (0x00040000U)
 
#define RI_ASCR1_CH_19   (0x00080000U)
 
#define RI_ASCR1_CH_20   (0x00100000U)
 
#define RI_ASCR1_CH_21   (0x00200000U)
 
#define RI_ASCR1_CH_22   (0x00400000U)
 
#define RI_ASCR1_CH_23   (0x00800000U)
 
#define RI_ASCR1_CH_24   (0x01000000U)
 
#define RI_ASCR1_CH_25   (0x02000000U)
 
#define RI_ASCR1_VCOMP_Pos   (26U)
 
#define RI_ASCR1_VCOMP_Msk   (0x1U << RI_ASCR1_VCOMP_Pos)
 
#define RI_ASCR1_VCOMP   RI_ASCR1_VCOMP_Msk
 
#define RI_ASCR1_CH_27   (0x08000000U)
 
#define RI_ASCR1_CH_28   (0x10000000U)
 
#define RI_ASCR1_CH_29   (0x20000000U)
 
#define RI_ASCR1_CH_30   (0x40000000U)
 
#define RI_ASCR1_SCM_Pos   (31U)
 
#define RI_ASCR1_SCM_Msk   (0x1U << RI_ASCR1_SCM_Pos)
 
#define RI_ASCR1_SCM   RI_ASCR1_SCM_Msk
 
#define RI_ASCR2_GR10_1   (0x00000001U)
 
#define RI_ASCR2_GR10_2   (0x00000002U)
 
#define RI_ASCR2_GR10_3   (0x00000004U)
 
#define RI_ASCR2_GR10_4   (0x00000008U)
 
#define RI_ASCR2_GR6_Pos   (4U)
 
#define RI_ASCR2_GR6_Msk   (0x1800003U << RI_ASCR2_GR6_Pos)
 
#define RI_ASCR2_GR6   RI_ASCR2_GR6_Msk
 
#define RI_ASCR2_GR6_1   (0x0000001U << RI_ASCR2_GR6_Pos)
 
#define RI_ASCR2_GR6_2   (0x0000002U << RI_ASCR2_GR6_Pos)
 
#define RI_ASCR2_GR6_3   (0x0800000U << RI_ASCR2_GR6_Pos)
 
#define RI_ASCR2_GR6_4   (0x1000000U << RI_ASCR2_GR6_Pos)
 
#define RI_ASCR2_GR5_1   (0x00000040U)
 
#define RI_ASCR2_GR5_2   (0x00000080U)
 
#define RI_ASCR2_GR5_3   (0x00000100U)
 
#define RI_ASCR2_GR4_1   (0x00000200U)
 
#define RI_ASCR2_GR4_2   (0x00000400U)
 
#define RI_ASCR2_GR4_3   (0x00000800U)
 
#define RI_ASCR2_GR4_4   (0x00008000U)
 
#define RI_ASCR2_CH0b_Pos   (16U)
 
#define RI_ASCR2_CH0b_Msk   (0x1U << RI_ASCR2_CH0b_Pos)
 
#define RI_ASCR2_CH0b   RI_ASCR2_CH0b_Msk
 
#define RI_ASCR2_CH1b_Pos   (17U)
 
#define RI_ASCR2_CH1b_Msk   (0x1U << RI_ASCR2_CH1b_Pos)
 
#define RI_ASCR2_CH1b   RI_ASCR2_CH1b_Msk
 
#define RI_ASCR2_CH2b_Pos   (18U)
 
#define RI_ASCR2_CH2b_Msk   (0x1U << RI_ASCR2_CH2b_Pos)
 
#define RI_ASCR2_CH2b   RI_ASCR2_CH2b_Msk
 
#define RI_ASCR2_CH3b_Pos   (19U)
 
#define RI_ASCR2_CH3b_Msk   (0x1U << RI_ASCR2_CH3b_Pos)
 
#define RI_ASCR2_CH3b   RI_ASCR2_CH3b_Msk
 
#define RI_ASCR2_CH6b_Pos   (20U)
 
#define RI_ASCR2_CH6b_Msk   (0x1U << RI_ASCR2_CH6b_Pos)
 
#define RI_ASCR2_CH6b   RI_ASCR2_CH6b_Msk
 
#define RI_ASCR2_CH7b_Pos   (21U)
 
#define RI_ASCR2_CH7b_Msk   (0x1U << RI_ASCR2_CH7b_Pos)
 
#define RI_ASCR2_CH7b   RI_ASCR2_CH7b_Msk
 
#define RI_ASCR2_CH8b_Pos   (22U)
 
#define RI_ASCR2_CH8b_Msk   (0x1U << RI_ASCR2_CH8b_Pos)
 
#define RI_ASCR2_CH8b   RI_ASCR2_CH8b_Msk
 
#define RI_ASCR2_CH9b_Pos   (23U)
 
#define RI_ASCR2_CH9b_Msk   (0x1U << RI_ASCR2_CH9b_Pos)
 
#define RI_ASCR2_CH9b   RI_ASCR2_CH9b_Msk
 
#define RI_ASCR2_CH10b_Pos   (24U)
 
#define RI_ASCR2_CH10b_Msk   (0x1U << RI_ASCR2_CH10b_Pos)
 
#define RI_ASCR2_CH10b   RI_ASCR2_CH10b_Msk
 
#define RI_ASCR2_CH11b_Pos   (25U)
 
#define RI_ASCR2_CH11b_Msk   (0x1U << RI_ASCR2_CH11b_Pos)
 
#define RI_ASCR2_CH11b   RI_ASCR2_CH11b_Msk
 
#define RI_ASCR2_CH12b_Pos   (26U)
 
#define RI_ASCR2_CH12b_Msk   (0x1U << RI_ASCR2_CH12b_Pos)
 
#define RI_ASCR2_CH12b   RI_ASCR2_CH12b_Msk
 
#define RI_HYSCR1_PA_Pos   (0U)
 
#define RI_HYSCR1_PA_Msk   (0xFFFFU << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA   RI_HYSCR1_PA_Msk
 
#define RI_HYSCR1_PA_0   (0x0001U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_1   (0x0002U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_2   (0x0004U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_3   (0x0008U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_4   (0x0010U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_5   (0x0020U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_6   (0x0040U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_7   (0x0080U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_8   (0x0100U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_9   (0x0200U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_10   (0x0400U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_11   (0x0800U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_12   (0x1000U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_13   (0x2000U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_14   (0x4000U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PA_15   (0x8000U << RI_HYSCR1_PA_Pos)
 
#define RI_HYSCR1_PB_Pos   (16U)
 
#define RI_HYSCR1_PB_Msk   (0xFFFFU << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB   RI_HYSCR1_PB_Msk
 
#define RI_HYSCR1_PB_0   (0x0001U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_1   (0x0002U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_2   (0x0004U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_3   (0x0008U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_4   (0x0010U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_5   (0x0020U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_6   (0x0040U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_7   (0x0080U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_8   (0x0100U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_9   (0x0200U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_10   (0x0400U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_11   (0x0800U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_12   (0x1000U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_13   (0x2000U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_14   (0x4000U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR1_PB_15   (0x8000U << RI_HYSCR1_PB_Pos)
 
#define RI_HYSCR2_PC_Pos   (0U)
 
#define RI_HYSCR2_PC_Msk   (0xFFFFU << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC   RI_HYSCR2_PC_Msk
 
#define RI_HYSCR2_PC_0   (0x0001U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_1   (0x0002U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_2   (0x0004U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_3   (0x0008U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_4   (0x0010U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_5   (0x0020U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_6   (0x0040U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_7   (0x0080U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_8   (0x0100U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_9   (0x0200U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_10   (0x0400U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_11   (0x0800U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_12   (0x1000U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_13   (0x2000U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_14   (0x4000U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PC_15   (0x8000U << RI_HYSCR2_PC_Pos)
 
#define RI_HYSCR2_PD_Pos   (16U)
 
#define RI_HYSCR2_PD_Msk   (0xFFFFU << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD   RI_HYSCR2_PD_Msk
 
#define RI_HYSCR2_PD_0   (0x0001U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_1   (0x0002U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_2   (0x0004U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_3   (0x0008U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_4   (0x0010U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_5   (0x0020U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_6   (0x0040U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_7   (0x0080U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_8   (0x0100U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_9   (0x0200U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_10   (0x0400U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_11   (0x0800U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_12   (0x1000U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_13   (0x2000U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_14   (0x4000U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR2_PD_15   (0x8000U << RI_HYSCR2_PD_Pos)
 
#define RI_HYSCR3_PE_Pos   (0U)
 
#define RI_HYSCR3_PE_Msk   (0xFFFFU << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE   RI_HYSCR3_PE_Msk
 
#define RI_HYSCR3_PE_0   (0x0001U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_1   (0x0002U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_2   (0x0004U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_3   (0x0008U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_4   (0x0010U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_5   (0x0020U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_6   (0x0040U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_7   (0x0080U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_8   (0x0100U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_9   (0x0200U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_10   (0x0400U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_11   (0x0800U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_12   (0x1000U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_13   (0x2000U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_14   (0x4000U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PE_15   (0x8000U << RI_HYSCR3_PE_Pos)
 
#define RI_HYSCR3_PF_Pos   (16U)
 
#define RI_HYSCR3_PF_Msk   (0xFFFFU << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF   RI_HYSCR3_PF_Msk
 
#define RI_HYSCR3_PF_0   (0x0001U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_1   (0x0002U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_2   (0x0004U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_3   (0x0008U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_4   (0x0010U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_5   (0x0020U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_6   (0x0040U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_7   (0x0080U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_8   (0x0100U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_9   (0x0200U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_10   (0x0400U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_11   (0x0800U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_12   (0x1000U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_13   (0x2000U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_14   (0x4000U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR3_PF_15   (0x8000U << RI_HYSCR3_PF_Pos)
 
#define RI_HYSCR4_PG_Pos   (0U)
 
#define RI_HYSCR4_PG_Msk   (0xFFFFU << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG   RI_HYSCR4_PG_Msk
 
#define RI_HYSCR4_PG_0   (0x0001U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_1   (0x0002U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_2   (0x0004U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_3   (0x0008U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_4   (0x0010U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_5   (0x0020U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_6   (0x0040U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_7   (0x0080U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_8   (0x0100U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_9   (0x0200U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_10   (0x0400U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_11   (0x0800U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_12   (0x1000U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_13   (0x2000U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_14   (0x4000U << RI_HYSCR4_PG_Pos)
 
#define RI_HYSCR4_PG_15   (0x8000U << RI_HYSCR4_PG_Pos)
 
#define RI_ASMR1_PA_Pos   (0U)
 
#define RI_ASMR1_PA_Msk   (0xFFFFU << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA   RI_ASMR1_PA_Msk
 
#define RI_ASMR1_PA_0   (0x0001U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_1   (0x0002U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_2   (0x0004U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_3   (0x0008U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_4   (0x0010U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_5   (0x0020U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_6   (0x0040U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_7   (0x0080U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_8   (0x0100U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_9   (0x0200U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_10   (0x0400U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_11   (0x0800U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_12   (0x1000U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_13   (0x2000U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_14   (0x4000U << RI_ASMR1_PA_Pos)
 
#define RI_ASMR1_PA_15   (0x8000U << RI_ASMR1_PA_Pos)
 
#define RI_CMR1_PA_Pos   (0U)
 
#define RI_CMR1_PA_Msk   (0xFFFFU << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA   RI_CMR1_PA_Msk
 
#define RI_CMR1_PA_0   (0x0001U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_1   (0x0002U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_2   (0x0004U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_3   (0x0008U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_4   (0x0010U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_5   (0x0020U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_6   (0x0040U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_7   (0x0080U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_8   (0x0100U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_9   (0x0200U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_10   (0x0400U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_11   (0x0800U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_12   (0x1000U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_13   (0x2000U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_14   (0x4000U << RI_CMR1_PA_Pos)
 
#define RI_CMR1_PA_15   (0x8000U << RI_CMR1_PA_Pos)
 
#define RI_CICR1_PA_Pos   (0U)
 
#define RI_CICR1_PA_Msk   (0xFFFFU << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA   RI_CICR1_PA_Msk
 
#define RI_CICR1_PA_0   (0x0001U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_1   (0x0002U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_2   (0x0004U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_3   (0x0008U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_4   (0x0010U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_5   (0x0020U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_6   (0x0040U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_7   (0x0080U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_8   (0x0100U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_9   (0x0200U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_10   (0x0400U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_11   (0x0800U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_12   (0x1000U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_13   (0x2000U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_14   (0x4000U << RI_CICR1_PA_Pos)
 
#define RI_CICR1_PA_15   (0x8000U << RI_CICR1_PA_Pos)
 
#define RI_ASMR2_PB_Pos   (0U)
 
#define RI_ASMR2_PB_Msk   (0xFFFFU << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB   RI_ASMR2_PB_Msk
 
#define RI_ASMR2_PB_0   (0x0001U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_1   (0x0002U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_2   (0x0004U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_3   (0x0008U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_4   (0x0010U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_5   (0x0020U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_6   (0x0040U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_7   (0x0080U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_8   (0x0100U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_9   (0x0200U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_10   (0x0400U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_11   (0x0800U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_12   (0x1000U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_13   (0x2000U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_14   (0x4000U << RI_ASMR2_PB_Pos)
 
#define RI_ASMR2_PB_15   (0x8000U << RI_ASMR2_PB_Pos)
 
#define RI_CMR2_PB_Pos   (0U)
 
#define RI_CMR2_PB_Msk   (0xFFFFU << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB   RI_CMR2_PB_Msk
 
#define RI_CMR2_PB_0   (0x0001U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_1   (0x0002U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_2   (0x0004U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_3   (0x0008U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_4   (0x0010U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_5   (0x0020U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_6   (0x0040U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_7   (0x0080U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_8   (0x0100U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_9   (0x0200U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_10   (0x0400U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_11   (0x0800U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_12   (0x1000U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_13   (0x2000U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_14   (0x4000U << RI_CMR2_PB_Pos)
 
#define RI_CMR2_PB_15   (0x8000U << RI_CMR2_PB_Pos)
 
#define RI_CICR2_PB_Pos   (0U)
 
#define RI_CICR2_PB_Msk   (0xFFFFU << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB   RI_CICR2_PB_Msk
 
#define RI_CICR2_PB_0   (0x0001U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_1   (0x0002U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_2   (0x0004U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_3   (0x0008U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_4   (0x0010U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_5   (0x0020U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_6   (0x0040U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_7   (0x0080U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_8   (0x0100U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_9   (0x0200U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_10   (0x0400U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_11   (0x0800U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_12   (0x1000U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_13   (0x2000U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_14   (0x4000U << RI_CICR2_PB_Pos)
 
#define RI_CICR2_PB_15   (0x8000U << RI_CICR2_PB_Pos)
 
#define RI_ASMR3_PC_Pos   (0U)
 
#define RI_ASMR3_PC_Msk   (0xFFFFU << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC   RI_ASMR3_PC_Msk
 
#define RI_ASMR3_PC_0   (0x0001U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_1   (0x0002U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_2   (0x0004U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_3   (0x0008U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_4   (0x0010U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_5   (0x0020U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_6   (0x0040U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_7   (0x0080U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_8   (0x0100U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_9   (0x0200U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_10   (0x0400U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_11   (0x0800U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_12   (0x1000U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_13   (0x2000U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_14   (0x4000U << RI_ASMR3_PC_Pos)
 
#define RI_ASMR3_PC_15   (0x8000U << RI_ASMR3_PC_Pos)
 
#define RI_CMR3_PC_Pos   (0U)
 
#define RI_CMR3_PC_Msk   (0xFFFFU << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC   RI_CMR3_PC_Msk
 
#define RI_CMR3_PC_0   (0x0001U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_1   (0x0002U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_2   (0x0004U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_3   (0x0008U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_4   (0x0010U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_5   (0x0020U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_6   (0x0040U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_7   (0x0080U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_8   (0x0100U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_9   (0x0200U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_10   (0x0400U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_11   (0x0800U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_12   (0x1000U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_13   (0x2000U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_14   (0x4000U << RI_CMR3_PC_Pos)
 
#define RI_CMR3_PC_15   (0x8000U << RI_CMR3_PC_Pos)
 
#define RI_CICR3_PC_Pos   (0U)
 
#define RI_CICR3_PC_Msk   (0xFFFFU << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC   RI_CICR3_PC_Msk
 
#define RI_CICR3_PC_0   (0x0001U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_1   (0x0002U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_2   (0x0004U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_3   (0x0008U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_4   (0x0010U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_5   (0x0020U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_6   (0x0040U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_7   (0x0080U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_8   (0x0100U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_9   (0x0200U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_10   (0x0400U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_11   (0x0800U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_12   (0x1000U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_13   (0x2000U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_14   (0x4000U << RI_CICR3_PC_Pos)
 
#define RI_CICR3_PC_15   (0x8000U << RI_CICR3_PC_Pos)
 
#define RI_ASMR4_PF_Pos   (0U)
 
#define RI_ASMR4_PF_Msk   (0xFFFFU << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF   RI_ASMR4_PF_Msk
 
#define RI_ASMR4_PF_0   (0x0001U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_1   (0x0002U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_2   (0x0004U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_3   (0x0008U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_4   (0x0010U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_5   (0x0020U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_6   (0x0040U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_7   (0x0080U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_8   (0x0100U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_9   (0x0200U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_10   (0x0400U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_11   (0x0800U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_12   (0x1000U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_13   (0x2000U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_14   (0x4000U << RI_ASMR4_PF_Pos)
 
#define RI_ASMR4_PF_15   (0x8000U << RI_ASMR4_PF_Pos)
 
#define RI_CMR4_PF_Pos   (0U)
 
#define RI_CMR4_PF_Msk   (0xFFFFU << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF   RI_CMR4_PF_Msk
 
#define RI_CMR4_PF_0   (0x0001U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_1   (0x0002U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_2   (0x0004U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_3   (0x0008U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_4   (0x0010U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_5   (0x0020U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_6   (0x0040U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_7   (0x0080U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_8   (0x0100U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_9   (0x0200U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_10   (0x0400U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_11   (0x0800U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_12   (0x1000U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_13   (0x2000U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_14   (0x4000U << RI_CMR4_PF_Pos)
 
#define RI_CMR4_PF_15   (0x8000U << RI_CMR4_PF_Pos)
 
#define RI_CICR4_PF_Pos   (0U)
 
#define RI_CICR4_PF_Msk   (0xFFFFU << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF   RI_CICR4_PF_Msk
 
#define RI_CICR4_PF_0   (0x0001U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_1   (0x0002U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_2   (0x0004U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_3   (0x0008U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_4   (0x0010U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_5   (0x0020U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_6   (0x0040U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_7   (0x0080U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_8   (0x0100U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_9   (0x0200U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_10   (0x0400U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_11   (0x0800U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_12   (0x1000U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_13   (0x2000U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_14   (0x4000U << RI_CICR4_PF_Pos)
 
#define RI_CICR4_PF_15   (0x8000U << RI_CICR4_PF_Pos)
 
#define RI_ASMR5_PG_Pos   (0U)
 
#define RI_ASMR5_PG_Msk   (0xFFFFU << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG   RI_ASMR5_PG_Msk
 
#define RI_ASMR5_PG_0   (0x0001U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_1   (0x0002U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_2   (0x0004U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_3   (0x0008U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_4   (0x0010U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_5   (0x0020U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_6   (0x0040U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_7   (0x0080U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_8   (0x0100U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_9   (0x0200U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_10   (0x0400U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_11   (0x0800U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_12   (0x1000U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_13   (0x2000U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_14   (0x4000U << RI_ASMR5_PG_Pos)
 
#define RI_ASMR5_PG_15   (0x8000U << RI_ASMR5_PG_Pos)
 
#define RI_CMR5_PG_Pos   (0U)
 
#define RI_CMR5_PG_Msk   (0xFFFFU << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG   RI_CMR5_PG_Msk
 
#define RI_CMR5_PG_0   (0x0001U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_1   (0x0002U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_2   (0x0004U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_3   (0x0008U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_4   (0x0010U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_5   (0x0020U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_6   (0x0040U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_7   (0x0080U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_8   (0x0100U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_9   (0x0200U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_10   (0x0400U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_11   (0x0800U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_12   (0x1000U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_13   (0x2000U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_14   (0x4000U << RI_CMR5_PG_Pos)
 
#define RI_CMR5_PG_15   (0x8000U << RI_CMR5_PG_Pos)
 
#define RI_CICR5_PG_Pos   (0U)
 
#define RI_CICR5_PG_Msk   (0xFFFFU << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG   RI_CICR5_PG_Msk
 
#define RI_CICR5_PG_0   (0x0001U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_1   (0x0002U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_2   (0x0004U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_3   (0x0008U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_4   (0x0010U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_5   (0x0020U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_6   (0x0040U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_7   (0x0080U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_8   (0x0100U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_9   (0x0200U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_10   (0x0400U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_11   (0x0800U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_12   (0x1000U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_13   (0x2000U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_14   (0x4000U << RI_CICR5_PG_Pos)
 
#define RI_CICR5_PG_15   (0x8000U << RI_CICR5_PG_Pos)
 
#define TIM_CR1_CEN_Pos   (0U)
 
#define TIM_CR1_CEN_Msk   (0x1U << TIM_CR1_CEN_Pos)
 
#define TIM_CR1_CEN   TIM_CR1_CEN_Msk
 
#define TIM_CR1_UDIS_Pos   (1U)
 
#define TIM_CR1_UDIS_Msk   (0x1U << TIM_CR1_UDIS_Pos)
 
#define TIM_CR1_UDIS   TIM_CR1_UDIS_Msk
 
#define TIM_CR1_URS_Pos   (2U)
 
#define TIM_CR1_URS_Msk   (0x1U << TIM_CR1_URS_Pos)
 
#define TIM_CR1_URS   TIM_CR1_URS_Msk
 
#define TIM_CR1_OPM_Pos   (3U)
 
#define TIM_CR1_OPM_Msk   (0x1U << TIM_CR1_OPM_Pos)
 
#define TIM_CR1_OPM   TIM_CR1_OPM_Msk
 
#define TIM_CR1_DIR_Pos   (4U)
 
#define TIM_CR1_DIR_Msk   (0x1U << TIM_CR1_DIR_Pos)
 
#define TIM_CR1_DIR   TIM_CR1_DIR_Msk
 
#define TIM_CR1_CMS_Pos   (5U)
 
#define TIM_CR1_CMS_Msk   (0x3U << TIM_CR1_CMS_Pos)
 
#define TIM_CR1_CMS   TIM_CR1_CMS_Msk
 
#define TIM_CR1_CMS_0   (0x1U << TIM_CR1_CMS_Pos)
 
#define TIM_CR1_CMS_1   (0x2U << TIM_CR1_CMS_Pos)
 
#define TIM_CR1_ARPE_Pos   (7U)
 
#define TIM_CR1_ARPE_Msk   (0x1U << TIM_CR1_ARPE_Pos)
 
#define TIM_CR1_ARPE   TIM_CR1_ARPE_Msk
 
#define TIM_CR1_CKD_Pos   (8U)
 
#define TIM_CR1_CKD_Msk   (0x3U << TIM_CR1_CKD_Pos)
 
#define TIM_CR1_CKD   TIM_CR1_CKD_Msk
 
#define TIM_CR1_CKD_0   (0x1U << TIM_CR1_CKD_Pos)
 
#define TIM_CR1_CKD_1   (0x2U << TIM_CR1_CKD_Pos)
 
#define TIM_CR2_CCDS_Pos   (3U)
 
#define TIM_CR2_CCDS_Msk   (0x1U << TIM_CR2_CCDS_Pos)
 
#define TIM_CR2_CCDS   TIM_CR2_CCDS_Msk
 
#define TIM_CR2_MMS_Pos   (4U)
 
#define TIM_CR2_MMS_Msk   (0x7U << TIM_CR2_MMS_Pos)
 
#define TIM_CR2_MMS   TIM_CR2_MMS_Msk
 
#define TIM_CR2_MMS_0   (0x1U << TIM_CR2_MMS_Pos)
 
#define TIM_CR2_MMS_1   (0x2U << TIM_CR2_MMS_Pos)
 
#define TIM_CR2_MMS_2   (0x4U << TIM_CR2_MMS_Pos)
 
#define TIM_CR2_TI1S_Pos   (7U)
 
#define TIM_CR2_TI1S_Msk   (0x1U << TIM_CR2_TI1S_Pos)
 
#define TIM_CR2_TI1S   TIM_CR2_TI1S_Msk
 
#define TIM_SMCR_SMS_Pos   (0U)
 
#define TIM_SMCR_SMS_Msk   (0x7U << TIM_SMCR_SMS_Pos)
 
#define TIM_SMCR_SMS   TIM_SMCR_SMS_Msk
 
#define TIM_SMCR_SMS_0   (0x1U << TIM_SMCR_SMS_Pos)
 
#define TIM_SMCR_SMS_1   (0x2U << TIM_SMCR_SMS_Pos)
 
#define TIM_SMCR_SMS_2   (0x4U << TIM_SMCR_SMS_Pos)
 
#define TIM_SMCR_OCCS_Pos   (3U)
 
#define TIM_SMCR_OCCS_Msk   (0x1U << TIM_SMCR_OCCS_Pos)
 
#define TIM_SMCR_OCCS   TIM_SMCR_OCCS_Msk
 
#define TIM_SMCR_TS_Pos   (4U)
 
#define TIM_SMCR_TS_Msk   (0x7U << TIM_SMCR_TS_Pos)
 
#define TIM_SMCR_TS   TIM_SMCR_TS_Msk
 
#define TIM_SMCR_TS_0   (0x1U << TIM_SMCR_TS_Pos)
 
#define TIM_SMCR_TS_1   (0x2U << TIM_SMCR_TS_Pos)
 
#define TIM_SMCR_TS_2   (0x4U << TIM_SMCR_TS_Pos)
 
#define TIM_SMCR_MSM_Pos   (7U)
 
#define TIM_SMCR_MSM_Msk   (0x1U << TIM_SMCR_MSM_Pos)
 
#define TIM_SMCR_MSM   TIM_SMCR_MSM_Msk
 
#define TIM_SMCR_ETF_Pos   (8U)
 
#define TIM_SMCR_ETF_Msk   (0xFU << TIM_SMCR_ETF_Pos)
 
#define TIM_SMCR_ETF   TIM_SMCR_ETF_Msk
 
#define TIM_SMCR_ETF_0   (0x1U << TIM_SMCR_ETF_Pos)
 
#define TIM_SMCR_ETF_1   (0x2U << TIM_SMCR_ETF_Pos)
 
#define TIM_SMCR_ETF_2   (0x4U << TIM_SMCR_ETF_Pos)
 
#define TIM_SMCR_ETF_3   (0x8U << TIM_SMCR_ETF_Pos)
 
#define TIM_SMCR_ETPS_Pos   (12U)
 
#define TIM_SMCR_ETPS_Msk   (0x3U << TIM_SMCR_ETPS_Pos)
 
#define TIM_SMCR_ETPS   TIM_SMCR_ETPS_Msk
 
#define TIM_SMCR_ETPS_0   (0x1U << TIM_SMCR_ETPS_Pos)
 
#define TIM_SMCR_ETPS_1   (0x2U << TIM_SMCR_ETPS_Pos)
 
#define TIM_SMCR_ECE_Pos   (14U)
 
#define TIM_SMCR_ECE_Msk   (0x1U << TIM_SMCR_ECE_Pos)
 
#define TIM_SMCR_ECE   TIM_SMCR_ECE_Msk
 
#define TIM_SMCR_ETP_Pos   (15U)
 
#define TIM_SMCR_ETP_Msk   (0x1U << TIM_SMCR_ETP_Pos)
 
#define TIM_SMCR_ETP   TIM_SMCR_ETP_Msk
 
#define TIM_DIER_UIE_Pos   (0U)
 
#define TIM_DIER_UIE_Msk   (0x1U << TIM_DIER_UIE_Pos)
 
#define TIM_DIER_UIE   TIM_DIER_UIE_Msk
 
#define TIM_DIER_CC1IE_Pos   (1U)
 
#define TIM_DIER_CC1IE_Msk   (0x1U << TIM_DIER_CC1IE_Pos)
 
#define TIM_DIER_CC1IE   TIM_DIER_CC1IE_Msk
 
#define TIM_DIER_CC2IE_Pos   (2U)
 
#define TIM_DIER_CC2IE_Msk   (0x1U << TIM_DIER_CC2IE_Pos)
 
#define TIM_DIER_CC2IE   TIM_DIER_CC2IE_Msk
 
#define TIM_DIER_CC3IE_Pos   (3U)
 
#define TIM_DIER_CC3IE_Msk   (0x1U << TIM_DIER_CC3IE_Pos)
 
#define TIM_DIER_CC3IE   TIM_DIER_CC3IE_Msk
 
#define TIM_DIER_CC4IE_Pos   (4U)
 
#define TIM_DIER_CC4IE_Msk   (0x1U << TIM_DIER_CC4IE_Pos)
 
#define TIM_DIER_CC4IE   TIM_DIER_CC4IE_Msk
 
#define TIM_DIER_TIE_Pos   (6U)
 
#define TIM_DIER_TIE_Msk   (0x1U << TIM_DIER_TIE_Pos)
 
#define TIM_DIER_TIE   TIM_DIER_TIE_Msk
 
#define TIM_DIER_UDE_Pos   (8U)
 
#define TIM_DIER_UDE_Msk   (0x1U << TIM_DIER_UDE_Pos)
 
#define TIM_DIER_UDE   TIM_DIER_UDE_Msk
 
#define TIM_DIER_CC1DE_Pos   (9U)
 
#define TIM_DIER_CC1DE_Msk   (0x1U << TIM_DIER_CC1DE_Pos)
 
#define TIM_DIER_CC1DE   TIM_DIER_CC1DE_Msk
 
#define TIM_DIER_CC2DE_Pos   (10U)
 
#define TIM_DIER_CC2DE_Msk   (0x1U << TIM_DIER_CC2DE_Pos)
 
#define TIM_DIER_CC2DE   TIM_DIER_CC2DE_Msk
 
#define TIM_DIER_CC3DE_Pos   (11U)
 
#define TIM_DIER_CC3DE_Msk   (0x1U << TIM_DIER_CC3DE_Pos)
 
#define TIM_DIER_CC3DE   TIM_DIER_CC3DE_Msk
 
#define TIM_DIER_CC4DE_Pos   (12U)
 
#define TIM_DIER_CC4DE_Msk   (0x1U << TIM_DIER_CC4DE_Pos)
 
#define TIM_DIER_CC4DE   TIM_DIER_CC4DE_Msk
 
#define TIM_DIER_COMDE   ((uint16_t)0x2000U)
 
#define TIM_DIER_TDE_Pos   (14U)
 
#define TIM_DIER_TDE_Msk   (0x1U << TIM_DIER_TDE_Pos)
 
#define TIM_DIER_TDE   TIM_DIER_TDE_Msk
 
#define TIM_SR_UIF_Pos   (0U)
 
#define TIM_SR_UIF_Msk   (0x1U << TIM_SR_UIF_Pos)
 
#define TIM_SR_UIF   TIM_SR_UIF_Msk
 
#define TIM_SR_CC1IF_Pos   (1U)
 
#define TIM_SR_CC1IF_Msk   (0x1U << TIM_SR_CC1IF_Pos)
 
#define TIM_SR_CC1IF   TIM_SR_CC1IF_Msk
 
#define TIM_SR_CC2IF_Pos   (2U)
 
#define TIM_SR_CC2IF_Msk   (0x1U << TIM_SR_CC2IF_Pos)
 
#define TIM_SR_CC2IF   TIM_SR_CC2IF_Msk
 
#define TIM_SR_CC3IF_Pos   (3U)
 
#define TIM_SR_CC3IF_Msk   (0x1U << TIM_SR_CC3IF_Pos)
 
#define TIM_SR_CC3IF   TIM_SR_CC3IF_Msk
 
#define TIM_SR_CC4IF_Pos   (4U)
 
#define TIM_SR_CC4IF_Msk   (0x1U << TIM_SR_CC4IF_Pos)
 
#define TIM_SR_CC4IF   TIM_SR_CC4IF_Msk
 
#define TIM_SR_TIF_Pos   (6U)
 
#define TIM_SR_TIF_Msk   (0x1U << TIM_SR_TIF_Pos)
 
#define TIM_SR_TIF   TIM_SR_TIF_Msk
 
#define TIM_SR_CC1OF_Pos   (9U)
 
#define TIM_SR_CC1OF_Msk   (0x1U << TIM_SR_CC1OF_Pos)
 
#define TIM_SR_CC1OF   TIM_SR_CC1OF_Msk
 
#define TIM_SR_CC2OF_Pos   (10U)
 
#define TIM_SR_CC2OF_Msk   (0x1U << TIM_SR_CC2OF_Pos)
 
#define TIM_SR_CC2OF   TIM_SR_CC2OF_Msk
 
#define TIM_SR_CC3OF_Pos   (11U)
 
#define TIM_SR_CC3OF_Msk   (0x1U << TIM_SR_CC3OF_Pos)
 
#define TIM_SR_CC3OF   TIM_SR_CC3OF_Msk
 
#define TIM_SR_CC4OF_Pos   (12U)
 
#define TIM_SR_CC4OF_Msk   (0x1U << TIM_SR_CC4OF_Pos)
 
#define TIM_SR_CC4OF   TIM_SR_CC4OF_Msk
 
#define TIM_EGR_UG_Pos   (0U)
 
#define TIM_EGR_UG_Msk   (0x1U << TIM_EGR_UG_Pos)
 
#define TIM_EGR_UG   TIM_EGR_UG_Msk
 
#define TIM_EGR_CC1G_Pos   (1U)
 
#define TIM_EGR_CC1G_Msk   (0x1U << TIM_EGR_CC1G_Pos)
 
#define TIM_EGR_CC1G   TIM_EGR_CC1G_Msk
 
#define TIM_EGR_CC2G_Pos   (2U)
 
#define TIM_EGR_CC2G_Msk   (0x1U << TIM_EGR_CC2G_Pos)
 
#define TIM_EGR_CC2G   TIM_EGR_CC2G_Msk
 
#define TIM_EGR_CC3G_Pos   (3U)
 
#define TIM_EGR_CC3G_Msk   (0x1U << TIM_EGR_CC3G_Pos)
 
#define TIM_EGR_CC3G   TIM_EGR_CC3G_Msk
 
#define TIM_EGR_CC4G_Pos   (4U)
 
#define TIM_EGR_CC4G_Msk   (0x1U << TIM_EGR_CC4G_Pos)
 
#define TIM_EGR_CC4G   TIM_EGR_CC4G_Msk
 
#define TIM_EGR_TG_Pos   (6U)
 
#define TIM_EGR_TG_Msk   (0x1U << TIM_EGR_TG_Pos)
 
#define TIM_EGR_TG   TIM_EGR_TG_Msk
 
#define TIM_CCMR1_CC1S_Pos   (0U)
 
#define TIM_CCMR1_CC1S_Msk   (0x3U << TIM_CCMR1_CC1S_Pos)
 
#define TIM_CCMR1_CC1S   TIM_CCMR1_CC1S_Msk
 
#define TIM_CCMR1_CC1S_0   (0x1U << TIM_CCMR1_CC1S_Pos)
 
#define TIM_CCMR1_CC1S_1   (0x2U << TIM_CCMR1_CC1S_Pos)
 
#define TIM_CCMR1_OC1FE_Pos   (2U)
 
#define TIM_CCMR1_OC1FE_Msk   (0x1U << TIM_CCMR1_OC1FE_Pos)
 
#define TIM_CCMR1_OC1FE   TIM_CCMR1_OC1FE_Msk
 
#define TIM_CCMR1_OC1PE_Pos   (3U)
 
#define TIM_CCMR1_OC1PE_Msk   (0x1U << TIM_CCMR1_OC1PE_Pos)
 
#define TIM_CCMR1_OC1PE   TIM_CCMR1_OC1PE_Msk
 
#define TIM_CCMR1_OC1M_Pos   (4U)
 
#define TIM_CCMR1_OC1M_Msk   (0x7U << TIM_CCMR1_OC1M_Pos)
 
#define TIM_CCMR1_OC1M   TIM_CCMR1_OC1M_Msk
 
#define TIM_CCMR1_OC1M_0   (0x1U << TIM_CCMR1_OC1M_Pos)
 
#define TIM_CCMR1_OC1M_1   (0x2U << TIM_CCMR1_OC1M_Pos)
 
#define TIM_CCMR1_OC1M_2   (0x4U << TIM_CCMR1_OC1M_Pos)
 
#define TIM_CCMR1_OC1CE_Pos   (7U)
 
#define TIM_CCMR1_OC1CE_Msk   (0x1U << TIM_CCMR1_OC1CE_Pos)
 
#define TIM_CCMR1_OC1CE   TIM_CCMR1_OC1CE_Msk
 
#define TIM_CCMR1_CC2S_Pos   (8U)
 
#define TIM_CCMR1_CC2S_Msk   (0x3U << TIM_CCMR1_CC2S_Pos)
 
#define TIM_CCMR1_CC2S   TIM_CCMR1_CC2S_Msk
 
#define TIM_CCMR1_CC2S_0   (0x1U << TIM_CCMR1_CC2S_Pos)
 
#define TIM_CCMR1_CC2S_1   (0x2U << TIM_CCMR1_CC2S_Pos)
 
#define TIM_CCMR1_OC2FE_Pos   (10U)
 
#define TIM_CCMR1_OC2FE_Msk   (0x1U << TIM_CCMR1_OC2FE_Pos)
 
#define TIM_CCMR1_OC2FE   TIM_CCMR1_OC2FE_Msk
 
#define TIM_CCMR1_OC2PE_Pos   (11U)
 
#define TIM_CCMR1_OC2PE_Msk   (0x1U << TIM_CCMR1_OC2PE_Pos)
 
#define TIM_CCMR1_OC2PE   TIM_CCMR1_OC2PE_Msk
 
#define TIM_CCMR1_OC2M_Pos   (12U)
 
#define TIM_CCMR1_OC2M_Msk   (0x7U << TIM_CCMR1_OC2M_Pos)
 
#define TIM_CCMR1_OC2M   TIM_CCMR1_OC2M_Msk
 
#define TIM_CCMR1_OC2M_0   (0x1U << TIM_CCMR1_OC2M_Pos)
 
#define TIM_CCMR1_OC2M_1   (0x2U << TIM_CCMR1_OC2M_Pos)
 
#define TIM_CCMR1_OC2M_2   (0x4U << TIM_CCMR1_OC2M_Pos)
 
#define TIM_CCMR1_OC2CE_Pos   (15U)
 
#define TIM_CCMR1_OC2CE_Msk   (0x1U << TIM_CCMR1_OC2CE_Pos)
 
#define TIM_CCMR1_OC2CE   TIM_CCMR1_OC2CE_Msk
 
#define TIM_CCMR1_IC1PSC_Pos   (2U)
 
#define TIM_CCMR1_IC1PSC_Msk   (0x3U << TIM_CCMR1_IC1PSC_Pos)
 
#define TIM_CCMR1_IC1PSC   TIM_CCMR1_IC1PSC_Msk
 
#define TIM_CCMR1_IC1PSC_0   (0x1U << TIM_CCMR1_IC1PSC_Pos)
 
#define TIM_CCMR1_IC1PSC_1   (0x2U << TIM_CCMR1_IC1PSC_Pos)
 
#define TIM_CCMR1_IC1F_Pos   (4U)
 
#define TIM_CCMR1_IC1F_Msk   (0xFU << TIM_CCMR1_IC1F_Pos)
 
#define TIM_CCMR1_IC1F   TIM_CCMR1_IC1F_Msk
 
#define TIM_CCMR1_IC1F_0   (0x1U << TIM_CCMR1_IC1F_Pos)
 
#define TIM_CCMR1_IC1F_1   (0x2U << TIM_CCMR1_IC1F_Pos)
 
#define TIM_CCMR1_IC1F_2   (0x4U << TIM_CCMR1_IC1F_Pos)
 
#define TIM_CCMR1_IC1F_3   (0x8U << TIM_CCMR1_IC1F_Pos)
 
#define TIM_CCMR1_IC2PSC_Pos   (10U)
 
#define TIM_CCMR1_IC2PSC_Msk   (0x3U << TIM_CCMR1_IC2PSC_Pos)
 
#define TIM_CCMR1_IC2PSC   TIM_CCMR1_IC2PSC_Msk
 
#define TIM_CCMR1_IC2PSC_0   (0x1U << TIM_CCMR1_IC2PSC_Pos)
 
#define TIM_CCMR1_IC2PSC_1   (0x2U << TIM_CCMR1_IC2PSC_Pos)
 
#define TIM_CCMR1_IC2F_Pos   (12U)
 
#define TIM_CCMR1_IC2F_Msk   (0xFU << TIM_CCMR1_IC2F_Pos)
 
#define TIM_CCMR1_IC2F   TIM_CCMR1_IC2F_Msk
 
#define TIM_CCMR1_IC2F_0   (0x1U << TIM_CCMR1_IC2F_Pos)
 
#define TIM_CCMR1_IC2F_1   (0x2U << TIM_CCMR1_IC2F_Pos)
 
#define TIM_CCMR1_IC2F_2   (0x4U << TIM_CCMR1_IC2F_Pos)
 
#define TIM_CCMR1_IC2F_3   (0x8U << TIM_CCMR1_IC2F_Pos)
 
#define TIM_CCMR2_CC3S_Pos   (0U)
 
#define TIM_CCMR2_CC3S_Msk   (0x3U << TIM_CCMR2_CC3S_Pos)
 
#define TIM_CCMR2_CC3S   TIM_CCMR2_CC3S_Msk
 
#define TIM_CCMR2_CC3S_0   (0x1U << TIM_CCMR2_CC3S_Pos)
 
#define TIM_CCMR2_CC3S_1   (0x2U << TIM_CCMR2_CC3S_Pos)
 
#define TIM_CCMR2_OC3FE_Pos   (2U)
 
#define TIM_CCMR2_OC3FE_Msk   (0x1U << TIM_CCMR2_OC3FE_Pos)
 
#define TIM_CCMR2_OC3FE   TIM_CCMR2_OC3FE_Msk
 
#define TIM_CCMR2_OC3PE_Pos   (3U)
 
#define TIM_CCMR2_OC3PE_Msk   (0x1U << TIM_CCMR2_OC3PE_Pos)
 
#define TIM_CCMR2_OC3PE   TIM_CCMR2_OC3PE_Msk
 
#define TIM_CCMR2_OC3M_Pos   (4U)
 
#define TIM_CCMR2_OC3M_Msk   (0x7U << TIM_CCMR2_OC3M_Pos)
 
#define TIM_CCMR2_OC3M   TIM_CCMR2_OC3M_Msk
 
#define TIM_CCMR2_OC3M_0   (0x1U << TIM_CCMR2_OC3M_Pos)
 
#define TIM_CCMR2_OC3M_1   (0x2U << TIM_CCMR2_OC3M_Pos)
 
#define TIM_CCMR2_OC3M_2   (0x4U << TIM_CCMR2_OC3M_Pos)
 
#define TIM_CCMR2_OC3CE_Pos   (7U)
 
#define TIM_CCMR2_OC3CE_Msk   (0x1U << TIM_CCMR2_OC3CE_Pos)
 
#define TIM_CCMR2_OC3CE   TIM_CCMR2_OC3CE_Msk
 
#define TIM_CCMR2_CC4S_Pos   (8U)
 
#define TIM_CCMR2_CC4S_Msk   (0x3U << TIM_CCMR2_CC4S_Pos)
 
#define TIM_CCMR2_CC4S   TIM_CCMR2_CC4S_Msk
 
#define TIM_CCMR2_CC4S_0   (0x1U << TIM_CCMR2_CC4S_Pos)
 
#define TIM_CCMR2_CC4S_1   (0x2U << TIM_CCMR2_CC4S_Pos)
 
#define TIM_CCMR2_OC4FE_Pos   (10U)
 
#define TIM_CCMR2_OC4FE_Msk   (0x1U << TIM_CCMR2_OC4FE_Pos)
 
#define TIM_CCMR2_OC4FE   TIM_CCMR2_OC4FE_Msk
 
#define TIM_CCMR2_OC4PE_Pos   (11U)
 
#define TIM_CCMR2_OC4PE_Msk   (0x1U << TIM_CCMR2_OC4PE_Pos)
 
#define TIM_CCMR2_OC4PE   TIM_CCMR2_OC4PE_Msk
 
#define TIM_CCMR2_OC4M_Pos   (12U)
 
#define TIM_CCMR2_OC4M_Msk   (0x7U << TIM_CCMR2_OC4M_Pos)
 
#define TIM_CCMR2_OC4M   TIM_CCMR2_OC4M_Msk
 
#define TIM_CCMR2_OC4M_0   (0x1U << TIM_CCMR2_OC4M_Pos)
 
#define TIM_CCMR2_OC4M_1   (0x2U << TIM_CCMR2_OC4M_Pos)
 
#define TIM_CCMR2_OC4M_2   (0x4U << TIM_CCMR2_OC4M_Pos)
 
#define TIM_CCMR2_OC4CE_Pos   (15U)
 
#define TIM_CCMR2_OC4CE_Msk   (0x1U << TIM_CCMR2_OC4CE_Pos)
 
#define TIM_CCMR2_OC4CE   TIM_CCMR2_OC4CE_Msk
 
#define TIM_CCMR2_IC3PSC_Pos   (2U)
 
#define TIM_CCMR2_IC3PSC_Msk   (0x3U << TIM_CCMR2_IC3PSC_Pos)
 
#define TIM_CCMR2_IC3PSC   TIM_CCMR2_IC3PSC_Msk
 
#define TIM_CCMR2_IC3PSC_0   (0x1U << TIM_CCMR2_IC3PSC_Pos)
 
#define TIM_CCMR2_IC3PSC_1   (0x2U << TIM_CCMR2_IC3PSC_Pos)
 
#define TIM_CCMR2_IC3F_Pos   (4U)
 
#define TIM_CCMR2_IC3F_Msk   (0xFU << TIM_CCMR2_IC3F_Pos)
 
#define TIM_CCMR2_IC3F   TIM_CCMR2_IC3F_Msk
 
#define TIM_CCMR2_IC3F_0   (0x1U << TIM_CCMR2_IC3F_Pos)
 
#define TIM_CCMR2_IC3F_1   (0x2U << TIM_CCMR2_IC3F_Pos)
 
#define TIM_CCMR2_IC3F_2   (0x4U << TIM_CCMR2_IC3F_Pos)
 
#define TIM_CCMR2_IC3F_3   (0x8U << TIM_CCMR2_IC3F_Pos)
 
#define TIM_CCMR2_IC4PSC_Pos   (10U)
 
#define TIM_CCMR2_IC4PSC_Msk   (0x3U << TIM_CCMR2_IC4PSC_Pos)
 
#define TIM_CCMR2_IC4PSC   TIM_CCMR2_IC4PSC_Msk
 
#define TIM_CCMR2_IC4PSC_0   (0x1U << TIM_CCMR2_IC4PSC_Pos)
 
#define TIM_CCMR2_IC4PSC_1   (0x2U << TIM_CCMR2_IC4PSC_Pos)
 
#define TIM_CCMR2_IC4F_Pos   (12U)
 
#define TIM_CCMR2_IC4F_Msk   (0xFU << TIM_CCMR2_IC4F_Pos)
 
#define TIM_CCMR2_IC4F   TIM_CCMR2_IC4F_Msk
 
#define TIM_CCMR2_IC4F_0   (0x1U << TIM_CCMR2_IC4F_Pos)
 
#define TIM_CCMR2_IC4F_1   (0x2U << TIM_CCMR2_IC4F_Pos)
 
#define TIM_CCMR2_IC4F_2   (0x4U << TIM_CCMR2_IC4F_Pos)
 
#define TIM_CCMR2_IC4F_3   (0x8U << TIM_CCMR2_IC4F_Pos)
 
#define TIM_CCER_CC1E_Pos   (0U)
 
#define TIM_CCER_CC1E_Msk   (0x1U << TIM_CCER_CC1E_Pos)
 
#define TIM_CCER_CC1E   TIM_CCER_CC1E_Msk
 
#define TIM_CCER_CC1P_Pos   (1U)
 
#define TIM_CCER_CC1P_Msk   (0x1U << TIM_CCER_CC1P_Pos)
 
#define TIM_CCER_CC1P   TIM_CCER_CC1P_Msk
 
#define TIM_CCER_CC1NP_Pos   (3U)
 
#define TIM_CCER_CC1NP_Msk   (0x1U << TIM_CCER_CC1NP_Pos)
 
#define TIM_CCER_CC1NP   TIM_CCER_CC1NP_Msk
 
#define TIM_CCER_CC2E_Pos   (4U)
 
#define TIM_CCER_CC2E_Msk   (0x1U << TIM_CCER_CC2E_Pos)
 
#define TIM_CCER_CC2E   TIM_CCER_CC2E_Msk
 
#define TIM_CCER_CC2P_Pos   (5U)
 
#define TIM_CCER_CC2P_Msk   (0x1U << TIM_CCER_CC2P_Pos)
 
#define TIM_CCER_CC2P   TIM_CCER_CC2P_Msk
 
#define TIM_CCER_CC2NP_Pos   (7U)
 
#define TIM_CCER_CC2NP_Msk   (0x1U << TIM_CCER_CC2NP_Pos)
 
#define TIM_CCER_CC2NP   TIM_CCER_CC2NP_Msk
 
#define TIM_CCER_CC3E_Pos   (8U)
 
#define TIM_CCER_CC3E_Msk   (0x1U << TIM_CCER_CC3E_Pos)
 
#define TIM_CCER_CC3E   TIM_CCER_CC3E_Msk
 
#define TIM_CCER_CC3P_Pos   (9U)
 
#define TIM_CCER_CC3P_Msk   (0x1U << TIM_CCER_CC3P_Pos)
 
#define TIM_CCER_CC3P   TIM_CCER_CC3P_Msk
 
#define TIM_CCER_CC3NP_Pos   (11U)
 
#define TIM_CCER_CC3NP_Msk   (0x1U << TIM_CCER_CC3NP_Pos)
 
#define TIM_CCER_CC3NP   TIM_CCER_CC3NP_Msk
 
#define TIM_CCER_CC4E_Pos   (12U)
 
#define TIM_CCER_CC4E_Msk   (0x1U << TIM_CCER_CC4E_Pos)
 
#define TIM_CCER_CC4E   TIM_CCER_CC4E_Msk
 
#define TIM_CCER_CC4P_Pos   (13U)
 
#define TIM_CCER_CC4P_Msk   (0x1U << TIM_CCER_CC4P_Pos)
 
#define TIM_CCER_CC4P   TIM_CCER_CC4P_Msk
 
#define TIM_CCER_CC4NP_Pos   (15U)
 
#define TIM_CCER_CC4NP_Msk   (0x1U << TIM_CCER_CC4NP_Pos)
 
#define TIM_CCER_CC4NP   TIM_CCER_CC4NP_Msk
 
#define TIM_CNT_CNT_Pos   (0U)
 
#define TIM_CNT_CNT_Msk   (0xFFFFFFFFU << TIM_CNT_CNT_Pos)
 
#define TIM_CNT_CNT   TIM_CNT_CNT_Msk
 
#define TIM_PSC_PSC_Pos   (0U)
 
#define TIM_PSC_PSC_Msk   (0xFFFFU << TIM_PSC_PSC_Pos)
 
#define TIM_PSC_PSC   TIM_PSC_PSC_Msk
 
#define TIM_ARR_ARR_Pos   (0U)
 
#define TIM_ARR_ARR_Msk   (0xFFFFFFFFU << TIM_ARR_ARR_Pos)
 
#define TIM_ARR_ARR   TIM_ARR_ARR_Msk
 
#define TIM_CCR1_CCR1_Pos   (0U)
 
#define TIM_CCR1_CCR1_Msk   (0xFFFFU << TIM_CCR1_CCR1_Pos)
 
#define TIM_CCR1_CCR1   TIM_CCR1_CCR1_Msk
 
#define TIM_CCR2_CCR2_Pos   (0U)
 
#define TIM_CCR2_CCR2_Msk   (0xFFFFU << TIM_CCR2_CCR2_Pos)
 
#define TIM_CCR2_CCR2   TIM_CCR2_CCR2_Msk
 
#define TIM_CCR3_CCR3_Pos   (0U)
 
#define TIM_CCR3_CCR3_Msk   (0xFFFFU << TIM_CCR3_CCR3_Pos)
 
#define TIM_CCR3_CCR3   TIM_CCR3_CCR3_Msk
 
#define TIM_CCR4_CCR4_Pos   (0U)
 
#define TIM_CCR4_CCR4_Msk   (0xFFFFU << TIM_CCR4_CCR4_Pos)
 
#define TIM_CCR4_CCR4   TIM_CCR4_CCR4_Msk
 
#define TIM_DCR_DBA_Pos   (0U)
 
#define TIM_DCR_DBA_Msk   (0x1FU << TIM_DCR_DBA_Pos)
 
#define TIM_DCR_DBA   TIM_DCR_DBA_Msk
 
#define TIM_DCR_DBA_0   (0x01U << TIM_DCR_DBA_Pos)
 
#define TIM_DCR_DBA_1   (0x02U << TIM_DCR_DBA_Pos)
 
#define TIM_DCR_DBA_2   (0x04U << TIM_DCR_DBA_Pos)
 
#define TIM_DCR_DBA_3   (0x08U << TIM_DCR_DBA_Pos)
 
#define TIM_DCR_DBA_4   (0x10U << TIM_DCR_DBA_Pos)
 
#define TIM_DCR_DBL_Pos   (8U)
 
#define TIM_DCR_DBL_Msk   (0x1FU << TIM_DCR_DBL_Pos)
 
#define TIM_DCR_DBL   TIM_DCR_DBL_Msk
 
#define TIM_DCR_DBL_0   (0x01U << TIM_DCR_DBL_Pos)
 
#define TIM_DCR_DBL_1   (0x02U << TIM_DCR_DBL_Pos)
 
#define TIM_DCR_DBL_2   (0x04U << TIM_DCR_DBL_Pos)
 
#define TIM_DCR_DBL_3   (0x08U << TIM_DCR_DBL_Pos)
 
#define TIM_DCR_DBL_4   (0x10U << TIM_DCR_DBL_Pos)
 
#define TIM_DMAR_DMAB_Pos   (0U)
 
#define TIM_DMAR_DMAB_Msk   (0xFFFFU << TIM_DMAR_DMAB_Pos)
 
#define TIM_DMAR_DMAB   TIM_DMAR_DMAB_Msk
 
#define TIM_OR_TI1RMP_Pos   (0U)
 
#define TIM_OR_TI1RMP_Msk   (0x3U << TIM_OR_TI1RMP_Pos)
 
#define TIM_OR_TI1RMP   TIM_OR_TI1RMP_Msk
 
#define TIM_OR_TI1RMP_0   (0x1U << TIM_OR_TI1RMP_Pos)
 
#define TIM_OR_TI1RMP_1   (0x2U << TIM_OR_TI1RMP_Pos)
 
#define TIM_OR_ETR_RMP_Pos   (2U)
 
#define TIM_OR_ETR_RMP_Msk   (0x1U << TIM_OR_ETR_RMP_Pos)
 
#define TIM_OR_ETR_RMP   TIM_OR_ETR_RMP_Msk
 
#define TIM_OR_TI1_RMP_RI_Pos   (3U)
 
#define TIM_OR_TI1_RMP_RI_Msk   (0x1U << TIM_OR_TI1_RMP_RI_Pos)
 
#define TIM_OR_TI1_RMP_RI   TIM_OR_TI1_RMP_RI_Msk
 
#define TIM9_OR_ITR1_RMP_Pos   (2U)
 
#define TIM9_OR_ITR1_RMP_Msk   (0x1U << TIM9_OR_ITR1_RMP_Pos)
 
#define TIM9_OR_ITR1_RMP   TIM9_OR_ITR1_RMP_Msk
 
#define TIM2_OR_ITR1_RMP_Pos   (0U)
 
#define TIM2_OR_ITR1_RMP_Msk   (0x1U << TIM2_OR_ITR1_RMP_Pos)
 
#define TIM2_OR_ITR1_RMP   TIM2_OR_ITR1_RMP_Msk
 
#define TIM3_OR_ITR2_RMP_Pos   (0U)
 
#define TIM3_OR_ITR2_RMP_Msk   (0x1U << TIM3_OR_ITR2_RMP_Pos)
 
#define TIM3_OR_ITR2_RMP   TIM3_OR_ITR2_RMP_Msk
 
#define USART_SR_PE_Pos   (0U)
 
#define USART_SR_PE_Msk   (0x1U << USART_SR_PE_Pos)
 
#define USART_SR_PE   USART_SR_PE_Msk
 
#define USART_SR_FE_Pos   (1U)
 
#define USART_SR_FE_Msk   (0x1U << USART_SR_FE_Pos)
 
#define USART_SR_FE   USART_SR_FE_Msk
 
#define USART_SR_NE_Pos   (2U)
 
#define USART_SR_NE_Msk   (0x1U << USART_SR_NE_Pos)
 
#define USART_SR_NE   USART_SR_NE_Msk
 
#define USART_SR_ORE_Pos   (3U)
 
#define USART_SR_ORE_Msk   (0x1U << USART_SR_ORE_Pos)
 
#define USART_SR_ORE   USART_SR_ORE_Msk
 
#define USART_SR_IDLE_Pos   (4U)
 
#define USART_SR_IDLE_Msk   (0x1U << USART_SR_IDLE_Pos)
 
#define USART_SR_IDLE   USART_SR_IDLE_Msk
 
#define USART_SR_RXNE_Pos   (5U)
 
#define USART_SR_RXNE_Msk   (0x1U << USART_SR_RXNE_Pos)
 
#define USART_SR_RXNE   USART_SR_RXNE_Msk
 
#define USART_SR_TC_Pos   (6U)
 
#define USART_SR_TC_Msk   (0x1U << USART_SR_TC_Pos)
 
#define USART_SR_TC   USART_SR_TC_Msk
 
#define USART_SR_TXE_Pos   (7U)
 
#define USART_SR_TXE_Msk   (0x1U << USART_SR_TXE_Pos)
 
#define USART_SR_TXE   USART_SR_TXE_Msk
 
#define USART_SR_LBD_Pos   (8U)
 
#define USART_SR_LBD_Msk   (0x1U << USART_SR_LBD_Pos)
 
#define USART_SR_LBD   USART_SR_LBD_Msk
 
#define USART_SR_CTS_Pos   (9U)
 
#define USART_SR_CTS_Msk   (0x1U << USART_SR_CTS_Pos)
 
#define USART_SR_CTS   USART_SR_CTS_Msk
 
#define USART_DR_DR_Pos   (0U)
 
#define USART_DR_DR_Msk   (0x1FFU << USART_DR_DR_Pos)
 
#define USART_DR_DR   USART_DR_DR_Msk
 
#define USART_BRR_DIV_FRACTION_Pos   (0U)
 
#define USART_BRR_DIV_FRACTION_Msk   (0xFU << USART_BRR_DIV_FRACTION_Pos)
 
#define USART_BRR_DIV_FRACTION   USART_BRR_DIV_FRACTION_Msk
 
#define USART_BRR_DIV_MANTISSA_Pos   (4U)
 
#define USART_BRR_DIV_MANTISSA_Msk   (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)
 
#define USART_BRR_DIV_MANTISSA   USART_BRR_DIV_MANTISSA_Msk
 
#define USART_CR1_SBK_Pos   (0U)
 
#define USART_CR1_SBK_Msk   (0x1U << USART_CR1_SBK_Pos)
 
#define USART_CR1_SBK   USART_CR1_SBK_Msk
 
#define USART_CR1_RWU_Pos   (1U)
 
#define USART_CR1_RWU_Msk   (0x1U << USART_CR1_RWU_Pos)
 
#define USART_CR1_RWU   USART_CR1_RWU_Msk
 
#define USART_CR1_RE_Pos   (2U)
 
#define USART_CR1_RE_Msk   (0x1U << USART_CR1_RE_Pos)
 
#define USART_CR1_RE   USART_CR1_RE_Msk
 
#define USART_CR1_TE_Pos   (3U)
 
#define USART_CR1_TE_Msk   (0x1U << USART_CR1_TE_Pos)
 
#define USART_CR1_TE   USART_CR1_TE_Msk
 
#define USART_CR1_IDLEIE_Pos   (4U)
 
#define USART_CR1_IDLEIE_Msk   (0x1U << USART_CR1_IDLEIE_Pos)
 
#define USART_CR1_IDLEIE   USART_CR1_IDLEIE_Msk
 
#define USART_CR1_RXNEIE_Pos   (5U)
 
#define USART_CR1_RXNEIE_Msk   (0x1U << USART_CR1_RXNEIE_Pos)
 
#define USART_CR1_RXNEIE   USART_CR1_RXNEIE_Msk
 
#define USART_CR1_TCIE_Pos   (6U)
 
#define USART_CR1_TCIE_Msk   (0x1U << USART_CR1_TCIE_Pos)
 
#define USART_CR1_TCIE   USART_CR1_TCIE_Msk
 
#define USART_CR1_TXEIE_Pos   (7U)
 
#define USART_CR1_TXEIE_Msk   (0x1U << USART_CR1_TXEIE_Pos)
 
#define USART_CR1_TXEIE   USART_CR1_TXEIE_Msk
 
#define USART_CR1_PEIE_Pos   (8U)
 
#define USART_CR1_PEIE_Msk   (0x1U << USART_CR1_PEIE_Pos)
 
#define USART_CR1_PEIE   USART_CR1_PEIE_Msk
 
#define USART_CR1_PS_Pos   (9U)
 
#define USART_CR1_PS_Msk   (0x1U << USART_CR1_PS_Pos)
 
#define USART_CR1_PS   USART_CR1_PS_Msk
 
#define USART_CR1_PCE_Pos   (10U)
 
#define USART_CR1_PCE_Msk   (0x1U << USART_CR1_PCE_Pos)
 
#define USART_CR1_PCE   USART_CR1_PCE_Msk
 
#define USART_CR1_WAKE_Pos   (11U)
 
#define USART_CR1_WAKE_Msk   (0x1U << USART_CR1_WAKE_Pos)
 
#define USART_CR1_WAKE   USART_CR1_WAKE_Msk
 
#define USART_CR1_M_Pos   (12U)
 
#define USART_CR1_M_Msk   (0x1U << USART_CR1_M_Pos)
 
#define USART_CR1_M   USART_CR1_M_Msk
 
#define USART_CR1_UE_Pos   (13U)
 
#define USART_CR1_UE_Msk   (0x1U << USART_CR1_UE_Pos)
 
#define USART_CR1_UE   USART_CR1_UE_Msk
 
#define USART_CR1_OVER8_Pos   (15U)
 
#define USART_CR1_OVER8_Msk   (0x1U << USART_CR1_OVER8_Pos)
 
#define USART_CR1_OVER8   USART_CR1_OVER8_Msk
 
#define USART_CR2_ADD_Pos   (0U)
 
#define USART_CR2_ADD_Msk   (0xFU << USART_CR2_ADD_Pos)
 
#define USART_CR2_ADD   USART_CR2_ADD_Msk
 
#define USART_CR2_LBDL_Pos   (5U)
 
#define USART_CR2_LBDL_Msk   (0x1U << USART_CR2_LBDL_Pos)
 
#define USART_CR2_LBDL   USART_CR2_LBDL_Msk
 
#define USART_CR2_LBDIE_Pos   (6U)
 
#define USART_CR2_LBDIE_Msk   (0x1U << USART_CR2_LBDIE_Pos)
 
#define USART_CR2_LBDIE   USART_CR2_LBDIE_Msk
 
#define USART_CR2_LBCL_Pos   (8U)
 
#define USART_CR2_LBCL_Msk   (0x1U << USART_CR2_LBCL_Pos)
 
#define USART_CR2_LBCL   USART_CR2_LBCL_Msk
 
#define USART_CR2_CPHA_Pos   (9U)
 
#define USART_CR2_CPHA_Msk   (0x1U << USART_CR2_CPHA_Pos)
 
#define USART_CR2_CPHA   USART_CR2_CPHA_Msk
 
#define USART_CR2_CPOL_Pos   (10U)
 
#define USART_CR2_CPOL_Msk   (0x1U << USART_CR2_CPOL_Pos)
 
#define USART_CR2_CPOL   USART_CR2_CPOL_Msk
 
#define USART_CR2_CLKEN_Pos   (11U)
 
#define USART_CR2_CLKEN_Msk   (0x1U << USART_CR2_CLKEN_Pos)
 
#define USART_CR2_CLKEN   USART_CR2_CLKEN_Msk
 
#define USART_CR2_STOP_Pos   (12U)
 
#define USART_CR2_STOP_Msk   (0x3U << USART_CR2_STOP_Pos)
 
#define USART_CR2_STOP   USART_CR2_STOP_Msk
 
#define USART_CR2_STOP_0   (0x1U << USART_CR2_STOP_Pos)
 
#define USART_CR2_STOP_1   (0x2U << USART_CR2_STOP_Pos)
 
#define USART_CR2_LINEN_Pos   (14U)
 
#define USART_CR2_LINEN_Msk   (0x1U << USART_CR2_LINEN_Pos)
 
#define USART_CR2_LINEN   USART_CR2_LINEN_Msk
 
#define USART_CR3_EIE_Pos   (0U)
 
#define USART_CR3_EIE_Msk   (0x1U << USART_CR3_EIE_Pos)
 
#define USART_CR3_EIE   USART_CR3_EIE_Msk
 
#define USART_CR3_IREN_Pos   (1U)
 
#define USART_CR3_IREN_Msk   (0x1U << USART_CR3_IREN_Pos)
 
#define USART_CR3_IREN   USART_CR3_IREN_Msk
 
#define USART_CR3_IRLP_Pos   (2U)
 
#define USART_CR3_IRLP_Msk   (0x1U << USART_CR3_IRLP_Pos)
 
#define USART_CR3_IRLP   USART_CR3_IRLP_Msk
 
#define USART_CR3_HDSEL_Pos   (3U)
 
#define USART_CR3_HDSEL_Msk   (0x1U << USART_CR3_HDSEL_Pos)
 
#define USART_CR3_HDSEL   USART_CR3_HDSEL_Msk
 
#define USART_CR3_NACK_Pos   (4U)
 
#define USART_CR3_NACK_Msk   (0x1U << USART_CR3_NACK_Pos)
 
#define USART_CR3_NACK   USART_CR3_NACK_Msk
 
#define USART_CR3_SCEN_Pos   (5U)
 
#define USART_CR3_SCEN_Msk   (0x1U << USART_CR3_SCEN_Pos)
 
#define USART_CR3_SCEN   USART_CR3_SCEN_Msk
 
#define USART_CR3_DMAR_Pos   (6U)
 
#define USART_CR3_DMAR_Msk   (0x1U << USART_CR3_DMAR_Pos)
 
#define USART_CR3_DMAR   USART_CR3_DMAR_Msk
 
#define USART_CR3_DMAT_Pos   (7U)
 
#define USART_CR3_DMAT_Msk   (0x1U << USART_CR3_DMAT_Pos)
 
#define USART_CR3_DMAT   USART_CR3_DMAT_Msk
 
#define USART_CR3_RTSE_Pos   (8U)
 
#define USART_CR3_RTSE_Msk   (0x1U << USART_CR3_RTSE_Pos)
 
#define USART_CR3_RTSE   USART_CR3_RTSE_Msk
 
#define USART_CR3_CTSE_Pos   (9U)
 
#define USART_CR3_CTSE_Msk   (0x1U << USART_CR3_CTSE_Pos)
 
#define USART_CR3_CTSE   USART_CR3_CTSE_Msk
 
#define USART_CR3_CTSIE_Pos   (10U)
 
#define USART_CR3_CTSIE_Msk   (0x1U << USART_CR3_CTSIE_Pos)
 
#define USART_CR3_CTSIE   USART_CR3_CTSIE_Msk
 
#define USART_CR3_ONEBIT_Pos   (11U)
 
#define USART_CR3_ONEBIT_Msk   (0x1U << USART_CR3_ONEBIT_Pos)
 
#define USART_CR3_ONEBIT   USART_CR3_ONEBIT_Msk
 
#define USART_GTPR_PSC_Pos   (0U)
 
#define USART_GTPR_PSC_Msk   (0xFFU << USART_GTPR_PSC_Pos)
 
#define USART_GTPR_PSC   USART_GTPR_PSC_Msk
 
#define USART_GTPR_PSC_0   (0x01U << USART_GTPR_PSC_Pos)
 
#define USART_GTPR_PSC_1   (0x02U << USART_GTPR_PSC_Pos)
 
#define USART_GTPR_PSC_2   (0x04U << USART_GTPR_PSC_Pos)
 
#define USART_GTPR_PSC_3   (0x08U << USART_GTPR_PSC_Pos)
 
#define USART_GTPR_PSC_4   (0x10U << USART_GTPR_PSC_Pos)
 
#define USART_GTPR_PSC_5   (0x20U << USART_GTPR_PSC_Pos)
 
#define USART_GTPR_PSC_6   (0x40U << USART_GTPR_PSC_Pos)
 
#define USART_GTPR_PSC_7   (0x80U << USART_GTPR_PSC_Pos)
 
#define USART_GTPR_GT_Pos   (8U)
 
#define USART_GTPR_GT_Msk   (0xFFU << USART_GTPR_GT_Pos)
 
#define USART_GTPR_GT   USART_GTPR_GT_Msk
 
#define USB_EP0R   USB_BASE
 
#define USB_EP1R   (USB_BASE + 0x00000004U)
 
#define USB_EP2R   (USB_BASE + 0x00000008U)
 
#define USB_EP3R   (USB_BASE + 0x0000000CU)
 
#define USB_EP4R   (USB_BASE + 0x00000010U)
 
#define USB_EP5R   (USB_BASE + 0x00000014U)
 
#define USB_EP6R   (USB_BASE + 0x00000018U)
 
#define USB_EP7R   (USB_BASE + 0x0000001CU)
 
#define USB_EP_CTR_RX_Pos   (15U)
 
#define USB_EP_CTR_RX_Msk   (0x1U << USB_EP_CTR_RX_Pos)
 
#define USB_EP_CTR_RX   USB_EP_CTR_RX_Msk
 
#define USB_EP_DTOG_RX_Pos   (14U)
 
#define USB_EP_DTOG_RX_Msk   (0x1U << USB_EP_DTOG_RX_Pos)
 
#define USB_EP_DTOG_RX   USB_EP_DTOG_RX_Msk
 
#define USB_EPRX_STAT_Pos   (12U)
 
#define USB_EPRX_STAT_Msk   (0x3U << USB_EPRX_STAT_Pos)
 
#define USB_EPRX_STAT   USB_EPRX_STAT_Msk
 
#define USB_EP_SETUP_Pos   (11U)
 
#define USB_EP_SETUP_Msk   (0x1U << USB_EP_SETUP_Pos)
 
#define USB_EP_SETUP   USB_EP_SETUP_Msk
 
#define USB_EP_T_FIELD_Pos   (9U)
 
#define USB_EP_T_FIELD_Msk   (0x3U << USB_EP_T_FIELD_Pos)
 
#define USB_EP_T_FIELD   USB_EP_T_FIELD_Msk
 
#define USB_EP_KIND_Pos   (8U)
 
#define USB_EP_KIND_Msk   (0x1U << USB_EP_KIND_Pos)
 
#define USB_EP_KIND   USB_EP_KIND_Msk
 
#define USB_EP_CTR_TX_Pos   (7U)
 
#define USB_EP_CTR_TX_Msk   (0x1U << USB_EP_CTR_TX_Pos)
 
#define USB_EP_CTR_TX   USB_EP_CTR_TX_Msk
 
#define USB_EP_DTOG_TX_Pos   (6U)
 
#define USB_EP_DTOG_TX_Msk   (0x1U << USB_EP_DTOG_TX_Pos)
 
#define USB_EP_DTOG_TX   USB_EP_DTOG_TX_Msk
 
#define USB_EPTX_STAT_Pos   (4U)
 
#define USB_EPTX_STAT_Msk   (0x3U << USB_EPTX_STAT_Pos)
 
#define USB_EPTX_STAT   USB_EPTX_STAT_Msk
 
#define USB_EPADDR_FIELD_Pos   (0U)
 
#define USB_EPADDR_FIELD_Msk   (0xFU << USB_EPADDR_FIELD_Pos)
 
#define USB_EPADDR_FIELD   USB_EPADDR_FIELD_Msk
 
#define USB_EPREG_MASK   (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
 
#define USB_EP_TYPE_MASK_Pos   (9U)
 
#define USB_EP_TYPE_MASK_Msk   (0x3U << USB_EP_TYPE_MASK_Pos)
 
#define USB_EP_TYPE_MASK   USB_EP_TYPE_MASK_Msk
 
#define USB_EP_BULK   (0x00000000U)
 
#define USB_EP_CONTROL   (0x00000200U)
 
#define USB_EP_ISOCHRONOUS   (0x00000400U)
 
#define USB_EP_INTERRUPT   (0x00000600U)
 
#define USB_EP_T_MASK   (~USB_EP_T_FIELD & USB_EPREG_MASK)
 
#define USB_EPKIND_MASK   (~USB_EP_KIND & USB_EPREG_MASK)
 
#define USB_EP_TX_DIS   (0x00000000U)
 
#define USB_EP_TX_STALL   (0x00000010U)
 
#define USB_EP_TX_NAK   (0x00000020U)
 
#define USB_EP_TX_VALID   (0x00000030U)
 
#define USB_EPTX_DTOG1   (0x00000010U)
 
#define USB_EPTX_DTOG2   (0x00000020U)
 
#define USB_EPTX_DTOGMASK   (USB_EPTX_STAT|USB_EPREG_MASK)
 
#define USB_EP_RX_DIS   (0x00000000U)
 
#define USB_EP_RX_STALL   (0x00001000U)
 
#define USB_EP_RX_NAK   (0x00002000U)
 
#define USB_EP_RX_VALID   (0x00003000U)
 
#define USB_EPRX_DTOG1   (0x00001000U)
 
#define USB_EPRX_DTOG2   (0x00002000U)
 
#define USB_EPRX_DTOGMASK   (USB_EPRX_STAT|USB_EPREG_MASK)
 
#define USB_EP0R_EA_Pos   (0U)
 
#define USB_EP0R_EA_Msk   (0xFU << USB_EP0R_EA_Pos)
 
#define USB_EP0R_EA   USB_EP0R_EA_Msk
 
#define USB_EP0R_STAT_TX_Pos   (4U)
 
#define USB_EP0R_STAT_TX_Msk   (0x3U << USB_EP0R_STAT_TX_Pos)
 
#define USB_EP0R_STAT_TX   USB_EP0R_STAT_TX_Msk
 
#define USB_EP0R_STAT_TX_0   (0x1U << USB_EP0R_STAT_TX_Pos)
 
#define USB_EP0R_STAT_TX_1   (0x2U << USB_EP0R_STAT_TX_Pos)
 
#define USB_EP0R_DTOG_TX_Pos   (6U)
 
#define USB_EP0R_DTOG_TX_Msk   (0x1U << USB_EP0R_DTOG_TX_Pos)
 
#define USB_EP0R_DTOG_TX   USB_EP0R_DTOG_TX_Msk
 
#define USB_EP0R_CTR_TX_Pos   (7U)
 
#define USB_EP0R_CTR_TX_Msk   (0x1U << USB_EP0R_CTR_TX_Pos)
 
#define USB_EP0R_CTR_TX   USB_EP0R_CTR_TX_Msk
 
#define USB_EP0R_EP_KIND_Pos   (8U)
 
#define USB_EP0R_EP_KIND_Msk   (0x1U << USB_EP0R_EP_KIND_Pos)
 
#define USB_EP0R_EP_KIND   USB_EP0R_EP_KIND_Msk
 
#define USB_EP0R_EP_TYPE_Pos   (9U)
 
#define USB_EP0R_EP_TYPE_Msk   (0x3U << USB_EP0R_EP_TYPE_Pos)
 
#define USB_EP0R_EP_TYPE   USB_EP0R_EP_TYPE_Msk
 
#define USB_EP0R_EP_TYPE_0   (0x1U << USB_EP0R_EP_TYPE_Pos)
 
#define USB_EP0R_EP_TYPE_1   (0x2U << USB_EP0R_EP_TYPE_Pos)
 
#define USB_EP0R_SETUP_Pos   (11U)
 
#define USB_EP0R_SETUP_Msk   (0x1U << USB_EP0R_SETUP_Pos)
 
#define USB_EP0R_SETUP   USB_EP0R_SETUP_Msk
 
#define USB_EP0R_STAT_RX_Pos   (12U)
 
#define USB_EP0R_STAT_RX_Msk   (0x3U << USB_EP0R_STAT_RX_Pos)
 
#define USB_EP0R_STAT_RX   USB_EP0R_STAT_RX_Msk
 
#define USB_EP0R_STAT_RX_0   (0x1U << USB_EP0R_STAT_RX_Pos)
 
#define USB_EP0R_STAT_RX_1   (0x2U << USB_EP0R_STAT_RX_Pos)
 
#define USB_EP0R_DTOG_RX_Pos   (14U)
 
#define USB_EP0R_DTOG_RX_Msk   (0x1U << USB_EP0R_DTOG_RX_Pos)
 
#define USB_EP0R_DTOG_RX   USB_EP0R_DTOG_RX_Msk
 
#define USB_EP0R_CTR_RX_Pos   (15U)
 
#define USB_EP0R_CTR_RX_Msk   (0x1U << USB_EP0R_CTR_RX_Pos)
 
#define USB_EP0R_CTR_RX   USB_EP0R_CTR_RX_Msk
 
#define USB_EP1R_EA_Pos   (0U)
 
#define USB_EP1R_EA_Msk   (0xFU << USB_EP1R_EA_Pos)
 
#define USB_EP1R_EA   USB_EP1R_EA_Msk
 
#define USB_EP1R_STAT_TX_Pos   (4U)
 
#define USB_EP1R_STAT_TX_Msk   (0x3U << USB_EP1R_STAT_TX_Pos)
 
#define USB_EP1R_STAT_TX   USB_EP1R_STAT_TX_Msk
 
#define USB_EP1R_STAT_TX_0   (0x1U << USB_EP1R_STAT_TX_Pos)
 
#define USB_EP1R_STAT_TX_1   (0x2U << USB_EP1R_STAT_TX_Pos)
 
#define USB_EP1R_DTOG_TX_Pos   (6U)
 
#define USB_EP1R_DTOG_TX_Msk   (0x1U << USB_EP1R_DTOG_TX_Pos)
 
#define USB_EP1R_DTOG_TX   USB_EP1R_DTOG_TX_Msk
 
#define USB_EP1R_CTR_TX_Pos   (7U)
 
#define USB_EP1R_CTR_TX_Msk   (0x1U << USB_EP1R_CTR_TX_Pos)
 
#define USB_EP1R_CTR_TX   USB_EP1R_CTR_TX_Msk
 
#define USB_EP1R_EP_KIND_Pos   (8U)
 
#define USB_EP1R_EP_KIND_Msk   (0x1U << USB_EP1R_EP_KIND_Pos)
 
#define USB_EP1R_EP_KIND   USB_EP1R_EP_KIND_Msk
 
#define USB_EP1R_EP_TYPE_Pos   (9U)
 
#define USB_EP1R_EP_TYPE_Msk   (0x3U << USB_EP1R_EP_TYPE_Pos)
 
#define USB_EP1R_EP_TYPE   USB_EP1R_EP_TYPE_Msk
 
#define USB_EP1R_EP_TYPE_0   (0x1U << USB_EP1R_EP_TYPE_Pos)
 
#define USB_EP1R_EP_TYPE_1   (0x2U << USB_EP1R_EP_TYPE_Pos)
 
#define USB_EP1R_SETUP_Pos   (11U)
 
#define USB_EP1R_SETUP_Msk   (0x1U << USB_EP1R_SETUP_Pos)
 
#define USB_EP1R_SETUP   USB_EP1R_SETUP_Msk
 
#define USB_EP1R_STAT_RX_Pos   (12U)
 
#define USB_EP1R_STAT_RX_Msk   (0x3U << USB_EP1R_STAT_RX_Pos)
 
#define USB_EP1R_STAT_RX   USB_EP1R_STAT_RX_Msk
 
#define USB_EP1R_STAT_RX_0   (0x1U << USB_EP1R_STAT_RX_Pos)
 
#define USB_EP1R_STAT_RX_1   (0x2U << USB_EP1R_STAT_RX_Pos)
 
#define USB_EP1R_DTOG_RX_Pos   (14U)
 
#define USB_EP1R_DTOG_RX_Msk   (0x1U << USB_EP1R_DTOG_RX_Pos)
 
#define USB_EP1R_DTOG_RX   USB_EP1R_DTOG_RX_Msk
 
#define USB_EP1R_CTR_RX_Pos   (15U)
 
#define USB_EP1R_CTR_RX_Msk   (0x1U << USB_EP1R_CTR_RX_Pos)
 
#define USB_EP1R_CTR_RX   USB_EP1R_CTR_RX_Msk
 
#define USB_EP2R_EA_Pos   (0U)
 
#define USB_EP2R_EA_Msk   (0xFU << USB_EP2R_EA_Pos)
 
#define USB_EP2R_EA   USB_EP2R_EA_Msk
 
#define USB_EP2R_STAT_TX_Pos   (4U)
 
#define USB_EP2R_STAT_TX_Msk   (0x3U << USB_EP2R_STAT_TX_Pos)
 
#define USB_EP2R_STAT_TX   USB_EP2R_STAT_TX_Msk
 
#define USB_EP2R_STAT_TX_0   (0x1U << USB_EP2R_STAT_TX_Pos)
 
#define USB_EP2R_STAT_TX_1   (0x2U << USB_EP2R_STAT_TX_Pos)
 
#define USB_EP2R_DTOG_TX_Pos   (6U)
 
#define USB_EP2R_DTOG_TX_Msk   (0x1U << USB_EP2R_DTOG_TX_Pos)
 
#define USB_EP2R_DTOG_TX   USB_EP2R_DTOG_TX_Msk
 
#define USB_EP2R_CTR_TX_Pos   (7U)
 
#define USB_EP2R_CTR_TX_Msk   (0x1U << USB_EP2R_CTR_TX_Pos)
 
#define USB_EP2R_CTR_TX   USB_EP2R_CTR_TX_Msk
 
#define USB_EP2R_EP_KIND_Pos   (8U)
 
#define USB_EP2R_EP_KIND_Msk   (0x1U << USB_EP2R_EP_KIND_Pos)
 
#define USB_EP2R_EP_KIND   USB_EP2R_EP_KIND_Msk
 
#define USB_EP2R_EP_TYPE_Pos   (9U)
 
#define USB_EP2R_EP_TYPE_Msk   (0x3U << USB_EP2R_EP_TYPE_Pos)
 
#define USB_EP2R_EP_TYPE   USB_EP2R_EP_TYPE_Msk
 
#define USB_EP2R_EP_TYPE_0   (0x1U << USB_EP2R_EP_TYPE_Pos)
 
#define USB_EP2R_EP_TYPE_1   (0x2U << USB_EP2R_EP_TYPE_Pos)
 
#define USB_EP2R_SETUP_Pos   (11U)
 
#define USB_EP2R_SETUP_Msk   (0x1U << USB_EP2R_SETUP_Pos)
 
#define USB_EP2R_SETUP   USB_EP2R_SETUP_Msk
 
#define USB_EP2R_STAT_RX_Pos   (12U)
 
#define USB_EP2R_STAT_RX_Msk   (0x3U << USB_EP2R_STAT_RX_Pos)
 
#define USB_EP2R_STAT_RX   USB_EP2R_STAT_RX_Msk
 
#define USB_EP2R_STAT_RX_0   (0x1U << USB_EP2R_STAT_RX_Pos)
 
#define USB_EP2R_STAT_RX_1   (0x2U << USB_EP2R_STAT_RX_Pos)
 
#define USB_EP2R_DTOG_RX_Pos   (14U)
 
#define USB_EP2R_DTOG_RX_Msk   (0x1U << USB_EP2R_DTOG_RX_Pos)
 
#define USB_EP2R_DTOG_RX   USB_EP2R_DTOG_RX_Msk
 
#define USB_EP2R_CTR_RX_Pos   (15U)
 
#define USB_EP2R_CTR_RX_Msk   (0x1U << USB_EP2R_CTR_RX_Pos)
 
#define USB_EP2R_CTR_RX   USB_EP2R_CTR_RX_Msk
 
#define USB_EP3R_EA_Pos   (0U)
 
#define USB_EP3R_EA_Msk   (0xFU << USB_EP3R_EA_Pos)
 
#define USB_EP3R_EA   USB_EP3R_EA_Msk
 
#define USB_EP3R_STAT_TX_Pos   (4U)
 
#define USB_EP3R_STAT_TX_Msk   (0x3U << USB_EP3R_STAT_TX_Pos)
 
#define USB_EP3R_STAT_TX   USB_EP3R_STAT_TX_Msk
 
#define USB_EP3R_STAT_TX_0   (0x1U << USB_EP3R_STAT_TX_Pos)
 
#define USB_EP3R_STAT_TX_1   (0x2U << USB_EP3R_STAT_TX_Pos)
 
#define USB_EP3R_DTOG_TX_Pos   (6U)
 
#define USB_EP3R_DTOG_TX_Msk   (0x1U << USB_EP3R_DTOG_TX_Pos)
 
#define USB_EP3R_DTOG_TX   USB_EP3R_DTOG_TX_Msk
 
#define USB_EP3R_CTR_TX_Pos   (7U)
 
#define USB_EP3R_CTR_TX_Msk   (0x1U << USB_EP3R_CTR_TX_Pos)
 
#define USB_EP3R_CTR_TX   USB_EP3R_CTR_TX_Msk
 
#define USB_EP3R_EP_KIND_Pos   (8U)
 
#define USB_EP3R_EP_KIND_Msk   (0x1U << USB_EP3R_EP_KIND_Pos)
 
#define USB_EP3R_EP_KIND   USB_EP3R_EP_KIND_Msk
 
#define USB_EP3R_EP_TYPE_Pos   (9U)
 
#define USB_EP3R_EP_TYPE_Msk   (0x3U << USB_EP3R_EP_TYPE_Pos)
 
#define USB_EP3R_EP_TYPE   USB_EP3R_EP_TYPE_Msk
 
#define USB_EP3R_EP_TYPE_0   (0x1U << USB_EP3R_EP_TYPE_Pos)
 
#define USB_EP3R_EP_TYPE_1   (0x2U << USB_EP3R_EP_TYPE_Pos)
 
#define USB_EP3R_SETUP_Pos   (11U)
 
#define USB_EP3R_SETUP_Msk   (0x1U << USB_EP3R_SETUP_Pos)
 
#define USB_EP3R_SETUP   USB_EP3R_SETUP_Msk
 
#define USB_EP3R_STAT_RX_Pos   (12U)
 
#define USB_EP3R_STAT_RX_Msk   (0x3U << USB_EP3R_STAT_RX_Pos)
 
#define USB_EP3R_STAT_RX   USB_EP3R_STAT_RX_Msk
 
#define USB_EP3R_STAT_RX_0   (0x1U << USB_EP3R_STAT_RX_Pos)
 
#define USB_EP3R_STAT_RX_1   (0x2U << USB_EP3R_STAT_RX_Pos)
 
#define USB_EP3R_DTOG_RX_Pos   (14U)
 
#define USB_EP3R_DTOG_RX_Msk   (0x1U << USB_EP3R_DTOG_RX_Pos)
 
#define USB_EP3R_DTOG_RX   USB_EP3R_DTOG_RX_Msk
 
#define USB_EP3R_CTR_RX_Pos   (15U)
 
#define USB_EP3R_CTR_RX_Msk   (0x1U << USB_EP3R_CTR_RX_Pos)
 
#define USB_EP3R_CTR_RX   USB_EP3R_CTR_RX_Msk
 
#define USB_EP4R_EA_Pos   (0U)
 
#define USB_EP4R_EA_Msk   (0xFU << USB_EP4R_EA_Pos)
 
#define USB_EP4R_EA   USB_EP4R_EA_Msk
 
#define USB_EP4R_STAT_TX_Pos   (4U)
 
#define USB_EP4R_STAT_TX_Msk   (0x3U << USB_EP4R_STAT_TX_Pos)
 
#define USB_EP4R_STAT_TX   USB_EP4R_STAT_TX_Msk
 
#define USB_EP4R_STAT_TX_0   (0x1U << USB_EP4R_STAT_TX_Pos)
 
#define USB_EP4R_STAT_TX_1   (0x2U << USB_EP4R_STAT_TX_Pos)
 
#define USB_EP4R_DTOG_TX_Pos   (6U)
 
#define USB_EP4R_DTOG_TX_Msk   (0x1U << USB_EP4R_DTOG_TX_Pos)
 
#define USB_EP4R_DTOG_TX   USB_EP4R_DTOG_TX_Msk
 
#define USB_EP4R_CTR_TX_Pos   (7U)
 
#define USB_EP4R_CTR_TX_Msk   (0x1U << USB_EP4R_CTR_TX_Pos)
 
#define USB_EP4R_CTR_TX   USB_EP4R_CTR_TX_Msk
 
#define USB_EP4R_EP_KIND_Pos   (8U)
 
#define USB_EP4R_EP_KIND_Msk   (0x1U << USB_EP4R_EP_KIND_Pos)
 
#define USB_EP4R_EP_KIND   USB_EP4R_EP_KIND_Msk
 
#define USB_EP4R_EP_TYPE_Pos   (9U)
 
#define USB_EP4R_EP_TYPE_Msk   (0x3U << USB_EP4R_EP_TYPE_Pos)
 
#define USB_EP4R_EP_TYPE   USB_EP4R_EP_TYPE_Msk
 
#define USB_EP4R_EP_TYPE_0   (0x1U << USB_EP4R_EP_TYPE_Pos)
 
#define USB_EP4R_EP_TYPE_1   (0x2U << USB_EP4R_EP_TYPE_Pos)
 
#define USB_EP4R_SETUP_Pos   (11U)
 
#define USB_EP4R_SETUP_Msk   (0x1U << USB_EP4R_SETUP_Pos)
 
#define USB_EP4R_SETUP   USB_EP4R_SETUP_Msk
 
#define USB_EP4R_STAT_RX_Pos   (12U)
 
#define USB_EP4R_STAT_RX_Msk   (0x3U << USB_EP4R_STAT_RX_Pos)
 
#define USB_EP4R_STAT_RX   USB_EP4R_STAT_RX_Msk
 
#define USB_EP4R_STAT_RX_0   (0x1U << USB_EP4R_STAT_RX_Pos)
 
#define USB_EP4R_STAT_RX_1   (0x2U << USB_EP4R_STAT_RX_Pos)
 
#define USB_EP4R_DTOG_RX_Pos   (14U)
 
#define USB_EP4R_DTOG_RX_Msk   (0x1U << USB_EP4R_DTOG_RX_Pos)
 
#define USB_EP4R_DTOG_RX   USB_EP4R_DTOG_RX_Msk
 
#define USB_EP4R_CTR_RX_Pos   (15U)
 
#define USB_EP4R_CTR_RX_Msk   (0x1U << USB_EP4R_CTR_RX_Pos)
 
#define USB_EP4R_CTR_RX   USB_EP4R_CTR_RX_Msk
 
#define USB_EP5R_EA_Pos   (0U)
 
#define USB_EP5R_EA_Msk   (0xFU << USB_EP5R_EA_Pos)
 
#define USB_EP5R_EA   USB_EP5R_EA_Msk
 
#define USB_EP5R_STAT_TX_Pos   (4U)
 
#define USB_EP5R_STAT_TX_Msk   (0x3U << USB_EP5R_STAT_TX_Pos)
 
#define USB_EP5R_STAT_TX   USB_EP5R_STAT_TX_Msk
 
#define USB_EP5R_STAT_TX_0   (0x1U << USB_EP5R_STAT_TX_Pos)
 
#define USB_EP5R_STAT_TX_1   (0x2U << USB_EP5R_STAT_TX_Pos)
 
#define USB_EP5R_DTOG_TX_Pos   (6U)
 
#define USB_EP5R_DTOG_TX_Msk   (0x1U << USB_EP5R_DTOG_TX_Pos)
 
#define USB_EP5R_DTOG_TX   USB_EP5R_DTOG_TX_Msk
 
#define USB_EP5R_CTR_TX_Pos   (7U)
 
#define USB_EP5R_CTR_TX_Msk   (0x1U << USB_EP5R_CTR_TX_Pos)
 
#define USB_EP5R_CTR_TX   USB_EP5R_CTR_TX_Msk
 
#define USB_EP5R_EP_KIND_Pos   (8U)
 
#define USB_EP5R_EP_KIND_Msk   (0x1U << USB_EP5R_EP_KIND_Pos)
 
#define USB_EP5R_EP_KIND   USB_EP5R_EP_KIND_Msk
 
#define USB_EP5R_EP_TYPE_Pos   (9U)
 
#define USB_EP5R_EP_TYPE_Msk   (0x3U << USB_EP5R_EP_TYPE_Pos)
 
#define USB_EP5R_EP_TYPE   USB_EP5R_EP_TYPE_Msk
 
#define USB_EP5R_EP_TYPE_0   (0x1U << USB_EP5R_EP_TYPE_Pos)
 
#define USB_EP5R_EP_TYPE_1   (0x2U << USB_EP5R_EP_TYPE_Pos)
 
#define USB_EP5R_SETUP_Pos   (11U)
 
#define USB_EP5R_SETUP_Msk   (0x1U << USB_EP5R_SETUP_Pos)
 
#define USB_EP5R_SETUP   USB_EP5R_SETUP_Msk
 
#define USB_EP5R_STAT_RX_Pos   (12U)
 
#define USB_EP5R_STAT_RX_Msk   (0x3U << USB_EP5R_STAT_RX_Pos)
 
#define USB_EP5R_STAT_RX   USB_EP5R_STAT_RX_Msk
 
#define USB_EP5R_STAT_RX_0   (0x1U << USB_EP5R_STAT_RX_Pos)
 
#define USB_EP5R_STAT_RX_1   (0x2U << USB_EP5R_STAT_RX_Pos)
 
#define USB_EP5R_DTOG_RX_Pos   (14U)
 
#define USB_EP5R_DTOG_RX_Msk   (0x1U << USB_EP5R_DTOG_RX_Pos)
 
#define USB_EP5R_DTOG_RX   USB_EP5R_DTOG_RX_Msk
 
#define USB_EP5R_CTR_RX_Pos   (15U)
 
#define USB_EP5R_CTR_RX_Msk   (0x1U << USB_EP5R_CTR_RX_Pos)
 
#define USB_EP5R_CTR_RX   USB_EP5R_CTR_RX_Msk
 
#define USB_EP6R_EA_Pos   (0U)
 
#define USB_EP6R_EA_Msk   (0xFU << USB_EP6R_EA_Pos)
 
#define USB_EP6R_EA   USB_EP6R_EA_Msk
 
#define USB_EP6R_STAT_TX_Pos   (4U)
 
#define USB_EP6R_STAT_TX_Msk   (0x3U << USB_EP6R_STAT_TX_Pos)
 
#define USB_EP6R_STAT_TX   USB_EP6R_STAT_TX_Msk
 
#define USB_EP6R_STAT_TX_0   (0x1U << USB_EP6R_STAT_TX_Pos)
 
#define USB_EP6R_STAT_TX_1   (0x2U << USB_EP6R_STAT_TX_Pos)
 
#define USB_EP6R_DTOG_TX_Pos   (6U)
 
#define USB_EP6R_DTOG_TX_Msk   (0x1U << USB_EP6R_DTOG_TX_Pos)
 
#define USB_EP6R_DTOG_TX   USB_EP6R_DTOG_TX_Msk
 
#define USB_EP6R_CTR_TX_Pos   (7U)
 
#define USB_EP6R_CTR_TX_Msk   (0x1U << USB_EP6R_CTR_TX_Pos)
 
#define USB_EP6R_CTR_TX   USB_EP6R_CTR_TX_Msk
 
#define USB_EP6R_EP_KIND_Pos   (8U)
 
#define USB_EP6R_EP_KIND_Msk   (0x1U << USB_EP6R_EP_KIND_Pos)
 
#define USB_EP6R_EP_KIND   USB_EP6R_EP_KIND_Msk
 
#define USB_EP6R_EP_TYPE_Pos   (9U)
 
#define USB_EP6R_EP_TYPE_Msk   (0x3U << USB_EP6R_EP_TYPE_Pos)
 
#define USB_EP6R_EP_TYPE   USB_EP6R_EP_TYPE_Msk
 
#define USB_EP6R_EP_TYPE_0   (0x1U << USB_EP6R_EP_TYPE_Pos)
 
#define USB_EP6R_EP_TYPE_1   (0x2U << USB_EP6R_EP_TYPE_Pos)
 
#define USB_EP6R_SETUP_Pos   (11U)
 
#define USB_EP6R_SETUP_Msk   (0x1U << USB_EP6R_SETUP_Pos)
 
#define USB_EP6R_SETUP   USB_EP6R_SETUP_Msk
 
#define USB_EP6R_STAT_RX_Pos   (12U)
 
#define USB_EP6R_STAT_RX_Msk   (0x3U << USB_EP6R_STAT_RX_Pos)
 
#define USB_EP6R_STAT_RX   USB_EP6R_STAT_RX_Msk
 
#define USB_EP6R_STAT_RX_0   (0x1U << USB_EP6R_STAT_RX_Pos)
 
#define USB_EP6R_STAT_RX_1   (0x2U << USB_EP6R_STAT_RX_Pos)
 
#define USB_EP6R_DTOG_RX_Pos   (14U)
 
#define USB_EP6R_DTOG_RX_Msk   (0x1U << USB_EP6R_DTOG_RX_Pos)
 
#define USB_EP6R_DTOG_RX   USB_EP6R_DTOG_RX_Msk
 
#define USB_EP6R_CTR_RX_Pos   (15U)
 
#define USB_EP6R_CTR_RX_Msk   (0x1U << USB_EP6R_CTR_RX_Pos)
 
#define USB_EP6R_CTR_RX   USB_EP6R_CTR_RX_Msk
 
#define USB_EP7R_EA_Pos   (0U)
 
#define USB_EP7R_EA_Msk   (0xFU << USB_EP7R_EA_Pos)
 
#define USB_EP7R_EA   USB_EP7R_EA_Msk
 
#define USB_EP7R_STAT_TX_Pos   (4U)
 
#define USB_EP7R_STAT_TX_Msk   (0x3U << USB_EP7R_STAT_TX_Pos)
 
#define USB_EP7R_STAT_TX   USB_EP7R_STAT_TX_Msk
 
#define USB_EP7R_STAT_TX_0   (0x1U << USB_EP7R_STAT_TX_Pos)
 
#define USB_EP7R_STAT_TX_1   (0x2U << USB_EP7R_STAT_TX_Pos)
 
#define USB_EP7R_DTOG_TX_Pos   (6U)
 
#define USB_EP7R_DTOG_TX_Msk   (0x1U << USB_EP7R_DTOG_TX_Pos)
 
#define USB_EP7R_DTOG_TX   USB_EP7R_DTOG_TX_Msk
 
#define USB_EP7R_CTR_TX_Pos   (7U)
 
#define USB_EP7R_CTR_TX_Msk   (0x1U << USB_EP7R_CTR_TX_Pos)
 
#define USB_EP7R_CTR_TX   USB_EP7R_CTR_TX_Msk
 
#define USB_EP7R_EP_KIND_Pos   (8U)
 
#define USB_EP7R_EP_KIND_Msk   (0x1U << USB_EP7R_EP_KIND_Pos)
 
#define USB_EP7R_EP_KIND   USB_EP7R_EP_KIND_Msk
 
#define USB_EP7R_EP_TYPE_Pos   (9U)
 
#define USB_EP7R_EP_TYPE_Msk   (0x3U << USB_EP7R_EP_TYPE_Pos)
 
#define USB_EP7R_EP_TYPE   USB_EP7R_EP_TYPE_Msk
 
#define USB_EP7R_EP_TYPE_0   (0x1U << USB_EP7R_EP_TYPE_Pos)
 
#define USB_EP7R_EP_TYPE_1   (0x2U << USB_EP7R_EP_TYPE_Pos)
 
#define USB_EP7R_SETUP_Pos   (11U)
 
#define USB_EP7R_SETUP_Msk   (0x1U << USB_EP7R_SETUP_Pos)
 
#define USB_EP7R_SETUP   USB_EP7R_SETUP_Msk
 
#define USB_EP7R_STAT_RX_Pos   (12U)
 
#define USB_EP7R_STAT_RX_Msk   (0x3U << USB_EP7R_STAT_RX_Pos)
 
#define USB_EP7R_STAT_RX   USB_EP7R_STAT_RX_Msk
 
#define USB_EP7R_STAT_RX_0   (0x1U << USB_EP7R_STAT_RX_Pos)
 
#define USB_EP7R_STAT_RX_1   (0x2U << USB_EP7R_STAT_RX_Pos)
 
#define USB_EP7R_DTOG_RX_Pos   (14U)
 
#define USB_EP7R_DTOG_RX_Msk   (0x1U << USB_EP7R_DTOG_RX_Pos)
 
#define USB_EP7R_DTOG_RX   USB_EP7R_DTOG_RX_Msk
 
#define USB_EP7R_CTR_RX_Pos   (15U)
 
#define USB_EP7R_CTR_RX_Msk   (0x1U << USB_EP7R_CTR_RX_Pos)
 
#define USB_EP7R_CTR_RX   USB_EP7R_CTR_RX_Msk
 
#define USB_CNTR   (USB_BASE + 0x00000040U)
 
#define USB_ISTR   (USB_BASE + 0x00000044U)
 
#define USB_FNR   (USB_BASE + 0x00000048U)
 
#define USB_DADDR   (USB_BASE + 0x0000004CU)
 
#define USB_BTABLE   (USB_BASE + 0x00000050U)
 
#define USB_CNTR_FRES_Pos   (0U)
 
#define USB_CNTR_FRES_Msk   (0x1U << USB_CNTR_FRES_Pos)
 
#define USB_CNTR_FRES   USB_CNTR_FRES_Msk
 
#define USB_CNTR_PDWN_Pos   (1U)
 
#define USB_CNTR_PDWN_Msk   (0x1U << USB_CNTR_PDWN_Pos)
 
#define USB_CNTR_PDWN   USB_CNTR_PDWN_Msk
 
#define USB_CNTR_LPMODE_Pos   (2U)
 
#define USB_CNTR_LPMODE_Msk   (0x1U << USB_CNTR_LPMODE_Pos)
 
#define USB_CNTR_LPMODE   USB_CNTR_LPMODE_Msk
 
#define USB_CNTR_FSUSP_Pos   (3U)
 
#define USB_CNTR_FSUSP_Msk   (0x1U << USB_CNTR_FSUSP_Pos)
 
#define USB_CNTR_FSUSP   USB_CNTR_FSUSP_Msk
 
#define USB_CNTR_RESUME_Pos   (4U)
 
#define USB_CNTR_RESUME_Msk   (0x1U << USB_CNTR_RESUME_Pos)
 
#define USB_CNTR_RESUME   USB_CNTR_RESUME_Msk
 
#define USB_CNTR_ESOFM_Pos   (8U)
 
#define USB_CNTR_ESOFM_Msk   (0x1U << USB_CNTR_ESOFM_Pos)
 
#define USB_CNTR_ESOFM   USB_CNTR_ESOFM_Msk
 
#define USB_CNTR_SOFM_Pos   (9U)
 
#define USB_CNTR_SOFM_Msk   (0x1U << USB_CNTR_SOFM_Pos)
 
#define USB_CNTR_SOFM   USB_CNTR_SOFM_Msk
 
#define USB_CNTR_RESETM_Pos   (10U)
 
#define USB_CNTR_RESETM_Msk   (0x1U << USB_CNTR_RESETM_Pos)
 
#define USB_CNTR_RESETM   USB_CNTR_RESETM_Msk
 
#define USB_CNTR_SUSPM_Pos   (11U)
 
#define USB_CNTR_SUSPM_Msk   (0x1U << USB_CNTR_SUSPM_Pos)
 
#define USB_CNTR_SUSPM   USB_CNTR_SUSPM_Msk
 
#define USB_CNTR_WKUPM_Pos   (12U)
 
#define USB_CNTR_WKUPM_Msk   (0x1U << USB_CNTR_WKUPM_Pos)
 
#define USB_CNTR_WKUPM   USB_CNTR_WKUPM_Msk
 
#define USB_CNTR_ERRM_Pos   (13U)
 
#define USB_CNTR_ERRM_Msk   (0x1U << USB_CNTR_ERRM_Pos)
 
#define USB_CNTR_ERRM   USB_CNTR_ERRM_Msk
 
#define USB_CNTR_PMAOVRM_Pos   (14U)
 
#define USB_CNTR_PMAOVRM_Msk   (0x1U << USB_CNTR_PMAOVRM_Pos)
 
#define USB_CNTR_PMAOVRM   USB_CNTR_PMAOVRM_Msk
 
#define USB_CNTR_CTRM_Pos   (15U)
 
#define USB_CNTR_CTRM_Msk   (0x1U << USB_CNTR_CTRM_Pos)
 
#define USB_CNTR_CTRM   USB_CNTR_CTRM_Msk
 
#define USB_ISTR_EP_ID_Pos   (0U)
 
#define USB_ISTR_EP_ID_Msk   (0xFU << USB_ISTR_EP_ID_Pos)
 
#define USB_ISTR_EP_ID   USB_ISTR_EP_ID_Msk
 
#define USB_ISTR_DIR_Pos   (4U)
 
#define USB_ISTR_DIR_Msk   (0x1U << USB_ISTR_DIR_Pos)
 
#define USB_ISTR_DIR   USB_ISTR_DIR_Msk
 
#define USB_ISTR_ESOF_Pos   (8U)
 
#define USB_ISTR_ESOF_Msk   (0x1U << USB_ISTR_ESOF_Pos)
 
#define USB_ISTR_ESOF   USB_ISTR_ESOF_Msk
 
#define USB_ISTR_SOF_Pos   (9U)
 
#define USB_ISTR_SOF_Msk   (0x1U << USB_ISTR_SOF_Pos)
 
#define USB_ISTR_SOF   USB_ISTR_SOF_Msk
 
#define USB_ISTR_RESET_Pos   (10U)
 
#define USB_ISTR_RESET_Msk   (0x1U << USB_ISTR_RESET_Pos)
 
#define USB_ISTR_RESET   USB_ISTR_RESET_Msk
 
#define USB_ISTR_SUSP_Pos   (11U)
 
#define USB_ISTR_SUSP_Msk   (0x1U << USB_ISTR_SUSP_Pos)
 
#define USB_ISTR_SUSP   USB_ISTR_SUSP_Msk
 
#define USB_ISTR_WKUP_Pos   (12U)
 
#define USB_ISTR_WKUP_Msk   (0x1U << USB_ISTR_WKUP_Pos)
 
#define USB_ISTR_WKUP   USB_ISTR_WKUP_Msk
 
#define USB_ISTR_ERR_Pos   (13U)
 
#define USB_ISTR_ERR_Msk   (0x1U << USB_ISTR_ERR_Pos)
 
#define USB_ISTR_ERR   USB_ISTR_ERR_Msk
 
#define USB_ISTR_PMAOVR_Pos   (14U)
 
#define USB_ISTR_PMAOVR_Msk   (0x1U << USB_ISTR_PMAOVR_Pos)
 
#define USB_ISTR_PMAOVR   USB_ISTR_PMAOVR_Msk
 
#define USB_ISTR_CTR_Pos   (15U)
 
#define USB_ISTR_CTR_Msk   (0x1U << USB_ISTR_CTR_Pos)
 
#define USB_ISTR_CTR   USB_ISTR_CTR_Msk
 
#define USB_CLR_CTR   (~USB_ISTR_CTR)
 
#define USB_CLR_PMAOVRM   (~USB_ISTR_PMAOVR)
 
#define USB_CLR_ERR   (~USB_ISTR_ERR)
 
#define USB_CLR_WKUP   (~USB_ISTR_WKUP)
 
#define USB_CLR_SUSP   (~USB_ISTR_SUSP)
 
#define USB_CLR_RESET   (~USB_ISTR_RESET)
 
#define USB_CLR_SOF   (~USB_ISTR_SOF)
 
#define USB_CLR_ESOF   (~USB_ISTR_ESOF)
 
#define USB_FNR_FN_Pos   (0U)
 
#define USB_FNR_FN_Msk   (0x7FFU << USB_FNR_FN_Pos)
 
#define USB_FNR_FN   USB_FNR_FN_Msk
 
#define USB_FNR_LSOF_Pos   (11U)
 
#define USB_FNR_LSOF_Msk   (0x3U << USB_FNR_LSOF_Pos)
 
#define USB_FNR_LSOF   USB_FNR_LSOF_Msk
 
#define USB_FNR_LCK_Pos   (13U)
 
#define USB_FNR_LCK_Msk   (0x1U << USB_FNR_LCK_Pos)
 
#define USB_FNR_LCK   USB_FNR_LCK_Msk
 
#define USB_FNR_RXDM_Pos   (14U)
 
#define USB_FNR_RXDM_Msk   (0x1U << USB_FNR_RXDM_Pos)
 
#define USB_FNR_RXDM   USB_FNR_RXDM_Msk
 
#define USB_FNR_RXDP_Pos   (15U)
 
#define USB_FNR_RXDP_Msk   (0x1U << USB_FNR_RXDP_Pos)
 
#define USB_FNR_RXDP   USB_FNR_RXDP_Msk
 
#define USB_DADDR_ADD_Pos   (0U)
 
#define USB_DADDR_ADD_Msk   (0x7FU << USB_DADDR_ADD_Pos)
 
#define USB_DADDR_ADD   USB_DADDR_ADD_Msk
 
#define USB_DADDR_ADD0_Pos   (0U)
 
#define USB_DADDR_ADD0_Msk   (0x1U << USB_DADDR_ADD0_Pos)
 
#define USB_DADDR_ADD0   USB_DADDR_ADD0_Msk
 
#define USB_DADDR_ADD1_Pos   (1U)
 
#define USB_DADDR_ADD1_Msk   (0x1U << USB_DADDR_ADD1_Pos)
 
#define USB_DADDR_ADD1   USB_DADDR_ADD1_Msk
 
#define USB_DADDR_ADD2_Pos   (2U)
 
#define USB_DADDR_ADD2_Msk   (0x1U << USB_DADDR_ADD2_Pos)
 
#define USB_DADDR_ADD2   USB_DADDR_ADD2_Msk
 
#define USB_DADDR_ADD3_Pos   (3U)
 
#define USB_DADDR_ADD3_Msk   (0x1U << USB_DADDR_ADD3_Pos)
 
#define USB_DADDR_ADD3   USB_DADDR_ADD3_Msk
 
#define USB_DADDR_ADD4_Pos   (4U)
 
#define USB_DADDR_ADD4_Msk   (0x1U << USB_DADDR_ADD4_Pos)
 
#define USB_DADDR_ADD4   USB_DADDR_ADD4_Msk
 
#define USB_DADDR_ADD5_Pos   (5U)
 
#define USB_DADDR_ADD5_Msk   (0x1U << USB_DADDR_ADD5_Pos)
 
#define USB_DADDR_ADD5   USB_DADDR_ADD5_Msk
 
#define USB_DADDR_ADD6_Pos   (6U)
 
#define USB_DADDR_ADD6_Msk   (0x1U << USB_DADDR_ADD6_Pos)
 
#define USB_DADDR_ADD6   USB_DADDR_ADD6_Msk
 
#define USB_DADDR_EF_Pos   (7U)
 
#define USB_DADDR_EF_Msk   (0x1U << USB_DADDR_EF_Pos)
 
#define USB_DADDR_EF   USB_DADDR_EF_Msk
 
#define USB_BTABLE_BTABLE_Pos   (3U)
 
#define USB_BTABLE_BTABLE_Msk   (0x1FFFU << USB_BTABLE_BTABLE_Pos)
 
#define USB_BTABLE_BTABLE   USB_BTABLE_BTABLE_Msk
 
#define USB_ADDR0_TX_ADDR0_TX_Pos   (1U)
 
#define USB_ADDR0_TX_ADDR0_TX_Msk   (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos)
 
#define USB_ADDR0_TX_ADDR0_TX   USB_ADDR0_TX_ADDR0_TX_Msk
 
#define USB_ADDR1_TX_ADDR1_TX_Pos   (1U)
 
#define USB_ADDR1_TX_ADDR1_TX_Msk   (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos)
 
#define USB_ADDR1_TX_ADDR1_TX   USB_ADDR1_TX_ADDR1_TX_Msk
 
#define USB_ADDR2_TX_ADDR2_TX_Pos   (1U)
 
#define USB_ADDR2_TX_ADDR2_TX_Msk   (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos)
 
#define USB_ADDR2_TX_ADDR2_TX   USB_ADDR2_TX_ADDR2_TX_Msk
 
#define USB_ADDR3_TX_ADDR3_TX_Pos   (1U)
 
#define USB_ADDR3_TX_ADDR3_TX_Msk   (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos)
 
#define USB_ADDR3_TX_ADDR3_TX   USB_ADDR3_TX_ADDR3_TX_Msk
 
#define USB_ADDR4_TX_ADDR4_TX_Pos   (1U)
 
#define USB_ADDR4_TX_ADDR4_TX_Msk   (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos)
 
#define USB_ADDR4_TX_ADDR4_TX   USB_ADDR4_TX_ADDR4_TX_Msk
 
#define USB_ADDR5_TX_ADDR5_TX_Pos   (1U)
 
#define USB_ADDR5_TX_ADDR5_TX_Msk   (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos)
 
#define USB_ADDR5_TX_ADDR5_TX   USB_ADDR5_TX_ADDR5_TX_Msk
 
#define USB_ADDR6_TX_ADDR6_TX_Pos   (1U)
 
#define USB_ADDR6_TX_ADDR6_TX_Msk   (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos)
 
#define USB_ADDR6_TX_ADDR6_TX   USB_ADDR6_TX_ADDR6_TX_Msk
 
#define USB_ADDR7_TX_ADDR7_TX_Pos   (1U)
 
#define USB_ADDR7_TX_ADDR7_TX_Msk   (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos)
 
#define USB_ADDR7_TX_ADDR7_TX   USB_ADDR7_TX_ADDR7_TX_Msk
 
#define USB_COUNT0_TX_COUNT0_TX_Pos   (0U)
 
#define USB_COUNT0_TX_COUNT0_TX_Msk   (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos)
 
#define USB_COUNT0_TX_COUNT0_TX   USB_COUNT0_TX_COUNT0_TX_Msk
 
#define USB_COUNT1_TX_COUNT1_TX_Pos   (0U)
 
#define USB_COUNT1_TX_COUNT1_TX_Msk   (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos)
 
#define USB_COUNT1_TX_COUNT1_TX   USB_COUNT1_TX_COUNT1_TX_Msk
 
#define USB_COUNT2_TX_COUNT2_TX_Pos   (0U)
 
#define USB_COUNT2_TX_COUNT2_TX_Msk   (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos)
 
#define USB_COUNT2_TX_COUNT2_TX   USB_COUNT2_TX_COUNT2_TX_Msk
 
#define USB_COUNT3_TX_COUNT3_TX_Pos   (0U)
 
#define USB_COUNT3_TX_COUNT3_TX_Msk   (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos)
 
#define USB_COUNT3_TX_COUNT3_TX   USB_COUNT3_TX_COUNT3_TX_Msk
 
#define USB_COUNT4_TX_COUNT4_TX_Pos   (0U)
 
#define USB_COUNT4_TX_COUNT4_TX_Msk   (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos)
 
#define USB_COUNT4_TX_COUNT4_TX   USB_COUNT4_TX_COUNT4_TX_Msk
 
#define USB_COUNT5_TX_COUNT5_TX_Pos   (0U)
 
#define USB_COUNT5_TX_COUNT5_TX_Msk   (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos)
 
#define USB_COUNT5_TX_COUNT5_TX   USB_COUNT5_TX_COUNT5_TX_Msk
 
#define USB_COUNT6_TX_COUNT6_TX_Pos   (0U)
 
#define USB_COUNT6_TX_COUNT6_TX_Msk   (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos)
 
#define USB_COUNT6_TX_COUNT6_TX   USB_COUNT6_TX_COUNT6_TX_Msk
 
#define USB_COUNT7_TX_COUNT7_TX_Pos   (0U)
 
#define USB_COUNT7_TX_COUNT7_TX_Msk   (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos)
 
#define USB_COUNT7_TX_COUNT7_TX   USB_COUNT7_TX_COUNT7_TX_Msk
 
#define USB_COUNT0_TX_0_COUNT0_TX_0   (0x000003FFU)
 
#define USB_COUNT0_TX_1_COUNT0_TX_1   (0x03FF0000U)
 
#define USB_COUNT1_TX_0_COUNT1_TX_0   (0x000003FFU)
 
#define USB_COUNT1_TX_1_COUNT1_TX_1   (0x03FF0000U)
 
#define USB_COUNT2_TX_0_COUNT2_TX_0   (0x000003FFU)
 
#define USB_COUNT2_TX_1_COUNT2_TX_1   (0x03FF0000U)
 
#define USB_COUNT3_TX_0_COUNT3_TX_0   ((uint32_t)0x00000000U03FF)
 
#define USB_COUNT3_TX_1_COUNT3_TX_1   ((uint32_t)0x000003FFU0000)
 
#define USB_COUNT4_TX_0_COUNT4_TX_0   (0x000003FFU)
 
#define USB_COUNT4_TX_1_COUNT4_TX_1   (0x03FF0000U)
 
#define USB_COUNT5_TX_0_COUNT5_TX_0   (0x000003FFU)
 
#define USB_COUNT5_TX_1_COUNT5_TX_1   (0x03FF0000U)
 
#define USB_COUNT6_TX_0_COUNT6_TX_0   (0x000003FFU)
 
#define USB_COUNT6_TX_1_COUNT6_TX_1   (0x03FF0000U)
 
#define USB_COUNT7_TX_0_COUNT7_TX_0   (0x000003FFU)
 
#define USB_COUNT7_TX_1_COUNT7_TX_1   (0x03FF0000U)
 
#define USB_ADDR0_RX_ADDR0_RX_Pos   (1U)
 
#define USB_ADDR0_RX_ADDR0_RX_Msk   (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos)
 
#define USB_ADDR0_RX_ADDR0_RX   USB_ADDR0_RX_ADDR0_RX_Msk
 
#define USB_ADDR1_RX_ADDR1_RX_Pos   (1U)
 
#define USB_ADDR1_RX_ADDR1_RX_Msk   (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos)
 
#define USB_ADDR1_RX_ADDR1_RX   USB_ADDR1_RX_ADDR1_RX_Msk
 
#define USB_ADDR2_RX_ADDR2_RX_Pos   (1U)
 
#define USB_ADDR2_RX_ADDR2_RX_Msk   (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos)
 
#define USB_ADDR2_RX_ADDR2_RX   USB_ADDR2_RX_ADDR2_RX_Msk
 
#define USB_ADDR3_RX_ADDR3_RX_Pos   (1U)
 
#define USB_ADDR3_RX_ADDR3_RX_Msk   (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos)
 
#define USB_ADDR3_RX_ADDR3_RX   USB_ADDR3_RX_ADDR3_RX_Msk
 
#define USB_ADDR4_RX_ADDR4_RX_Pos   (1U)
 
#define USB_ADDR4_RX_ADDR4_RX_Msk   (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos)
 
#define USB_ADDR4_RX_ADDR4_RX   USB_ADDR4_RX_ADDR4_RX_Msk
 
#define USB_ADDR5_RX_ADDR5_RX_Pos   (1U)
 
#define USB_ADDR5_RX_ADDR5_RX_Msk   (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos)
 
#define USB_ADDR5_RX_ADDR5_RX   USB_ADDR5_RX_ADDR5_RX_Msk
 
#define USB_ADDR6_RX_ADDR6_RX_Pos   (1U)
 
#define USB_ADDR6_RX_ADDR6_RX_Msk   (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos)
 
#define USB_ADDR6_RX_ADDR6_RX   USB_ADDR6_RX_ADDR6_RX_Msk
 
#define USB_ADDR7_RX_ADDR7_RX_Pos   (1U)
 
#define USB_ADDR7_RX_ADDR7_RX_Msk   (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos)
 
#define USB_ADDR7_RX_ADDR7_RX   USB_ADDR7_RX_ADDR7_RX_Msk
 
#define USB_COUNT0_RX_COUNT0_RX_Pos   (0U)
 
#define USB_COUNT0_RX_COUNT0_RX_Msk   (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos)
 
#define USB_COUNT0_RX_COUNT0_RX   USB_COUNT0_RX_COUNT0_RX_Msk
 
#define USB_COUNT0_RX_NUM_BLOCK_Pos   (10U)
 
#define USB_COUNT0_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT0_RX_NUM_BLOCK   USB_COUNT0_RX_NUM_BLOCK_Msk
 
#define USB_COUNT0_RX_NUM_BLOCK_0   (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT0_RX_NUM_BLOCK_1   (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT0_RX_NUM_BLOCK_2   (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT0_RX_NUM_BLOCK_3   (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT0_RX_NUM_BLOCK_4   (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT0_RX_BLSIZE_Pos   (15U)
 
#define USB_COUNT0_RX_BLSIZE_Msk   (0x1U << USB_COUNT0_RX_BLSIZE_Pos)
 
#define USB_COUNT0_RX_BLSIZE   USB_COUNT0_RX_BLSIZE_Msk
 
#define USB_COUNT1_RX_COUNT1_RX_Pos   (0U)
 
#define USB_COUNT1_RX_COUNT1_RX_Msk   (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos)
 
#define USB_COUNT1_RX_COUNT1_RX   USB_COUNT1_RX_COUNT1_RX_Msk
 
#define USB_COUNT1_RX_NUM_BLOCK_Pos   (10U)
 
#define USB_COUNT1_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT1_RX_NUM_BLOCK   USB_COUNT1_RX_NUM_BLOCK_Msk
 
#define USB_COUNT1_RX_NUM_BLOCK_0   (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT1_RX_NUM_BLOCK_1   (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT1_RX_NUM_BLOCK_2   (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT1_RX_NUM_BLOCK_3   (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT1_RX_NUM_BLOCK_4   (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT1_RX_BLSIZE_Pos   (15U)
 
#define USB_COUNT1_RX_BLSIZE_Msk   (0x1U << USB_COUNT1_RX_BLSIZE_Pos)
 
#define USB_COUNT1_RX_BLSIZE   USB_COUNT1_RX_BLSIZE_Msk
 
#define USB_COUNT2_RX_COUNT2_RX_Pos   (0U)
 
#define USB_COUNT2_RX_COUNT2_RX_Msk   (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos)
 
#define USB_COUNT2_RX_COUNT2_RX   USB_COUNT2_RX_COUNT2_RX_Msk
 
#define USB_COUNT2_RX_NUM_BLOCK_Pos   (10U)
 
#define USB_COUNT2_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT2_RX_NUM_BLOCK   USB_COUNT2_RX_NUM_BLOCK_Msk
 
#define USB_COUNT2_RX_NUM_BLOCK_0   (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT2_RX_NUM_BLOCK_1   (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT2_RX_NUM_BLOCK_2   (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT2_RX_NUM_BLOCK_3   (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT2_RX_NUM_BLOCK_4   (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT2_RX_BLSIZE_Pos   (15U)
 
#define USB_COUNT2_RX_BLSIZE_Msk   (0x1U << USB_COUNT2_RX_BLSIZE_Pos)
 
#define USB_COUNT2_RX_BLSIZE   USB_COUNT2_RX_BLSIZE_Msk
 
#define USB_COUNT3_RX_COUNT3_RX_Pos   (0U)
 
#define USB_COUNT3_RX_COUNT3_RX_Msk   (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos)
 
#define USB_COUNT3_RX_COUNT3_RX   USB_COUNT3_RX_COUNT3_RX_Msk
 
#define USB_COUNT3_RX_NUM_BLOCK_Pos   (10U)
 
#define USB_COUNT3_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT3_RX_NUM_BLOCK   USB_COUNT3_RX_NUM_BLOCK_Msk
 
#define USB_COUNT3_RX_NUM_BLOCK_0   (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT3_RX_NUM_BLOCK_1   (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT3_RX_NUM_BLOCK_2   (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT3_RX_NUM_BLOCK_3   (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT3_RX_NUM_BLOCK_4   (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT3_RX_BLSIZE_Pos   (15U)
 
#define USB_COUNT3_RX_BLSIZE_Msk   (0x1U << USB_COUNT3_RX_BLSIZE_Pos)
 
#define USB_COUNT3_RX_BLSIZE   USB_COUNT3_RX_BLSIZE_Msk
 
#define USB_COUNT4_RX_COUNT4_RX_Pos   (0U)
 
#define USB_COUNT4_RX_COUNT4_RX_Msk   (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos)
 
#define USB_COUNT4_RX_COUNT4_RX   USB_COUNT4_RX_COUNT4_RX_Msk
 
#define USB_COUNT4_RX_NUM_BLOCK_Pos   (10U)
 
#define USB_COUNT4_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT4_RX_NUM_BLOCK   USB_COUNT4_RX_NUM_BLOCK_Msk
 
#define USB_COUNT4_RX_NUM_BLOCK_0   (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT4_RX_NUM_BLOCK_1   (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT4_RX_NUM_BLOCK_2   (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT4_RX_NUM_BLOCK_3   (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT4_RX_NUM_BLOCK_4   (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT4_RX_BLSIZE_Pos   (15U)
 
#define USB_COUNT4_RX_BLSIZE_Msk   (0x1U << USB_COUNT4_RX_BLSIZE_Pos)
 
#define USB_COUNT4_RX_BLSIZE   USB_COUNT4_RX_BLSIZE_Msk
 
#define USB_COUNT5_RX_COUNT5_RX_Pos   (0U)
 
#define USB_COUNT5_RX_COUNT5_RX_Msk   (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos)
 
#define USB_COUNT5_RX_COUNT5_RX   USB_COUNT5_RX_COUNT5_RX_Msk
 
#define USB_COUNT5_RX_NUM_BLOCK_Pos   (10U)
 
#define USB_COUNT5_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT5_RX_NUM_BLOCK   USB_COUNT5_RX_NUM_BLOCK_Msk
 
#define USB_COUNT5_RX_NUM_BLOCK_0   (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT5_RX_NUM_BLOCK_1   (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT5_RX_NUM_BLOCK_2   (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT5_RX_NUM_BLOCK_3   (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT5_RX_NUM_BLOCK_4   (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT5_RX_BLSIZE_Pos   (15U)
 
#define USB_COUNT5_RX_BLSIZE_Msk   (0x1U << USB_COUNT5_RX_BLSIZE_Pos)
 
#define USB_COUNT5_RX_BLSIZE   USB_COUNT5_RX_BLSIZE_Msk
 
#define USB_COUNT6_RX_COUNT6_RX_Pos   (0U)
 
#define USB_COUNT6_RX_COUNT6_RX_Msk   (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos)
 
#define USB_COUNT6_RX_COUNT6_RX   USB_COUNT6_RX_COUNT6_RX_Msk
 
#define USB_COUNT6_RX_NUM_BLOCK_Pos   (10U)
 
#define USB_COUNT6_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT6_RX_NUM_BLOCK   USB_COUNT6_RX_NUM_BLOCK_Msk
 
#define USB_COUNT6_RX_NUM_BLOCK_0   (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT6_RX_NUM_BLOCK_1   (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT6_RX_NUM_BLOCK_2   (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT6_RX_NUM_BLOCK_3   (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT6_RX_NUM_BLOCK_4   (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT6_RX_BLSIZE_Pos   (15U)
 
#define USB_COUNT6_RX_BLSIZE_Msk   (0x1U << USB_COUNT6_RX_BLSIZE_Pos)
 
#define USB_COUNT6_RX_BLSIZE   USB_COUNT6_RX_BLSIZE_Msk
 
#define USB_COUNT7_RX_COUNT7_RX_Pos   (0U)
 
#define USB_COUNT7_RX_COUNT7_RX_Msk   (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos)
 
#define USB_COUNT7_RX_COUNT7_RX   USB_COUNT7_RX_COUNT7_RX_Msk
 
#define USB_COUNT7_RX_NUM_BLOCK_Pos   (10U)
 
#define USB_COUNT7_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT7_RX_NUM_BLOCK   USB_COUNT7_RX_NUM_BLOCK_Msk
 
#define USB_COUNT7_RX_NUM_BLOCK_0   (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT7_RX_NUM_BLOCK_1   (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT7_RX_NUM_BLOCK_2   (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT7_RX_NUM_BLOCK_3   (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT7_RX_NUM_BLOCK_4   (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos)
 
#define USB_COUNT7_RX_BLSIZE_Pos   (15U)
 
#define USB_COUNT7_RX_BLSIZE_Msk   (0x1U << USB_COUNT7_RX_BLSIZE_Pos)
 
#define USB_COUNT7_RX_BLSIZE   USB_COUNT7_RX_BLSIZE_Msk
 
#define USB_COUNT0_RX_0_COUNT0_RX_0   (0x000003FFU)
 
#define USB_COUNT0_RX_0_NUM_BLOCK_0   (0x00007C00U)
 
#define USB_COUNT0_RX_0_NUM_BLOCK_0_0   (0x00000400U)
 
#define USB_COUNT0_RX_0_NUM_BLOCK_0_1   (0x00000800U)
 
#define USB_COUNT0_RX_0_NUM_BLOCK_0_2   (0x00001000U)
 
#define USB_COUNT0_RX_0_NUM_BLOCK_0_3   (0x00002000U)
 
#define USB_COUNT0_RX_0_NUM_BLOCK_0_4   (0x00004000U)
 
#define USB_COUNT0_RX_0_BLSIZE_0   (0x00008000U)
 
#define USB_COUNT0_RX_1_COUNT0_RX_1   (0x03FF0000U)
 
#define USB_COUNT0_RX_1_NUM_BLOCK_1   (0x7C000000U)
 
#define USB_COUNT0_RX_1_NUM_BLOCK_1_0   (0x04000000U)
 
#define USB_COUNT0_RX_1_NUM_BLOCK_1_1   (0x08000000U)
 
#define USB_COUNT0_RX_1_NUM_BLOCK_1_2   (0x10000000U)
 
#define USB_COUNT0_RX_1_NUM_BLOCK_1_3   (0x20000000U)
 
#define USB_COUNT0_RX_1_NUM_BLOCK_1_4   (0x40000000U)
 
#define USB_COUNT0_RX_1_BLSIZE_1   (0x80000000U)
 
#define USB_COUNT1_RX_0_COUNT1_RX_0   (0x000003FFU)
 
#define USB_COUNT1_RX_0_NUM_BLOCK_0   (0x00007C00U)
 
#define USB_COUNT1_RX_0_NUM_BLOCK_0_0   (0x00000400U)
 
#define USB_COUNT1_RX_0_NUM_BLOCK_0_1   (0x00000800U)
 
#define USB_COUNT1_RX_0_NUM_BLOCK_0_2   (0x00001000U)
 
#define USB_COUNT1_RX_0_NUM_BLOCK_0_3   (0x00002000U)
 
#define USB_COUNT1_RX_0_NUM_BLOCK_0_4   (0x00004000U)
 
#define USB_COUNT1_RX_0_BLSIZE_0   (0x00008000U)
 
#define USB_COUNT1_RX_1_COUNT1_RX_1   (0x03FF0000U)
 
#define USB_COUNT1_RX_1_NUM_BLOCK_1   (0x7C000000U)
 
#define USB_COUNT1_RX_1_NUM_BLOCK_1_0   (0x04000000U)
 
#define USB_COUNT1_RX_1_NUM_BLOCK_1_1   (0x08000000U)
 
#define USB_COUNT1_RX_1_NUM_BLOCK_1_2   (0x10000000U)
 
#define USB_COUNT1_RX_1_NUM_BLOCK_1_3   (0x20000000U)
 
#define USB_COUNT1_RX_1_NUM_BLOCK_1_4   (0x40000000U)
 
#define USB_COUNT1_RX_1_BLSIZE_1   (0x80000000U)
 
#define USB_COUNT2_RX_0_COUNT2_RX_0   (0x000003FFU)
 
#define USB_COUNT2_RX_0_NUM_BLOCK_0   (0x00007C00U)
 
#define USB_COUNT2_RX_0_NUM_BLOCK_0_0   (0x00000400U)
 
#define USB_COUNT2_RX_0_NUM_BLOCK_0_1   (0x00000800U)
 
#define USB_COUNT2_RX_0_NUM_BLOCK_0_2   (0x00001000U)
 
#define USB_COUNT2_RX_0_NUM_BLOCK_0_3   (0x00002000U)
 
#define USB_COUNT2_RX_0_NUM_BLOCK_0_4   (0x00004000U)
 
#define USB_COUNT2_RX_0_BLSIZE_0   (0x00008000U)
 
#define USB_COUNT2_RX_1_COUNT2_RX_1   (0x03FF0000U)
 
#define USB_COUNT2_RX_1_NUM_BLOCK_1   (0x7C000000U)
 
#define USB_COUNT2_RX_1_NUM_BLOCK_1_0   (0x04000000U)
 
#define USB_COUNT2_RX_1_NUM_BLOCK_1_1   (0x08000000U)
 
#define USB_COUNT2_RX_1_NUM_BLOCK_1_2   (0x10000000U)
 
#define USB_COUNT2_RX_1_NUM_BLOCK_1_3   (0x20000000U)
 
#define USB_COUNT2_RX_1_NUM_BLOCK_1_4   (0x40000000U)
 
#define USB_COUNT2_RX_1_BLSIZE_1   (0x80000000U)
 
#define USB_COUNT3_RX_0_COUNT3_RX_0   (0x000003FFU)
 
#define USB_COUNT3_RX_0_NUM_BLOCK_0   (0x00007C00U)
 
#define USB_COUNT3_RX_0_NUM_BLOCK_0_0   (0x00000400U)
 
#define USB_COUNT3_RX_0_NUM_BLOCK_0_1   (0x00000800U)
 
#define USB_COUNT3_RX_0_NUM_BLOCK_0_2   (0x00001000U)
 
#define USB_COUNT3_RX_0_NUM_BLOCK_0_3   (0x00002000U)
 
#define USB_COUNT3_RX_0_NUM_BLOCK_0_4   (0x00004000U)
 
#define USB_COUNT3_RX_0_BLSIZE_0   (0x00008000U)
 
#define USB_COUNT3_RX_1_COUNT3_RX_1   (0x03FF0000U)
 
#define USB_COUNT3_RX_1_NUM_BLOCK_1   (0x7C000000U)
 
#define USB_COUNT3_RX_1_NUM_BLOCK_1_0   (0x04000000U)
 
#define USB_COUNT3_RX_1_NUM_BLOCK_1_1   (0x08000000U)
 
#define USB_COUNT3_RX_1_NUM_BLOCK_1_2   (0x10000000U)
 
#define USB_COUNT3_RX_1_NUM_BLOCK_1_3   (0x20000000U)
 
#define USB_COUNT3_RX_1_NUM_BLOCK_1_4   (0x40000000U)
 
#define USB_COUNT3_RX_1_BLSIZE_1   (0x80000000U)
 
#define USB_COUNT4_RX_0_COUNT4_RX_0   (0x000003FFU)
 
#define USB_COUNT4_RX_0_NUM_BLOCK_0   (0x00007C00U)
 
#define USB_COUNT4_RX_0_NUM_BLOCK_0_0   (0x00000400U)
 
#define USB_COUNT4_RX_0_NUM_BLOCK_0_1   (0x00000800U)
 
#define USB_COUNT4_RX_0_NUM_BLOCK_0_2   (0x00001000U)
 
#define USB_COUNT4_RX_0_NUM_BLOCK_0_3   (0x00002000U)
 
#define USB_COUNT4_RX_0_NUM_BLOCK_0_4   (0x00004000U)
 
#define USB_COUNT4_RX_0_BLSIZE_0   (0x00008000U)
 
#define USB_COUNT4_RX_1_COUNT4_RX_1   (0x03FF0000U)
 
#define USB_COUNT4_RX_1_NUM_BLOCK_1   (0x7C000000U)
 
#define USB_COUNT4_RX_1_NUM_BLOCK_1_0   (0x04000000U)
 
#define USB_COUNT4_RX_1_NUM_BLOCK_1_1   (0x08000000U)
 
#define USB_COUNT4_RX_1_NUM_BLOCK_1_2   (0x10000000U)
 
#define USB_COUNT4_RX_1_NUM_BLOCK_1_3   (0x20000000U)
 
#define USB_COUNT4_RX_1_NUM_BLOCK_1_4   (0x40000000U)
 
#define USB_COUNT4_RX_1_BLSIZE_1   (0x80000000U)
 
#define USB_COUNT5_RX_0_COUNT5_RX_0   (0x000003FFU)
 
#define USB_COUNT5_RX_0_NUM_BLOCK_0   (0x00007C00U)
 
#define USB_COUNT5_RX_0_NUM_BLOCK_0_0   (0x00000400U)
 
#define USB_COUNT5_RX_0_NUM_BLOCK_0_1   (0x00000800U)
 
#define USB_COUNT5_RX_0_NUM_BLOCK_0_2   (0x00001000U)
 
#define USB_COUNT5_RX_0_NUM_BLOCK_0_3   (0x00002000U)
 
#define USB_COUNT5_RX_0_NUM_BLOCK_0_4   (0x00004000U)
 
#define USB_COUNT5_RX_0_BLSIZE_0   (0x00008000U)
 
#define USB_COUNT5_RX_1_COUNT5_RX_1   (0x03FF0000U)
 
#define USB_COUNT5_RX_1_NUM_BLOCK_1   (0x7C000000U)
 
#define USB_COUNT5_RX_1_NUM_BLOCK_1_0   (0x04000000U)
 
#define USB_COUNT5_RX_1_NUM_BLOCK_1_1   (0x08000000U)
 
#define USB_COUNT5_RX_1_NUM_BLOCK_1_2   (0x10000000U)
 
#define USB_COUNT5_RX_1_NUM_BLOCK_1_3   (0x20000000U)
 
#define USB_COUNT5_RX_1_NUM_BLOCK_1_4   (0x40000000U)
 
#define USB_COUNT5_RX_1_BLSIZE_1   (0x80000000U)
 
#define USB_COUNT6_RX_0_COUNT6_RX_0   (0x000003FFU)
 
#define USB_COUNT6_RX_0_NUM_BLOCK_0   (0x00007C00U)
 
#define USB_COUNT6_RX_0_NUM_BLOCK_0_0   (0x00000400U)
 
#define USB_COUNT6_RX_0_NUM_BLOCK_0_1   (0x00000800U)
 
#define USB_COUNT6_RX_0_NUM_BLOCK_0_2   (0x00001000U)
 
#define USB_COUNT6_RX_0_NUM_BLOCK_0_3   (0x00002000U)
 
#define USB_COUNT6_RX_0_NUM_BLOCK_0_4   (0x00004000U)
 
#define USB_COUNT6_RX_0_BLSIZE_0   (0x00008000U)
 
#define USB_COUNT6_RX_1_COUNT6_RX_1   (0x03FF0000U)
 
#define USB_COUNT6_RX_1_NUM_BLOCK_1   (0x7C000000U)
 
#define USB_COUNT6_RX_1_NUM_BLOCK_1_0   (0x04000000U)
 
#define USB_COUNT6_RX_1_NUM_BLOCK_1_1   (0x08000000U)
 
#define USB_COUNT6_RX_1_NUM_BLOCK_1_2   (0x10000000U)
 
#define USB_COUNT6_RX_1_NUM_BLOCK_1_3   (0x20000000U)
 
#define USB_COUNT6_RX_1_NUM_BLOCK_1_4   (0x40000000U)
 
#define USB_COUNT6_RX_1_BLSIZE_1   (0x80000000U)
 
#define USB_COUNT7_RX_0_COUNT7_RX_0   (0x000003FFU)
 
#define USB_COUNT7_RX_0_NUM_BLOCK_0   (0x00007C00U)
 
#define USB_COUNT7_RX_0_NUM_BLOCK_0_0   (0x00000400U)
 
#define USB_COUNT7_RX_0_NUM_BLOCK_0_1   (0x00000800U)
 
#define USB_COUNT7_RX_0_NUM_BLOCK_0_2   (0x00001000U)
 
#define USB_COUNT7_RX_0_NUM_BLOCK_0_3   (0x00002000U)
 
#define USB_COUNT7_RX_0_NUM_BLOCK_0_4   (0x00004000U)
 
#define USB_COUNT7_RX_0_BLSIZE_0   (0x00008000U)
 
#define USB_COUNT7_RX_1_COUNT7_RX_1   (0x03FF0000U)
 
#define USB_COUNT7_RX_1_NUM_BLOCK_1   (0x7C000000U)
 
#define USB_COUNT7_RX_1_NUM_BLOCK_1_0   (0x04000000U)
 
#define USB_COUNT7_RX_1_NUM_BLOCK_1_1   (0x08000000U)
 
#define USB_COUNT7_RX_1_NUM_BLOCK_1_2   (0x10000000U)
 
#define USB_COUNT7_RX_1_NUM_BLOCK_1_3   (0x20000000U)
 
#define USB_COUNT7_RX_1_NUM_BLOCK_1_4   (0x40000000U)
 
#define USB_COUNT7_RX_1_BLSIZE_1   (0x80000000U)
 
#define WWDG_CR_T_Pos   (0U)
 
#define WWDG_CR_T_Msk   (0x7FU << WWDG_CR_T_Pos)
 
#define WWDG_CR_T   WWDG_CR_T_Msk
 
#define WWDG_CR_T_0   (0x01U << WWDG_CR_T_Pos)
 
#define WWDG_CR_T_1   (0x02U << WWDG_CR_T_Pos)
 
#define WWDG_CR_T_2   (0x04U << WWDG_CR_T_Pos)
 
#define WWDG_CR_T_3   (0x08U << WWDG_CR_T_Pos)
 
#define WWDG_CR_T_4   (0x10U << WWDG_CR_T_Pos)
 
#define WWDG_CR_T_5   (0x20U << WWDG_CR_T_Pos)
 
#define WWDG_CR_T_6   (0x40U << WWDG_CR_T_Pos)
 
#define WWDG_CR_T0   WWDG_CR_T_0
 
#define WWDG_CR_T1   WWDG_CR_T_1
 
#define WWDG_CR_T2   WWDG_CR_T_2
 
#define WWDG_CR_T3   WWDG_CR_T_3
 
#define WWDG_CR_T4   WWDG_CR_T_4
 
#define WWDG_CR_T5   WWDG_CR_T_5
 
#define WWDG_CR_T6   WWDG_CR_T_6
 
#define WWDG_CR_WDGA_Pos   (7U)
 
#define WWDG_CR_WDGA_Msk   (0x1U << WWDG_CR_WDGA_Pos)
 
#define WWDG_CR_WDGA   WWDG_CR_WDGA_Msk
 
#define WWDG_CFR_W_Pos   (0U)
 
#define WWDG_CFR_W_Msk   (0x7FU << WWDG_CFR_W_Pos)
 
#define WWDG_CFR_W   WWDG_CFR_W_Msk
 
#define WWDG_CFR_W_0   (0x01U << WWDG_CFR_W_Pos)
 
#define WWDG_CFR_W_1   (0x02U << WWDG_CFR_W_Pos)
 
#define WWDG_CFR_W_2   (0x04U << WWDG_CFR_W_Pos)
 
#define WWDG_CFR_W_3   (0x08U << WWDG_CFR_W_Pos)
 
#define WWDG_CFR_W_4   (0x10U << WWDG_CFR_W_Pos)
 
#define WWDG_CFR_W_5   (0x20U << WWDG_CFR_W_Pos)
 
#define WWDG_CFR_W_6   (0x40U << WWDG_CFR_W_Pos)
 
#define WWDG_CFR_W0   WWDG_CFR_W_0
 
#define WWDG_CFR_W1   WWDG_CFR_W_1
 
#define WWDG_CFR_W2   WWDG_CFR_W_2
 
#define WWDG_CFR_W3   WWDG_CFR_W_3
 
#define WWDG_CFR_W4   WWDG_CFR_W_4
 
#define WWDG_CFR_W5   WWDG_CFR_W_5
 
#define WWDG_CFR_W6   WWDG_CFR_W_6
 
#define WWDG_CFR_WDGTB_Pos   (7U)
 
#define WWDG_CFR_WDGTB_Msk   (0x3U << WWDG_CFR_WDGTB_Pos)
 
#define WWDG_CFR_WDGTB   WWDG_CFR_WDGTB_Msk
 
#define WWDG_CFR_WDGTB_0   (0x1U << WWDG_CFR_WDGTB_Pos)
 
#define WWDG_CFR_WDGTB_1   (0x2U << WWDG_CFR_WDGTB_Pos)
 
#define WWDG_CFR_WDGTB0   WWDG_CFR_WDGTB_0
 
#define WWDG_CFR_WDGTB1   WWDG_CFR_WDGTB_1
 
#define WWDG_CFR_EWI_Pos   (9U)
 
#define WWDG_CFR_EWI_Msk   (0x1U << WWDG_CFR_EWI_Pos)
 
#define WWDG_CFR_EWI   WWDG_CFR_EWI_Msk
 
#define WWDG_SR_EWIF_Pos   (0U)
 
#define WWDG_SR_EWIF_Msk   (0x1U << WWDG_SR_EWIF_Pos)
 
#define WWDG_SR_EWIF   WWDG_SR_EWIF_Msk
 
#define SysTick_CTRL_ENABLE   (0x00000001U)
 
#define SysTick_CTRL_TICKINT   (0x00000002U)
 
#define SysTick_CTRL_CLKSOURCE   (0x00000004U)
 
#define SysTick_CTRL_COUNTFLAG   (0x00010000U)
 
#define SysTick_LOAD_RELOAD   (0x00FFFFFFU)
 
#define SysTick_VAL_CURRENT   (0x00FFFFFFU)
 
#define SysTick_CALIB_TENMS   (0x00FFFFFFU)
 
#define SysTick_CALIB_SKEW   (0x40000000U)
 
#define SysTick_CALIB_NOREF   (0x80000000U)
 
#define NVIC_ISER_SETENA_Pos   (0U)
 
#define NVIC_ISER_SETENA_Msk   (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA   NVIC_ISER_SETENA_Msk
 
#define NVIC_ISER_SETENA_0   (0x00000001U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_1   (0x00000002U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_2   (0x00000004U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_3   (0x00000008U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_4   (0x00000010U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_5   (0x00000020U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_6   (0x00000040U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_7   (0x00000080U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_8   (0x00000100U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_9   (0x00000200U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_10   (0x00000400U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_11   (0x00000800U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_12   (0x00001000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_13   (0x00002000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_14   (0x00004000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_15   (0x00008000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_16   (0x00010000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_17   (0x00020000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_18   (0x00040000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_19   (0x00080000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_20   (0x00100000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_21   (0x00200000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_22   (0x00400000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_23   (0x00800000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_24   (0x01000000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_25   (0x02000000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_26   (0x04000000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_27   (0x08000000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_28   (0x10000000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_29   (0x20000000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_30   (0x40000000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ISER_SETENA_31   (0x80000000U << NVIC_ISER_SETENA_Pos)
 
#define NVIC_ICER_CLRENA_Pos   (0U)
 
#define NVIC_ICER_CLRENA_Msk   (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA   NVIC_ICER_CLRENA_Msk
 
#define NVIC_ICER_CLRENA_0   (0x00000001U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_1   (0x00000002U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_2   (0x00000004U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_3   (0x00000008U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_4   (0x00000010U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_5   (0x00000020U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_6   (0x00000040U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_7   (0x00000080U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_8   (0x00000100U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_9   (0x00000200U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_10   (0x00000400U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_11   (0x00000800U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_12   (0x00001000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_13   (0x00002000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_14   (0x00004000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_15   (0x00008000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_16   (0x00010000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_17   (0x00020000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_18   (0x00040000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_19   (0x00080000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_20   (0x00100000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_21   (0x00200000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_22   (0x00400000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_23   (0x00800000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_24   (0x01000000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_25   (0x02000000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_26   (0x04000000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_27   (0x08000000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_28   (0x10000000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_29   (0x20000000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_30   (0x40000000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ICER_CLRENA_31   (0x80000000U << NVIC_ICER_CLRENA_Pos)
 
#define NVIC_ISPR_SETPEND_Pos   (0U)
 
#define NVIC_ISPR_SETPEND_Msk   (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND   NVIC_ISPR_SETPEND_Msk
 
#define NVIC_ISPR_SETPEND_0   (0x00000001U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_1   (0x00000002U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_2   (0x00000004U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_3   (0x00000008U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_4   (0x00000010U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_5   (0x00000020U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_6   (0x00000040U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_7   (0x00000080U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_8   (0x00000100U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_9   (0x00000200U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_10   (0x00000400U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_11   (0x00000800U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_12   (0x00001000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_13   (0x00002000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_14   (0x00004000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_15   (0x00008000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_16   (0x00010000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_17   (0x00020000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_18   (0x00040000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_19   (0x00080000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_20   (0x00100000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_21   (0x00200000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_22   (0x00400000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_23   (0x00800000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_24   (0x01000000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_25   (0x02000000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_26   (0x04000000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_27   (0x08000000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_28   (0x10000000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_29   (0x20000000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_30   (0x40000000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ISPR_SETPEND_31   (0x80000000U << NVIC_ISPR_SETPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_Pos   (0U)
 
#define NVIC_ICPR_CLRPEND_Msk   (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND   NVIC_ICPR_CLRPEND_Msk
 
#define NVIC_ICPR_CLRPEND_0   (0x00000001U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_1   (0x00000002U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_2   (0x00000004U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_3   (0x00000008U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_4   (0x00000010U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_5   (0x00000020U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_6   (0x00000040U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_7   (0x00000080U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_8   (0x00000100U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_9   (0x00000200U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_10   (0x00000400U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_11   (0x00000800U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_12   (0x00001000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_13   (0x00002000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_14   (0x00004000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_15   (0x00008000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_16   (0x00010000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_17   (0x00020000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_18   (0x00040000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_19   (0x00080000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_20   (0x00100000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_21   (0x00200000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_22   (0x00400000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_23   (0x00800000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_24   (0x01000000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_25   (0x02000000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_26   (0x04000000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_27   (0x08000000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_28   (0x10000000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_29   (0x20000000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_30   (0x40000000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_ICPR_CLRPEND_31   (0x80000000U << NVIC_ICPR_CLRPEND_Pos)
 
#define NVIC_IABR_ACTIVE_Pos   (0U)
 
#define NVIC_IABR_ACTIVE_Msk   (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE   NVIC_IABR_ACTIVE_Msk
 
#define NVIC_IABR_ACTIVE_0   (0x00000001U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_1   (0x00000002U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_2   (0x00000004U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_3   (0x00000008U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_4   (0x00000010U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_5   (0x00000020U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_6   (0x00000040U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_7   (0x00000080U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_8   (0x00000100U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_9   (0x00000200U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_10   (0x00000400U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_11   (0x00000800U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_12   (0x00001000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_13   (0x00002000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_14   (0x00004000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_15   (0x00008000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_16   (0x00010000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_17   (0x00020000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_18   (0x00040000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_19   (0x00080000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_20   (0x00100000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_21   (0x00200000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_22   (0x00400000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_23   (0x00800000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_24   (0x01000000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_25   (0x02000000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_26   (0x04000000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_27   (0x08000000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_28   (0x10000000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_29   (0x20000000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_30   (0x40000000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IABR_ACTIVE_31   (0x80000000U << NVIC_IABR_ACTIVE_Pos)
 
#define NVIC_IPR0_PRI_0   (0x000000FFU)
 
#define NVIC_IPR0_PRI_1   (0x0000FF00U)
 
#define NVIC_IPR0_PRI_2   (0x00FF0000U)
 
#define NVIC_IPR0_PRI_3   (0xFF000000U)
 
#define NVIC_IPR1_PRI_4   (0x000000FFU)
 
#define NVIC_IPR1_PRI_5   (0x0000FF00U)
 
#define NVIC_IPR1_PRI_6   (0x00FF0000U)
 
#define NVIC_IPR1_PRI_7   (0xFF000000U)
 
#define NVIC_IPR2_PRI_8   (0x000000FFU)
 
#define NVIC_IPR2_PRI_9   (0x0000FF00U)
 
#define NVIC_IPR2_PRI_10   (0x00FF0000U)
 
#define NVIC_IPR2_PRI_11   (0xFF000000U)
 
#define NVIC_IPR3_PRI_12   (0x000000FFU)
 
#define NVIC_IPR3_PRI_13   (0x0000FF00U)
 
#define NVIC_IPR3_PRI_14   (0x00FF0000U)
 
#define NVIC_IPR3_PRI_15   (0xFF000000U)
 
#define NVIC_IPR4_PRI_16   (0x000000FFU)
 
#define NVIC_IPR4_PRI_17   (0x0000FF00U)
 
#define NVIC_IPR4_PRI_18   (0x00FF0000U)
 
#define NVIC_IPR4_PRI_19   (0xFF000000U)
 
#define NVIC_IPR5_PRI_20   (0x000000FFU)
 
#define NVIC_IPR5_PRI_21   (0x0000FF00U)
 
#define NVIC_IPR5_PRI_22   (0x00FF0000U)
 
#define NVIC_IPR5_PRI_23   (0xFF000000U)
 
#define NVIC_IPR6_PRI_24   (0x000000FFU)
 
#define NVIC_IPR6_PRI_25   (0x0000FF00U)
 
#define NVIC_IPR6_PRI_26   (0x00FF0000U)
 
#define NVIC_IPR6_PRI_27   (0xFF000000U)
 
#define NVIC_IPR7_PRI_28   (0x000000FFU)
 
#define NVIC_IPR7_PRI_29   (0x0000FF00U)
 
#define NVIC_IPR7_PRI_30   (0x00FF0000U)
 
#define NVIC_IPR7_PRI_31   (0xFF000000U)
 
#define SCB_CPUID_REVISION   (0x0000000FU)
 
#define SCB_CPUID_PARTNO   (0x0000FFF0U)
 
#define SCB_CPUID_Constant   (0x000F0000U)
 
#define SCB_CPUID_VARIANT   (0x00F00000U)
 
#define SCB_CPUID_IMPLEMENTER   (0xFF000000U)
 
#define SCB_ICSR_VECTACTIVE   (0x000001FFU)
 
#define SCB_ICSR_RETTOBASE   (0x00000800U)
 
#define SCB_ICSR_VECTPENDING   (0x003FF000U)
 
#define SCB_ICSR_ISRPENDING   (0x00400000U)
 
#define SCB_ICSR_ISRPREEMPT   (0x00800000U)
 
#define SCB_ICSR_PENDSTCLR   (0x02000000U)
 
#define SCB_ICSR_PENDSTSET   (0x04000000U)
 
#define SCB_ICSR_PENDSVCLR   (0x08000000U)
 
#define SCB_ICSR_PENDSVSET   (0x10000000U)
 
#define SCB_ICSR_NMIPENDSET   (0x80000000U)
 
#define SCB_VTOR_TBLOFF   (0x1FFFFF80U)
 
#define SCB_VTOR_TBLBASE   (0x20000000U)
 
#define SCB_AIRCR_VECTRESET   (0x00000001U)
 
#define SCB_AIRCR_VECTCLRACTIVE   (0x00000002U)
 
#define SCB_AIRCR_SYSRESETREQ   (0x00000004U)
 
#define SCB_AIRCR_PRIGROUP   (0x00000700U)
 
#define SCB_AIRCR_PRIGROUP_0   (0x00000100U)
 
#define SCB_AIRCR_PRIGROUP_1   (0x00000200U)
 
#define SCB_AIRCR_PRIGROUP_2   (0x00000400U)
 
#define SCB_AIRCR_PRIGROUP0   (0x00000000U)
 
#define SCB_AIRCR_PRIGROUP1   (0x00000100U)
 
#define SCB_AIRCR_PRIGROUP2   (0x00000200U)
 
#define SCB_AIRCR_PRIGROUP3   (0x00000300U)
 
#define SCB_AIRCR_PRIGROUP4   (0x00000400U)
 
#define SCB_AIRCR_PRIGROUP5   (0x00000500U)
 
#define SCB_AIRCR_PRIGROUP6   (0x00000600U)
 
#define SCB_AIRCR_PRIGROUP7   (0x00000700U)
 
#define SCB_AIRCR_ENDIANESS   (0x00008000U)
 
#define SCB_AIRCR_VECTKEY   (0xFFFF0000U)
 
#define SCB_SCR_SLEEPONEXIT   (0x00000002U)
 
#define SCB_SCR_SLEEPDEEP   (0x00000004U)
 
#define SCB_SCR_SEVONPEND   (0x00000010U)
 
#define SCB_CCR_NONBASETHRDENA   (0x00000001U)
 
#define SCB_CCR_USERSETMPEND   (0x00000002U)
 
#define SCB_CCR_UNALIGN_TRP   (0x00000008U)
 
#define SCB_CCR_DIV_0_TRP   (0x00000010U)
 
#define SCB_CCR_BFHFNMIGN   (0x00000100U)
 
#define SCB_CCR_STKALIGN   (0x00000200U)
 
#define SCB_SHPR_PRI_N_Pos   (0U)
 
#define SCB_SHPR_PRI_N_Msk   (0xFFU << SCB_SHPR_PRI_N_Pos)
 
#define SCB_SHPR_PRI_N   SCB_SHPR_PRI_N_Msk
 
#define SCB_SHPR_PRI_N1_Pos   (8U)
 
#define SCB_SHPR_PRI_N1_Msk   (0xFFU << SCB_SHPR_PRI_N1_Pos)
 
#define SCB_SHPR_PRI_N1   SCB_SHPR_PRI_N1_Msk
 
#define SCB_SHPR_PRI_N2_Pos   (16U)
 
#define SCB_SHPR_PRI_N2_Msk   (0xFFU << SCB_SHPR_PRI_N2_Pos)
 
#define SCB_SHPR_PRI_N2   SCB_SHPR_PRI_N2_Msk
 
#define SCB_SHPR_PRI_N3_Pos   (24U)
 
#define SCB_SHPR_PRI_N3_Msk   (0xFFU << SCB_SHPR_PRI_N3_Pos)
 
#define SCB_SHPR_PRI_N3   SCB_SHPR_PRI_N3_Msk
 
#define SCB_SHCSR_MEMFAULTACT   (0x00000001U)
 
#define SCB_SHCSR_BUSFAULTACT   (0x00000002U)
 
#define SCB_SHCSR_USGFAULTACT   (0x00000008U)
 
#define SCB_SHCSR_SVCALLACT   (0x00000080U)
 
#define SCB_SHCSR_MONITORACT   (0x00000100U)
 
#define SCB_SHCSR_PENDSVACT   (0x00000400U)
 
#define SCB_SHCSR_SYSTICKACT   (0x00000800U)
 
#define SCB_SHCSR_USGFAULTPENDED   (0x00001000U)
 
#define SCB_SHCSR_MEMFAULTPENDED   (0x00002000U)
 
#define SCB_SHCSR_BUSFAULTPENDED   (0x00004000U)
 
#define SCB_SHCSR_SVCALLPENDED   (0x00008000U)
 
#define SCB_SHCSR_MEMFAULTENA   (0x00010000U)
 
#define SCB_SHCSR_BUSFAULTENA   (0x00020000U)
 
#define SCB_SHCSR_USGFAULTENA   (0x00040000U)
 
#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)
 
#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)
 
#define SCB_CFSR_IACCVIOL   SCB_CFSR_IACCVIOL_Msk
 
#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)
 
#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)
 
#define SCB_CFSR_DACCVIOL   SCB_CFSR_DACCVIOL_Msk
 
#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)
 
#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)
 
#define SCB_CFSR_MUNSTKERR   SCB_CFSR_MUNSTKERR_Msk
 
#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)
 
#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)
 
#define SCB_CFSR_MSTKERR   SCB_CFSR_MSTKERR_Msk
 
#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)
 
#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)
 
#define SCB_CFSR_MMARVALID   SCB_CFSR_MMARVALID_Msk
 
#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)
 
#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)
 
#define SCB_CFSR_IBUSERR   SCB_CFSR_IBUSERR_Msk
 
#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)
 
#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)
 
#define SCB_CFSR_PRECISERR   SCB_CFSR_PRECISERR_Msk
 
#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)
 
#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)
 
#define SCB_CFSR_IMPRECISERR   SCB_CFSR_IMPRECISERR_Msk
 
#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)
 
#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)
 
#define SCB_CFSR_UNSTKERR   SCB_CFSR_UNSTKERR_Msk
 
#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)
 
#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)
 
#define SCB_CFSR_STKERR   SCB_CFSR_STKERR_Msk
 
#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)
 
#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)
 
#define SCB_CFSR_BFARVALID   SCB_CFSR_BFARVALID_Msk
 
#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)
 
#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)
 
#define SCB_CFSR_UNDEFINSTR   SCB_CFSR_UNDEFINSTR_Msk
 
#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)
 
#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)
 
#define SCB_CFSR_INVSTATE   SCB_CFSR_INVSTATE_Msk
 
#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)
 
#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)
 
#define SCB_CFSR_INVPC   SCB_CFSR_INVPC_Msk
 
#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)
 
#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)
 
#define SCB_CFSR_NOCP   SCB_CFSR_NOCP_Msk
 
#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)
 
#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)
 
#define SCB_CFSR_UNALIGNED   SCB_CFSR_UNALIGNED_Msk
 
#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)
 
#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)
 
#define SCB_CFSR_DIVBYZERO   SCB_CFSR_DIVBYZERO_Msk
 
#define SCB_HFSR_VECTTBL   (0x00000002U)
 
#define SCB_HFSR_FORCED   (0x40000000U)
 
#define SCB_HFSR_DEBUGEVT   (0x80000000U)
 
#define SCB_DFSR_HALTED   (0x00000001U)
 
#define SCB_DFSR_BKPT   (0x00000002U)
 
#define SCB_DFSR_DWTTRAP   (0x00000004U)
 
#define SCB_DFSR_VCATCH   (0x00000008U)
 
#define SCB_DFSR_EXTERNAL   (0x00000010U)
 
#define SCB_MMFAR_ADDRESS_Pos   (0U)
 
#define SCB_MMFAR_ADDRESS_Msk   (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos)
 
#define SCB_MMFAR_ADDRESS   SCB_MMFAR_ADDRESS_Msk
 
#define SCB_BFAR_ADDRESS_Pos   (0U)
 
#define SCB_BFAR_ADDRESS_Msk   (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos)
 
#define SCB_BFAR_ADDRESS   SCB_BFAR_ADDRESS_Msk
 
#define SCB_AFSR_IMPDEF_Pos   (0U)
 
#define SCB_AFSR_IMPDEF_Msk   (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos)
 
#define SCB_AFSR_IMPDEF   SCB_AFSR_IMPDEF_Msk
 

Detailed Description

Macro Definition Documentation

◆ ADC_CCR_ADCPRE

#define ADC_CCR_ADCPRE   ADC_CCR_ADCPRE_Msk

ADC clock source asynchronous prescaler

◆ ADC_CCR_ADCPRE_0

#define ADC_CCR_ADCPRE_0   (0x1U << ADC_CCR_ADCPRE_Pos)

0x00010000

◆ ADC_CCR_ADCPRE_1

#define ADC_CCR_ADCPRE_1   (0x2U << ADC_CCR_ADCPRE_Pos)

0x00020000

◆ ADC_CCR_ADCPRE_Msk

#define ADC_CCR_ADCPRE_Msk   (0x3U << ADC_CCR_ADCPRE_Pos)

0x00030000

◆ ADC_CCR_ADCPRE_Pos

#define ADC_CCR_ADCPRE_Pos   (16U)

◆ ADC_CCR_TSVREFE

#define ADC_CCR_TSVREFE   ADC_CCR_TSVREFE_Msk

ADC internal path to VrefInt and temperature sensor enable

◆ ADC_CCR_TSVREFE_Msk

#define ADC_CCR_TSVREFE_Msk   (0x1U << ADC_CCR_TSVREFE_Pos)

0x00800000

◆ ADC_CCR_TSVREFE_Pos

#define ADC_CCR_TSVREFE_Pos   (23U)

◆ ADC_CR1_AWDCH

#define ADC_CR1_AWDCH   ADC_CR1_AWDCH_Msk

ADC analog watchdog 1 monitored channel selection

◆ ADC_CR1_AWDCH_0

#define ADC_CR1_AWDCH_0   (0x01U << ADC_CR1_AWDCH_Pos)

0x00000001

◆ ADC_CR1_AWDCH_1

#define ADC_CR1_AWDCH_1   (0x02U << ADC_CR1_AWDCH_Pos)

0x00000002

◆ ADC_CR1_AWDCH_2

#define ADC_CR1_AWDCH_2   (0x04U << ADC_CR1_AWDCH_Pos)

0x00000004

◆ ADC_CR1_AWDCH_3

#define ADC_CR1_AWDCH_3   (0x08U << ADC_CR1_AWDCH_Pos)

0x00000008

◆ ADC_CR1_AWDCH_4

#define ADC_CR1_AWDCH_4   (0x10U << ADC_CR1_AWDCH_Pos)

0x00000010

◆ ADC_CR1_AWDCH_Msk

#define ADC_CR1_AWDCH_Msk   (0x1FU << ADC_CR1_AWDCH_Pos)

0x0000001F

◆ ADC_CR1_AWDCH_Pos

#define ADC_CR1_AWDCH_Pos   (0U)

◆ ADC_CR1_AWDEN

#define ADC_CR1_AWDEN   ADC_CR1_AWDEN_Msk

ADC analog watchdog 1 enable on scope ADC group regular

◆ ADC_CR1_AWDEN_Msk

#define ADC_CR1_AWDEN_Msk   (0x1U << ADC_CR1_AWDEN_Pos)

0x00800000

◆ ADC_CR1_AWDEN_Pos

#define ADC_CR1_AWDEN_Pos   (23U)

◆ ADC_CR1_AWDIE

#define ADC_CR1_AWDIE   ADC_CR1_AWDIE_Msk

ADC analog watchdog 1 interrupt

◆ ADC_CR1_AWDIE_Msk

#define ADC_CR1_AWDIE_Msk   (0x1U << ADC_CR1_AWDIE_Pos)

0x00000040

◆ ADC_CR1_AWDIE_Pos

#define ADC_CR1_AWDIE_Pos   (6U)

◆ ADC_CR1_AWDSGL

#define ADC_CR1_AWDSGL   ADC_CR1_AWDSGL_Msk

ADC analog watchdog 1 monitoring a single channel or all channels

◆ ADC_CR1_AWDSGL_Msk

#define ADC_CR1_AWDSGL_Msk   (0x1U << ADC_CR1_AWDSGL_Pos)

0x00000200

◆ ADC_CR1_AWDSGL_Pos

#define ADC_CR1_AWDSGL_Pos   (9U)

◆ ADC_CR1_DISCEN

#define ADC_CR1_DISCEN   ADC_CR1_DISCEN_Msk

ADC group regular sequencer discontinuous mode

◆ ADC_CR1_DISCEN_Msk

#define ADC_CR1_DISCEN_Msk   (0x1U << ADC_CR1_DISCEN_Pos)

0x00000800

◆ ADC_CR1_DISCEN_Pos

#define ADC_CR1_DISCEN_Pos   (11U)

◆ ADC_CR1_DISCNUM

#define ADC_CR1_DISCNUM   ADC_CR1_DISCNUM_Msk

ADC group regular sequencer discontinuous number of ranks

◆ ADC_CR1_DISCNUM_0

#define ADC_CR1_DISCNUM_0   (0x1U << ADC_CR1_DISCNUM_Pos)

0x00002000

◆ ADC_CR1_DISCNUM_1

#define ADC_CR1_DISCNUM_1   (0x2U << ADC_CR1_DISCNUM_Pos)

0x00004000

◆ ADC_CR1_DISCNUM_2

#define ADC_CR1_DISCNUM_2   (0x4U << ADC_CR1_DISCNUM_Pos)

0x00008000

◆ ADC_CR1_DISCNUM_Msk

#define ADC_CR1_DISCNUM_Msk   (0x7U << ADC_CR1_DISCNUM_Pos)

0x0000E000

◆ ADC_CR1_DISCNUM_Pos

#define ADC_CR1_DISCNUM_Pos   (13U)

◆ ADC_CR1_EOCIE

#define ADC_CR1_EOCIE   (ADC_CR1_EOCSIE)

◆ ADC_CR1_EOCSIE

#define ADC_CR1_EOCSIE   ADC_CR1_EOCSIE_Msk

ADC group regular end of unitary conversion or end of sequence conversions interrupt

◆ ADC_CR1_EOCSIE_Msk

#define ADC_CR1_EOCSIE_Msk   (0x1U << ADC_CR1_EOCSIE_Pos)

0x00000020

◆ ADC_CR1_EOCSIE_Pos

#define ADC_CR1_EOCSIE_Pos   (5U)

◆ ADC_CR1_JAUTO

#define ADC_CR1_JAUTO   ADC_CR1_JAUTO_Msk

ADC group injected automatic trigger mode

◆ ADC_CR1_JAUTO_Msk

#define ADC_CR1_JAUTO_Msk   (0x1U << ADC_CR1_JAUTO_Pos)

0x00000400

◆ ADC_CR1_JAUTO_Pos

#define ADC_CR1_JAUTO_Pos   (10U)

◆ ADC_CR1_JAWDEN

#define ADC_CR1_JAWDEN   ADC_CR1_JAWDEN_Msk

ADC analog watchdog 1 enable on scope ADC group injected

◆ ADC_CR1_JAWDEN_Msk

#define ADC_CR1_JAWDEN_Msk   (0x1U << ADC_CR1_JAWDEN_Pos)

0x00400000

◆ ADC_CR1_JAWDEN_Pos

#define ADC_CR1_JAWDEN_Pos   (22U)

◆ ADC_CR1_JDISCEN

#define ADC_CR1_JDISCEN   ADC_CR1_JDISCEN_Msk

ADC group injected sequencer discontinuous mode

◆ ADC_CR1_JDISCEN_Msk

#define ADC_CR1_JDISCEN_Msk   (0x1U << ADC_CR1_JDISCEN_Pos)

0x00001000

◆ ADC_CR1_JDISCEN_Pos

#define ADC_CR1_JDISCEN_Pos   (12U)

◆ ADC_CR1_JEOCIE

#define ADC_CR1_JEOCIE   (ADC_CR1_JEOSIE)

◆ ADC_CR1_JEOSIE

#define ADC_CR1_JEOSIE   ADC_CR1_JEOSIE_Msk

ADC group injected end of sequence conversions interrupt

◆ ADC_CR1_JEOSIE_Msk

#define ADC_CR1_JEOSIE_Msk   (0x1U << ADC_CR1_JEOSIE_Pos)

0x00000080

◆ ADC_CR1_JEOSIE_Pos

#define ADC_CR1_JEOSIE_Pos   (7U)

◆ ADC_CR1_OVRIE

#define ADC_CR1_OVRIE   ADC_CR1_OVRIE_Msk

ADC group regular overrun interrupt

◆ ADC_CR1_OVRIE_Msk

#define ADC_CR1_OVRIE_Msk   (0x1U << ADC_CR1_OVRIE_Pos)

0x04000000

◆ ADC_CR1_OVRIE_Pos

#define ADC_CR1_OVRIE_Pos   (26U)

◆ ADC_CR1_PDD

#define ADC_CR1_PDD   ADC_CR1_PDD_Msk

ADC power down during auto delay phase

◆ ADC_CR1_PDD_Msk

#define ADC_CR1_PDD_Msk   (0x1U << ADC_CR1_PDD_Pos)

0x00010000

◆ ADC_CR1_PDD_Pos

#define ADC_CR1_PDD_Pos   (16U)

◆ ADC_CR1_PDI

#define ADC_CR1_PDI   ADC_CR1_PDI_Msk

ADC power down during idle phase

◆ ADC_CR1_PDI_Msk

#define ADC_CR1_PDI_Msk   (0x1U << ADC_CR1_PDI_Pos)

0x00020000

◆ ADC_CR1_PDI_Pos

#define ADC_CR1_PDI_Pos   (17U)

◆ ADC_CR1_RES

#define ADC_CR1_RES   ADC_CR1_RES_Msk

ADC resolution

◆ ADC_CR1_RES_0

#define ADC_CR1_RES_0   (0x1U << ADC_CR1_RES_Pos)

0x01000000

◆ ADC_CR1_RES_1

#define ADC_CR1_RES_1   (0x2U << ADC_CR1_RES_Pos)

0x02000000

◆ ADC_CR1_RES_Msk

#define ADC_CR1_RES_Msk   (0x3U << ADC_CR1_RES_Pos)

0x03000000

◆ ADC_CR1_RES_Pos

#define ADC_CR1_RES_Pos   (24U)

◆ ADC_CR1_SCAN

#define ADC_CR1_SCAN   ADC_CR1_SCAN_Msk

ADC scan mode

◆ ADC_CR1_SCAN_Msk

#define ADC_CR1_SCAN_Msk   (0x1U << ADC_CR1_SCAN_Pos)

0x00000100

◆ ADC_CR1_SCAN_Pos

#define ADC_CR1_SCAN_Pos   (8U)

◆ ADC_CR2_ADON

#define ADC_CR2_ADON   ADC_CR2_ADON_Msk

ADC enable

◆ ADC_CR2_ADON_Msk

#define ADC_CR2_ADON_Msk   (0x1U << ADC_CR2_ADON_Pos)

0x00000001

◆ ADC_CR2_ADON_Pos

#define ADC_CR2_ADON_Pos   (0U)

◆ ADC_CR2_ALIGN

#define ADC_CR2_ALIGN   ADC_CR2_ALIGN_Msk

ADC data alignement

◆ ADC_CR2_ALIGN_Msk

#define ADC_CR2_ALIGN_Msk   (0x1U << ADC_CR2_ALIGN_Pos)

0x00000800

◆ ADC_CR2_ALIGN_Pos

#define ADC_CR2_ALIGN_Pos   (11U)

◆ ADC_CR2_CFG

#define ADC_CR2_CFG   ADC_CR2_CFG_Msk

ADC channels bank selection

◆ ADC_CR2_CFG_Msk

#define ADC_CR2_CFG_Msk   (0x1U << ADC_CR2_CFG_Pos)

0x00000004

◆ ADC_CR2_CFG_Pos

#define ADC_CR2_CFG_Pos   (2U)

◆ ADC_CR2_CONT

#define ADC_CR2_CONT   ADC_CR2_CONT_Msk

ADC group regular continuous conversion mode

◆ ADC_CR2_CONT_Msk

#define ADC_CR2_CONT_Msk   (0x1U << ADC_CR2_CONT_Pos)

0x00000002

◆ ADC_CR2_CONT_Pos

#define ADC_CR2_CONT_Pos   (1U)

◆ ADC_CR2_DDS

#define ADC_CR2_DDS   ADC_CR2_DDS_Msk

ADC DMA transfer configuration

◆ ADC_CR2_DDS_Msk

#define ADC_CR2_DDS_Msk   (0x1U << ADC_CR2_DDS_Pos)

0x00000200

◆ ADC_CR2_DDS_Pos

#define ADC_CR2_DDS_Pos   (9U)

◆ ADC_CR2_DELS

#define ADC_CR2_DELS   ADC_CR2_DELS_Msk

ADC auto delay selection

◆ ADC_CR2_DELS_0

#define ADC_CR2_DELS_0   (0x1U << ADC_CR2_DELS_Pos)

0x00000010

◆ ADC_CR2_DELS_1

#define ADC_CR2_DELS_1   (0x2U << ADC_CR2_DELS_Pos)

0x00000020

◆ ADC_CR2_DELS_2

#define ADC_CR2_DELS_2   (0x4U << ADC_CR2_DELS_Pos)

0x00000040

◆ ADC_CR2_DELS_Msk

#define ADC_CR2_DELS_Msk   (0x7U << ADC_CR2_DELS_Pos)

0x00000070

◆ ADC_CR2_DELS_Pos

#define ADC_CR2_DELS_Pos   (4U)

◆ ADC_CR2_DMA

#define ADC_CR2_DMA   ADC_CR2_DMA_Msk

ADC DMA transfer enable

◆ ADC_CR2_DMA_Msk

#define ADC_CR2_DMA_Msk   (0x1U << ADC_CR2_DMA_Pos)

0x00000100

◆ ADC_CR2_DMA_Pos

#define ADC_CR2_DMA_Pos   (8U)

◆ ADC_CR2_EOCS

#define ADC_CR2_EOCS   ADC_CR2_EOCS_Msk

ADC end of unitary or end of sequence conversions selection

◆ ADC_CR2_EOCS_Msk

#define ADC_CR2_EOCS_Msk   (0x1U << ADC_CR2_EOCS_Pos)

0x00000400

◆ ADC_CR2_EOCS_Pos

#define ADC_CR2_EOCS_Pos   (10U)

◆ ADC_CR2_EXTEN

#define ADC_CR2_EXTEN   ADC_CR2_EXTEN_Msk

ADC group regular external trigger polarity

◆ ADC_CR2_EXTEN_0

#define ADC_CR2_EXTEN_0   (0x1U << ADC_CR2_EXTEN_Pos)

0x10000000

◆ ADC_CR2_EXTEN_1

#define ADC_CR2_EXTEN_1   (0x2U << ADC_CR2_EXTEN_Pos)

0x20000000

◆ ADC_CR2_EXTEN_Msk

#define ADC_CR2_EXTEN_Msk   (0x3U << ADC_CR2_EXTEN_Pos)

0x30000000

◆ ADC_CR2_EXTEN_Pos

#define ADC_CR2_EXTEN_Pos   (28U)

◆ ADC_CR2_EXTSEL

#define ADC_CR2_EXTSEL   ADC_CR2_EXTSEL_Msk

ADC group regular external trigger source

◆ ADC_CR2_EXTSEL_0

#define ADC_CR2_EXTSEL_0   (0x1U << ADC_CR2_EXTSEL_Pos)

0x01000000

◆ ADC_CR2_EXTSEL_1

#define ADC_CR2_EXTSEL_1   (0x2U << ADC_CR2_EXTSEL_Pos)

0x02000000

◆ ADC_CR2_EXTSEL_2

#define ADC_CR2_EXTSEL_2   (0x4U << ADC_CR2_EXTSEL_Pos)

0x04000000

◆ ADC_CR2_EXTSEL_3

#define ADC_CR2_EXTSEL_3   (0x8U << ADC_CR2_EXTSEL_Pos)

0x08000000

◆ ADC_CR2_EXTSEL_Msk

#define ADC_CR2_EXTSEL_Msk   (0xFU << ADC_CR2_EXTSEL_Pos)

0x0F000000

◆ ADC_CR2_EXTSEL_Pos

#define ADC_CR2_EXTSEL_Pos   (24U)

◆ ADC_CR2_JEXTEN

#define ADC_CR2_JEXTEN   ADC_CR2_JEXTEN_Msk

ADC group injected external trigger polarity

◆ ADC_CR2_JEXTEN_0

#define ADC_CR2_JEXTEN_0   (0x1U << ADC_CR2_JEXTEN_Pos)

0x00100000

◆ ADC_CR2_JEXTEN_1

#define ADC_CR2_JEXTEN_1   (0x2U << ADC_CR2_JEXTEN_Pos)

0x00200000

◆ ADC_CR2_JEXTEN_Msk

#define ADC_CR2_JEXTEN_Msk   (0x3U << ADC_CR2_JEXTEN_Pos)

0x00300000

◆ ADC_CR2_JEXTEN_Pos

#define ADC_CR2_JEXTEN_Pos   (20U)

◆ ADC_CR2_JEXTSEL

#define ADC_CR2_JEXTSEL   ADC_CR2_JEXTSEL_Msk

ADC group injected external trigger source

◆ ADC_CR2_JEXTSEL_0

#define ADC_CR2_JEXTSEL_0   (0x1U << ADC_CR2_JEXTSEL_Pos)

0x00010000

◆ ADC_CR2_JEXTSEL_1

#define ADC_CR2_JEXTSEL_1   (0x2U << ADC_CR2_JEXTSEL_Pos)

0x00020000

◆ ADC_CR2_JEXTSEL_2

#define ADC_CR2_JEXTSEL_2   (0x4U << ADC_CR2_JEXTSEL_Pos)

0x00040000

◆ ADC_CR2_JEXTSEL_3

#define ADC_CR2_JEXTSEL_3   (0x8U << ADC_CR2_JEXTSEL_Pos)

0x00080000

◆ ADC_CR2_JEXTSEL_Msk

#define ADC_CR2_JEXTSEL_Msk   (0xFU << ADC_CR2_JEXTSEL_Pos)

0x000F0000

◆ ADC_CR2_JEXTSEL_Pos

#define ADC_CR2_JEXTSEL_Pos   (16U)

◆ ADC_CR2_JSWSTART

#define ADC_CR2_JSWSTART   ADC_CR2_JSWSTART_Msk

ADC group injected conversion start

◆ ADC_CR2_JSWSTART_Msk

#define ADC_CR2_JSWSTART_Msk   (0x1U << ADC_CR2_JSWSTART_Pos)

0x00400000

◆ ADC_CR2_JSWSTART_Pos

#define ADC_CR2_JSWSTART_Pos   (22U)

◆ ADC_CR2_SWSTART

#define ADC_CR2_SWSTART   ADC_CR2_SWSTART_Msk

ADC group regular conversion start

◆ ADC_CR2_SWSTART_Msk

#define ADC_CR2_SWSTART_Msk   (0x1U << ADC_CR2_SWSTART_Pos)

0x40000000

◆ ADC_CR2_SWSTART_Pos

#define ADC_CR2_SWSTART_Pos   (30U)

◆ ADC_CSR_ADONS1

#define ADC_CSR_ADONS1   ADC_CSR_ADONS1_Msk

ADC multimode master ready flag

◆ ADC_CSR_ADONS1_Msk

#define ADC_CSR_ADONS1_Msk   (0x1U << ADC_CSR_ADONS1_Pos)

0x00000040

◆ ADC_CSR_ADONS1_Pos

#define ADC_CSR_ADONS1_Pos   (6U)

◆ ADC_CSR_AWD1

#define ADC_CSR_AWD1   ADC_CSR_AWD1_Msk

ADC multimode master analog watchdog 1 flag

◆ ADC_CSR_AWD1_Msk

#define ADC_CSR_AWD1_Msk   (0x1U << ADC_CSR_AWD1_Pos)

0x00000001

◆ ADC_CSR_AWD1_Pos

#define ADC_CSR_AWD1_Pos   (0U)

◆ ADC_CSR_EOC1

#define ADC_CSR_EOC1   (ADC_CSR_EOCS1)

◆ ADC_CSR_EOCS1

#define ADC_CSR_EOCS1   ADC_CSR_EOCS1_Msk

ADC multimode master group regular end of unitary conversion or end of sequence conversions flag

◆ ADC_CSR_EOCS1_Msk

#define ADC_CSR_EOCS1_Msk   (0x1U << ADC_CSR_EOCS1_Pos)

0x00000002

◆ ADC_CSR_EOCS1_Pos

#define ADC_CSR_EOCS1_Pos   (1U)

◆ ADC_CSR_JEOC1

#define ADC_CSR_JEOC1   (ADC_CSR_JEOS1)

◆ ADC_CSR_JEOS1

#define ADC_CSR_JEOS1   ADC_CSR_JEOS1_Msk

ADC multimode master group injected end of sequence conversions flag

◆ ADC_CSR_JEOS1_Msk

#define ADC_CSR_JEOS1_Msk   (0x1U << ADC_CSR_JEOS1_Pos)

0x00000004

◆ ADC_CSR_JEOS1_Pos

#define ADC_CSR_JEOS1_Pos   (2U)

◆ ADC_CSR_JSTRT1

#define ADC_CSR_JSTRT1   ADC_CSR_JSTRT1_Msk

ADC multimode master group injected conversion start flag

◆ ADC_CSR_JSTRT1_Msk

#define ADC_CSR_JSTRT1_Msk   (0x1U << ADC_CSR_JSTRT1_Pos)

0x00000008

◆ ADC_CSR_JSTRT1_Pos

#define ADC_CSR_JSTRT1_Pos   (3U)

◆ ADC_CSR_OVR1

#define ADC_CSR_OVR1   ADC_CSR_OVR1_Msk

ADC multimode master group regular overrun flag

◆ ADC_CSR_OVR1_Msk

#define ADC_CSR_OVR1_Msk   (0x1U << ADC_CSR_OVR1_Pos)

0x00000020

◆ ADC_CSR_OVR1_Pos

#define ADC_CSR_OVR1_Pos   (5U)

◆ ADC_CSR_STRT1

#define ADC_CSR_STRT1   ADC_CSR_STRT1_Msk

ADC multimode master group regular conversion start flag

◆ ADC_CSR_STRT1_Msk

#define ADC_CSR_STRT1_Msk   (0x1U << ADC_CSR_STRT1_Pos)

0x00000010

◆ ADC_CSR_STRT1_Pos

#define ADC_CSR_STRT1_Pos   (4U)

◆ ADC_DR_DATA

#define ADC_DR_DATA   ADC_DR_DATA_Msk

ADC group regular conversion data

◆ ADC_DR_DATA_Msk

#define ADC_DR_DATA_Msk   (0xFFFFU << ADC_DR_DATA_Pos)

0x0000FFFF

◆ ADC_DR_DATA_Pos

#define ADC_DR_DATA_Pos   (0U)

◆ ADC_HTR_HT

#define ADC_HTR_HT   ADC_HTR_HT_Msk

ADC analog watchdog 1 threshold high

◆ ADC_HTR_HT_Msk

#define ADC_HTR_HT_Msk   (0xFFFU << ADC_HTR_HT_Pos)

0x00000FFF

◆ ADC_HTR_HT_Pos

#define ADC_HTR_HT_Pos   (0U)

◆ ADC_JDR1_JDATA

#define ADC_JDR1_JDATA   ADC_JDR1_JDATA_Msk

ADC group injected sequencer rank 1 conversion data

◆ ADC_JDR1_JDATA_Msk

#define ADC_JDR1_JDATA_Msk   (0xFFFFU << ADC_JDR1_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR1_JDATA_Pos

#define ADC_JDR1_JDATA_Pos   (0U)

◆ ADC_JDR2_JDATA

#define ADC_JDR2_JDATA   ADC_JDR2_JDATA_Msk

ADC group injected sequencer rank 2 conversion data

◆ ADC_JDR2_JDATA_Msk

#define ADC_JDR2_JDATA_Msk   (0xFFFFU << ADC_JDR2_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR2_JDATA_Pos

#define ADC_JDR2_JDATA_Pos   (0U)

◆ ADC_JDR3_JDATA

#define ADC_JDR3_JDATA   ADC_JDR3_JDATA_Msk

ADC group injected sequencer rank 3 conversion data

◆ ADC_JDR3_JDATA_Msk

#define ADC_JDR3_JDATA_Msk   (0xFFFFU << ADC_JDR3_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR3_JDATA_Pos

#define ADC_JDR3_JDATA_Pos   (0U)

◆ ADC_JDR4_JDATA

#define ADC_JDR4_JDATA   ADC_JDR4_JDATA_Msk

ADC group injected sequencer rank 4 conversion data

◆ ADC_JDR4_JDATA_Msk

#define ADC_JDR4_JDATA_Msk   (0xFFFFU << ADC_JDR4_JDATA_Pos)

0x0000FFFF

◆ ADC_JDR4_JDATA_Pos

#define ADC_JDR4_JDATA_Pos   (0U)

◆ ADC_JOFR1_JOFFSET1

#define ADC_JOFR1_JOFFSET1   ADC_JOFR1_JOFFSET1_Msk

ADC group injected sequencer rank 1 offset value

◆ ADC_JOFR1_JOFFSET1_Msk

#define ADC_JOFR1_JOFFSET1_Msk   (0xFFFU << ADC_JOFR1_JOFFSET1_Pos)

0x00000FFF

◆ ADC_JOFR1_JOFFSET1_Pos

#define ADC_JOFR1_JOFFSET1_Pos   (0U)

◆ ADC_JOFR2_JOFFSET2

#define ADC_JOFR2_JOFFSET2   ADC_JOFR2_JOFFSET2_Msk

ADC group injected sequencer rank 2 offset value

◆ ADC_JOFR2_JOFFSET2_Msk

#define ADC_JOFR2_JOFFSET2_Msk   (0xFFFU << ADC_JOFR2_JOFFSET2_Pos)

0x00000FFF

◆ ADC_JOFR2_JOFFSET2_Pos

#define ADC_JOFR2_JOFFSET2_Pos   (0U)

◆ ADC_JOFR3_JOFFSET3

#define ADC_JOFR3_JOFFSET3   ADC_JOFR3_JOFFSET3_Msk

ADC group injected sequencer rank 3 offset value

◆ ADC_JOFR3_JOFFSET3_Msk

#define ADC_JOFR3_JOFFSET3_Msk   (0xFFFU << ADC_JOFR3_JOFFSET3_Pos)

0x00000FFF

◆ ADC_JOFR3_JOFFSET3_Pos

#define ADC_JOFR3_JOFFSET3_Pos   (0U)

◆ ADC_JOFR4_JOFFSET4

#define ADC_JOFR4_JOFFSET4   ADC_JOFR4_JOFFSET4_Msk

ADC group injected sequencer rank 4 offset value

◆ ADC_JOFR4_JOFFSET4_Msk

#define ADC_JOFR4_JOFFSET4_Msk   (0xFFFU << ADC_JOFR4_JOFFSET4_Pos)

0x00000FFF

◆ ADC_JOFR4_JOFFSET4_Pos

#define ADC_JOFR4_JOFFSET4_Pos   (0U)

◆ ADC_JSQR_JL

#define ADC_JSQR_JL   ADC_JSQR_JL_Msk

ADC group injected sequencer scan length

◆ ADC_JSQR_JL_0

#define ADC_JSQR_JL_0   (0x1U << ADC_JSQR_JL_Pos)

0x00100000

◆ ADC_JSQR_JL_1

#define ADC_JSQR_JL_1   (0x2U << ADC_JSQR_JL_Pos)

0x00200000

◆ ADC_JSQR_JL_Msk

#define ADC_JSQR_JL_Msk   (0x3U << ADC_JSQR_JL_Pos)

0x00300000

◆ ADC_JSQR_JL_Pos

#define ADC_JSQR_JL_Pos   (20U)

◆ ADC_JSQR_JSQ1

#define ADC_JSQR_JSQ1   ADC_JSQR_JSQ1_Msk

ADC group injected sequencer rank 1

◆ ADC_JSQR_JSQ1_0

#define ADC_JSQR_JSQ1_0   (0x01U << ADC_JSQR_JSQ1_Pos)

0x00000001

◆ ADC_JSQR_JSQ1_1

#define ADC_JSQR_JSQ1_1   (0x02U << ADC_JSQR_JSQ1_Pos)

0x00000002

◆ ADC_JSQR_JSQ1_2

#define ADC_JSQR_JSQ1_2   (0x04U << ADC_JSQR_JSQ1_Pos)

0x00000004

◆ ADC_JSQR_JSQ1_3

#define ADC_JSQR_JSQ1_3   (0x08U << ADC_JSQR_JSQ1_Pos)

0x00000008

◆ ADC_JSQR_JSQ1_4

#define ADC_JSQR_JSQ1_4   (0x10U << ADC_JSQR_JSQ1_Pos)

0x00000010

◆ ADC_JSQR_JSQ1_Msk

#define ADC_JSQR_JSQ1_Msk   (0x1FU << ADC_JSQR_JSQ1_Pos)

0x0000001F

◆ ADC_JSQR_JSQ1_Pos

#define ADC_JSQR_JSQ1_Pos   (0U)

◆ ADC_JSQR_JSQ2

#define ADC_JSQR_JSQ2   ADC_JSQR_JSQ2_Msk

ADC group injected sequencer rank 2

◆ ADC_JSQR_JSQ2_0

#define ADC_JSQR_JSQ2_0   (0x01U << ADC_JSQR_JSQ2_Pos)

0x00000020

◆ ADC_JSQR_JSQ2_1

#define ADC_JSQR_JSQ2_1   (0x02U << ADC_JSQR_JSQ2_Pos)

0x00000040

◆ ADC_JSQR_JSQ2_2

#define ADC_JSQR_JSQ2_2   (0x04U << ADC_JSQR_JSQ2_Pos)

0x00000080

◆ ADC_JSQR_JSQ2_3

#define ADC_JSQR_JSQ2_3   (0x08U << ADC_JSQR_JSQ2_Pos)

0x00000100

◆ ADC_JSQR_JSQ2_4

#define ADC_JSQR_JSQ2_4   (0x10U << ADC_JSQR_JSQ2_Pos)

0x00000200

◆ ADC_JSQR_JSQ2_Msk

#define ADC_JSQR_JSQ2_Msk   (0x1FU << ADC_JSQR_JSQ2_Pos)

0x000003E0

◆ ADC_JSQR_JSQ2_Pos

#define ADC_JSQR_JSQ2_Pos   (5U)

◆ ADC_JSQR_JSQ3

#define ADC_JSQR_JSQ3   ADC_JSQR_JSQ3_Msk

ADC group injected sequencer rank 3

◆ ADC_JSQR_JSQ3_0

#define ADC_JSQR_JSQ3_0   (0x01U << ADC_JSQR_JSQ3_Pos)

0x00000400

◆ ADC_JSQR_JSQ3_1

#define ADC_JSQR_JSQ3_1   (0x02U << ADC_JSQR_JSQ3_Pos)

0x00000800

◆ ADC_JSQR_JSQ3_2

#define ADC_JSQR_JSQ3_2   (0x04U << ADC_JSQR_JSQ3_Pos)

0x00001000

◆ ADC_JSQR_JSQ3_3

#define ADC_JSQR_JSQ3_3   (0x08U << ADC_JSQR_JSQ3_Pos)

0x00002000

◆ ADC_JSQR_JSQ3_4

#define ADC_JSQR_JSQ3_4   (0x10U << ADC_JSQR_JSQ3_Pos)

0x00004000

◆ ADC_JSQR_JSQ3_Msk

#define ADC_JSQR_JSQ3_Msk   (0x1FU << ADC_JSQR_JSQ3_Pos)

0x00007C00

◆ ADC_JSQR_JSQ3_Pos

#define ADC_JSQR_JSQ3_Pos   (10U)

◆ ADC_JSQR_JSQ4

#define ADC_JSQR_JSQ4   ADC_JSQR_JSQ4_Msk

ADC group injected sequencer rank 4

◆ ADC_JSQR_JSQ4_0

#define ADC_JSQR_JSQ4_0   (0x01U << ADC_JSQR_JSQ4_Pos)

0x00008000

◆ ADC_JSQR_JSQ4_1

#define ADC_JSQR_JSQ4_1   (0x02U << ADC_JSQR_JSQ4_Pos)

0x00010000

◆ ADC_JSQR_JSQ4_2

#define ADC_JSQR_JSQ4_2   (0x04U << ADC_JSQR_JSQ4_Pos)

0x00020000

◆ ADC_JSQR_JSQ4_3

#define ADC_JSQR_JSQ4_3   (0x08U << ADC_JSQR_JSQ4_Pos)

0x00040000

◆ ADC_JSQR_JSQ4_4

#define ADC_JSQR_JSQ4_4   (0x10U << ADC_JSQR_JSQ4_Pos)

0x00080000

◆ ADC_JSQR_JSQ4_Msk

#define ADC_JSQR_JSQ4_Msk   (0x1FU << ADC_JSQR_JSQ4_Pos)

0x000F8000

◆ ADC_JSQR_JSQ4_Pos

#define ADC_JSQR_JSQ4_Pos   (15U)

◆ ADC_LTR_LT

#define ADC_LTR_LT   ADC_LTR_LT_Msk

ADC analog watchdog 1 threshold low

◆ ADC_LTR_LT_Msk

#define ADC_LTR_LT_Msk   (0xFFFU << ADC_LTR_LT_Pos)

0x00000FFF

◆ ADC_LTR_LT_Pos

#define ADC_LTR_LT_Pos   (0U)

◆ ADC_SMPR0_SMP30

#define ADC_SMPR0_SMP30   ADC_SMPR0_SMP30_Msk

ADC channel 30 sampling time selection

◆ ADC_SMPR0_SMP30_0

#define ADC_SMPR0_SMP30_0   (0x1U << ADC_SMPR0_SMP30_Pos)

0x00000001

◆ ADC_SMPR0_SMP30_1

#define ADC_SMPR0_SMP30_1   (0x2U << ADC_SMPR0_SMP30_Pos)

0x00000002

◆ ADC_SMPR0_SMP30_2

#define ADC_SMPR0_SMP30_2   (0x4U << ADC_SMPR0_SMP30_Pos)

0x00000004

◆ ADC_SMPR0_SMP30_Msk

#define ADC_SMPR0_SMP30_Msk   (0x7U << ADC_SMPR0_SMP30_Pos)

0x00000007

◆ ADC_SMPR0_SMP30_Pos

#define ADC_SMPR0_SMP30_Pos   (0U)

◆ ADC_SMPR0_SMP31

#define ADC_SMPR0_SMP31   ADC_SMPR0_SMP31_Msk

ADC channel 31 sampling time selection

◆ ADC_SMPR0_SMP31_0

#define ADC_SMPR0_SMP31_0   (0x1U << ADC_SMPR0_SMP31_Pos)

0x00000008

◆ ADC_SMPR0_SMP31_1

#define ADC_SMPR0_SMP31_1   (0x2U << ADC_SMPR0_SMP31_Pos)

0x00000010

◆ ADC_SMPR0_SMP31_2

#define ADC_SMPR0_SMP31_2   (0x4U << ADC_SMPR0_SMP31_Pos)

0x00000020

◆ ADC_SMPR0_SMP31_Msk

#define ADC_SMPR0_SMP31_Msk   (0x7U << ADC_SMPR0_SMP31_Pos)

0x00000038

◆ ADC_SMPR0_SMP31_Pos

#define ADC_SMPR0_SMP31_Pos   (3U)

◆ ADC_SMPR1_SMP20

#define ADC_SMPR1_SMP20   ADC_SMPR1_SMP20_Msk

ADC channel 20 sampling time selection

◆ ADC_SMPR1_SMP20_0

#define ADC_SMPR1_SMP20_0   (0x1U << ADC_SMPR1_SMP20_Pos)

0x00000001

◆ ADC_SMPR1_SMP20_1

#define ADC_SMPR1_SMP20_1   (0x2U << ADC_SMPR1_SMP20_Pos)

0x00000002

◆ ADC_SMPR1_SMP20_2

#define ADC_SMPR1_SMP20_2   (0x4U << ADC_SMPR1_SMP20_Pos)

0x00000004

◆ ADC_SMPR1_SMP20_Msk

#define ADC_SMPR1_SMP20_Msk   (0x7U << ADC_SMPR1_SMP20_Pos)

0x00000007

◆ ADC_SMPR1_SMP20_Pos

#define ADC_SMPR1_SMP20_Pos   (0U)

◆ ADC_SMPR1_SMP21

#define ADC_SMPR1_SMP21   ADC_SMPR1_SMP21_Msk

ADC channel 21 sampling time selection

◆ ADC_SMPR1_SMP21_0

#define ADC_SMPR1_SMP21_0   (0x1U << ADC_SMPR1_SMP21_Pos)

0x00000008

◆ ADC_SMPR1_SMP21_1

#define ADC_SMPR1_SMP21_1   (0x2U << ADC_SMPR1_SMP21_Pos)

0x00000010

◆ ADC_SMPR1_SMP21_2

#define ADC_SMPR1_SMP21_2   (0x4U << ADC_SMPR1_SMP21_Pos)

0x00000020

◆ ADC_SMPR1_SMP21_Msk

#define ADC_SMPR1_SMP21_Msk   (0x7U << ADC_SMPR1_SMP21_Pos)

0x00000038

◆ ADC_SMPR1_SMP21_Pos

#define ADC_SMPR1_SMP21_Pos   (3U)

◆ ADC_SMPR1_SMP22

#define ADC_SMPR1_SMP22   ADC_SMPR1_SMP22_Msk

ADC channel 22 sampling time selection

◆ ADC_SMPR1_SMP22_0

#define ADC_SMPR1_SMP22_0   (0x1U << ADC_SMPR1_SMP22_Pos)

0x00000040

◆ ADC_SMPR1_SMP22_1

#define ADC_SMPR1_SMP22_1   (0x2U << ADC_SMPR1_SMP22_Pos)

0x00000080

◆ ADC_SMPR1_SMP22_2

#define ADC_SMPR1_SMP22_2   (0x4U << ADC_SMPR1_SMP22_Pos)

0x00000100

◆ ADC_SMPR1_SMP22_Msk

#define ADC_SMPR1_SMP22_Msk   (0x7U << ADC_SMPR1_SMP22_Pos)

0x000001C0

◆ ADC_SMPR1_SMP22_Pos

#define ADC_SMPR1_SMP22_Pos   (6U)

◆ ADC_SMPR1_SMP23

#define ADC_SMPR1_SMP23   ADC_SMPR1_SMP23_Msk

ADC channel 23 sampling time selection

◆ ADC_SMPR1_SMP23_0

#define ADC_SMPR1_SMP23_0   (0x1U << ADC_SMPR1_SMP23_Pos)

0x00000200

◆ ADC_SMPR1_SMP23_1

#define ADC_SMPR1_SMP23_1   (0x2U << ADC_SMPR1_SMP23_Pos)

0x00000400

◆ ADC_SMPR1_SMP23_2

#define ADC_SMPR1_SMP23_2   (0x4U << ADC_SMPR1_SMP23_Pos)

0x00000800

◆ ADC_SMPR1_SMP23_Msk

#define ADC_SMPR1_SMP23_Msk   (0x7U << ADC_SMPR1_SMP23_Pos)

0x00000E00

◆ ADC_SMPR1_SMP23_Pos

#define ADC_SMPR1_SMP23_Pos   (9U)

◆ ADC_SMPR1_SMP24

#define ADC_SMPR1_SMP24   ADC_SMPR1_SMP24_Msk

ADC channel 24 sampling time selection

◆ ADC_SMPR1_SMP24_0

#define ADC_SMPR1_SMP24_0   (0x1U << ADC_SMPR1_SMP24_Pos)

0x00001000

◆ ADC_SMPR1_SMP24_1

#define ADC_SMPR1_SMP24_1   (0x2U << ADC_SMPR1_SMP24_Pos)

0x00002000

◆ ADC_SMPR1_SMP24_2

#define ADC_SMPR1_SMP24_2   (0x4U << ADC_SMPR1_SMP24_Pos)

0x00004000

◆ ADC_SMPR1_SMP24_Msk

#define ADC_SMPR1_SMP24_Msk   (0x7U << ADC_SMPR1_SMP24_Pos)

0x00007000

◆ ADC_SMPR1_SMP24_Pos

#define ADC_SMPR1_SMP24_Pos   (12U)

◆ ADC_SMPR1_SMP25

#define ADC_SMPR1_SMP25   ADC_SMPR1_SMP25_Msk

ADC channel 25 sampling time selection

◆ ADC_SMPR1_SMP25_0

#define ADC_SMPR1_SMP25_0   (0x1U << ADC_SMPR1_SMP25_Pos)

0x00008000

◆ ADC_SMPR1_SMP25_1

#define ADC_SMPR1_SMP25_1   (0x2U << ADC_SMPR1_SMP25_Pos)

0x00010000

◆ ADC_SMPR1_SMP25_2

#define ADC_SMPR1_SMP25_2   (0x4U << ADC_SMPR1_SMP25_Pos)

0x00020000

◆ ADC_SMPR1_SMP25_Msk

#define ADC_SMPR1_SMP25_Msk   (0x7U << ADC_SMPR1_SMP25_Pos)

0x00038000

◆ ADC_SMPR1_SMP25_Pos

#define ADC_SMPR1_SMP25_Pos   (15U)

◆ ADC_SMPR1_SMP26

#define ADC_SMPR1_SMP26   ADC_SMPR1_SMP26_Msk

ADC channel 26 sampling time selection

◆ ADC_SMPR1_SMP26_0

#define ADC_SMPR1_SMP26_0   (0x1U << ADC_SMPR1_SMP26_Pos)

0x00040000

◆ ADC_SMPR1_SMP26_1

#define ADC_SMPR1_SMP26_1   (0x2U << ADC_SMPR1_SMP26_Pos)

0x00080000

◆ ADC_SMPR1_SMP26_2

#define ADC_SMPR1_SMP26_2   (0x4U << ADC_SMPR1_SMP26_Pos)

0x00100000

◆ ADC_SMPR1_SMP26_Msk

#define ADC_SMPR1_SMP26_Msk   (0x7U << ADC_SMPR1_SMP26_Pos)

0x001C0000

◆ ADC_SMPR1_SMP26_Pos

#define ADC_SMPR1_SMP26_Pos   (18U)

◆ ADC_SMPR1_SMP27

#define ADC_SMPR1_SMP27   ADC_SMPR1_SMP27_Msk

ADC channel 27 sampling time selection

◆ ADC_SMPR1_SMP27_0

#define ADC_SMPR1_SMP27_0   (0x1U << ADC_SMPR1_SMP27_Pos)

0x00200000

◆ ADC_SMPR1_SMP27_1

#define ADC_SMPR1_SMP27_1   (0x2U << ADC_SMPR1_SMP27_Pos)

0x00400000

◆ ADC_SMPR1_SMP27_2

#define ADC_SMPR1_SMP27_2   (0x4U << ADC_SMPR1_SMP27_Pos)

0x00800000

◆ ADC_SMPR1_SMP27_Msk

#define ADC_SMPR1_SMP27_Msk   (0x7U << ADC_SMPR1_SMP27_Pos)

0x00E00000

◆ ADC_SMPR1_SMP27_Pos

#define ADC_SMPR1_SMP27_Pos   (21U)

◆ ADC_SMPR1_SMP28

#define ADC_SMPR1_SMP28   ADC_SMPR1_SMP28_Msk

ADC channel 28 sampling time selection

◆ ADC_SMPR1_SMP28_0

#define ADC_SMPR1_SMP28_0   (0x1U << ADC_SMPR1_SMP28_Pos)

0x01000000

◆ ADC_SMPR1_SMP28_1

#define ADC_SMPR1_SMP28_1   (0x2U << ADC_SMPR1_SMP28_Pos)

0x02000000

◆ ADC_SMPR1_SMP28_2

#define ADC_SMPR1_SMP28_2   (0x4U << ADC_SMPR1_SMP28_Pos)

0x04000000

◆ ADC_SMPR1_SMP28_Msk

#define ADC_SMPR1_SMP28_Msk   (0x7U << ADC_SMPR1_SMP28_Pos)

0x07000000

◆ ADC_SMPR1_SMP28_Pos

#define ADC_SMPR1_SMP28_Pos   (24U)

◆ ADC_SMPR1_SMP29

#define ADC_SMPR1_SMP29   ADC_SMPR1_SMP29_Msk

ADC channel 29 sampling time selection

◆ ADC_SMPR1_SMP29_0

#define ADC_SMPR1_SMP29_0   (0x1U << ADC_SMPR1_SMP29_Pos)

0x08000000

◆ ADC_SMPR1_SMP29_1

#define ADC_SMPR1_SMP29_1   (0x2U << ADC_SMPR1_SMP29_Pos)

0x10000000

◆ ADC_SMPR1_SMP29_2

#define ADC_SMPR1_SMP29_2   (0x4U << ADC_SMPR1_SMP29_Pos)

0x20000000

◆ ADC_SMPR1_SMP29_Msk

#define ADC_SMPR1_SMP29_Msk   (0x7U << ADC_SMPR1_SMP29_Pos)

0x38000000

◆ ADC_SMPR1_SMP29_Pos

#define ADC_SMPR1_SMP29_Pos   (27U)

◆ ADC_SMPR2_SMP10

#define ADC_SMPR2_SMP10   ADC_SMPR2_SMP10_Msk

ADC channel 10 sampling time selection

◆ ADC_SMPR2_SMP10_0

#define ADC_SMPR2_SMP10_0   (0x1U << ADC_SMPR2_SMP10_Pos)

0x00000001

◆ ADC_SMPR2_SMP10_1

#define ADC_SMPR2_SMP10_1   (0x2U << ADC_SMPR2_SMP10_Pos)

0x00000002

◆ ADC_SMPR2_SMP10_2

#define ADC_SMPR2_SMP10_2   (0x4U << ADC_SMPR2_SMP10_Pos)

0x00000004

◆ ADC_SMPR2_SMP10_Msk

#define ADC_SMPR2_SMP10_Msk   (0x7U << ADC_SMPR2_SMP10_Pos)

0x00000007

◆ ADC_SMPR2_SMP10_Pos

#define ADC_SMPR2_SMP10_Pos   (0U)

◆ ADC_SMPR2_SMP11

#define ADC_SMPR2_SMP11   ADC_SMPR2_SMP11_Msk

ADC channel 11 sampling time selection

◆ ADC_SMPR2_SMP11_0

#define ADC_SMPR2_SMP11_0   (0x1U << ADC_SMPR2_SMP11_Pos)

0x00000008

◆ ADC_SMPR2_SMP11_1

#define ADC_SMPR2_SMP11_1   (0x2U << ADC_SMPR2_SMP11_Pos)

0x00000010

◆ ADC_SMPR2_SMP11_2

#define ADC_SMPR2_SMP11_2   (0x4U << ADC_SMPR2_SMP11_Pos)

0x00000020

◆ ADC_SMPR2_SMP11_Msk

#define ADC_SMPR2_SMP11_Msk   (0x7U << ADC_SMPR2_SMP11_Pos)

0x00000038

◆ ADC_SMPR2_SMP11_Pos

#define ADC_SMPR2_SMP11_Pos   (3U)

◆ ADC_SMPR2_SMP12

#define ADC_SMPR2_SMP12   ADC_SMPR2_SMP12_Msk

ADC channel 12 sampling time selection

◆ ADC_SMPR2_SMP12_0

#define ADC_SMPR2_SMP12_0   (0x1U << ADC_SMPR2_SMP12_Pos)

0x00000040

◆ ADC_SMPR2_SMP12_1

#define ADC_SMPR2_SMP12_1   (0x2U << ADC_SMPR2_SMP12_Pos)

0x00000080

◆ ADC_SMPR2_SMP12_2

#define ADC_SMPR2_SMP12_2   (0x4U << ADC_SMPR2_SMP12_Pos)

0x00000100

◆ ADC_SMPR2_SMP12_Msk

#define ADC_SMPR2_SMP12_Msk   (0x7U << ADC_SMPR2_SMP12_Pos)

0x000001C0

◆ ADC_SMPR2_SMP12_Pos

#define ADC_SMPR2_SMP12_Pos   (6U)

◆ ADC_SMPR2_SMP13

#define ADC_SMPR2_SMP13   ADC_SMPR2_SMP13_Msk

ADC channel 13 sampling time selection

◆ ADC_SMPR2_SMP13_0

#define ADC_SMPR2_SMP13_0   (0x1U << ADC_SMPR2_SMP13_Pos)

0x00000200

◆ ADC_SMPR2_SMP13_1

#define ADC_SMPR2_SMP13_1   (0x2U << ADC_SMPR2_SMP13_Pos)

0x00000400

◆ ADC_SMPR2_SMP13_2

#define ADC_SMPR2_SMP13_2   (0x4U << ADC_SMPR2_SMP13_Pos)

0x00000800

◆ ADC_SMPR2_SMP13_Msk

#define ADC_SMPR2_SMP13_Msk   (0x7U << ADC_SMPR2_SMP13_Pos)

0x00000E00

◆ ADC_SMPR2_SMP13_Pos

#define ADC_SMPR2_SMP13_Pos   (9U)

◆ ADC_SMPR2_SMP14

#define ADC_SMPR2_SMP14   ADC_SMPR2_SMP14_Msk

ADC channel 14 sampling time selection

◆ ADC_SMPR2_SMP14_0

#define ADC_SMPR2_SMP14_0   (0x1U << ADC_SMPR2_SMP14_Pos)

0x00001000

◆ ADC_SMPR2_SMP14_1

#define ADC_SMPR2_SMP14_1   (0x2U << ADC_SMPR2_SMP14_Pos)

0x00002000

◆ ADC_SMPR2_SMP14_2

#define ADC_SMPR2_SMP14_2   (0x4U << ADC_SMPR2_SMP14_Pos)

0x00004000

◆ ADC_SMPR2_SMP14_Msk

#define ADC_SMPR2_SMP14_Msk   (0x7U << ADC_SMPR2_SMP14_Pos)

0x00007000

◆ ADC_SMPR2_SMP14_Pos

#define ADC_SMPR2_SMP14_Pos   (12U)

◆ ADC_SMPR2_SMP15

#define ADC_SMPR2_SMP15   ADC_SMPR2_SMP15_Msk

ADC channel 5 sampling time selection

◆ ADC_SMPR2_SMP15_0

#define ADC_SMPR2_SMP15_0   (0x1U << ADC_SMPR2_SMP15_Pos)

0x00008000

◆ ADC_SMPR2_SMP15_1

#define ADC_SMPR2_SMP15_1   (0x2U << ADC_SMPR2_SMP15_Pos)

0x00010000

◆ ADC_SMPR2_SMP15_2

#define ADC_SMPR2_SMP15_2   (0x4U << ADC_SMPR2_SMP15_Pos)

0x00020000

◆ ADC_SMPR2_SMP15_Msk

#define ADC_SMPR2_SMP15_Msk   (0x7U << ADC_SMPR2_SMP15_Pos)

0x00038000

◆ ADC_SMPR2_SMP15_Pos

#define ADC_SMPR2_SMP15_Pos   (15U)

◆ ADC_SMPR2_SMP16

#define ADC_SMPR2_SMP16   ADC_SMPR2_SMP16_Msk

ADC channel 16 sampling time selection

◆ ADC_SMPR2_SMP16_0

#define ADC_SMPR2_SMP16_0   (0x1U << ADC_SMPR2_SMP16_Pos)

0x00040000

◆ ADC_SMPR2_SMP16_1

#define ADC_SMPR2_SMP16_1   (0x2U << ADC_SMPR2_SMP16_Pos)

0x00080000

◆ ADC_SMPR2_SMP16_2

#define ADC_SMPR2_SMP16_2   (0x4U << ADC_SMPR2_SMP16_Pos)

0x00100000

◆ ADC_SMPR2_SMP16_Msk

#define ADC_SMPR2_SMP16_Msk   (0x7U << ADC_SMPR2_SMP16_Pos)

0x001C0000

◆ ADC_SMPR2_SMP16_Pos

#define ADC_SMPR2_SMP16_Pos   (18U)

◆ ADC_SMPR2_SMP17

#define ADC_SMPR2_SMP17   ADC_SMPR2_SMP17_Msk

ADC channel 17 sampling time selection

◆ ADC_SMPR2_SMP17_0

#define ADC_SMPR2_SMP17_0   (0x1U << ADC_SMPR2_SMP17_Pos)

0x00200000

◆ ADC_SMPR2_SMP17_1

#define ADC_SMPR2_SMP17_1   (0x2U << ADC_SMPR2_SMP17_Pos)

0x00400000

◆ ADC_SMPR2_SMP17_2

#define ADC_SMPR2_SMP17_2   (0x4U << ADC_SMPR2_SMP17_Pos)

0x00800000

◆ ADC_SMPR2_SMP17_Msk

#define ADC_SMPR2_SMP17_Msk   (0x7U << ADC_SMPR2_SMP17_Pos)

0x00E00000

◆ ADC_SMPR2_SMP17_Pos

#define ADC_SMPR2_SMP17_Pos   (21U)

◆ ADC_SMPR2_SMP18

#define ADC_SMPR2_SMP18   ADC_SMPR2_SMP18_Msk

ADC channel 18 sampling time selection

◆ ADC_SMPR2_SMP18_0

#define ADC_SMPR2_SMP18_0   (0x1U << ADC_SMPR2_SMP18_Pos)

0x01000000

◆ ADC_SMPR2_SMP18_1

#define ADC_SMPR2_SMP18_1   (0x2U << ADC_SMPR2_SMP18_Pos)

0x02000000

◆ ADC_SMPR2_SMP18_2

#define ADC_SMPR2_SMP18_2   (0x4U << ADC_SMPR2_SMP18_Pos)

0x04000000

◆ ADC_SMPR2_SMP18_Msk

#define ADC_SMPR2_SMP18_Msk   (0x7U << ADC_SMPR2_SMP18_Pos)

0x07000000

◆ ADC_SMPR2_SMP18_Pos

#define ADC_SMPR2_SMP18_Pos   (24U)

◆ ADC_SMPR2_SMP19

#define ADC_SMPR2_SMP19   ADC_SMPR2_SMP19_Msk

ADC channel 19 sampling time selection

◆ ADC_SMPR2_SMP19_0

#define ADC_SMPR2_SMP19_0   (0x1U << ADC_SMPR2_SMP19_Pos)

0x08000000

◆ ADC_SMPR2_SMP19_1

#define ADC_SMPR2_SMP19_1   (0x2U << ADC_SMPR2_SMP19_Pos)

0x10000000

◆ ADC_SMPR2_SMP19_2

#define ADC_SMPR2_SMP19_2   (0x4U << ADC_SMPR2_SMP19_Pos)

0x20000000

◆ ADC_SMPR2_SMP19_Msk

#define ADC_SMPR2_SMP19_Msk   (0x7U << ADC_SMPR2_SMP19_Pos)

0x38000000

◆ ADC_SMPR2_SMP19_Pos

#define ADC_SMPR2_SMP19_Pos   (27U)

◆ ADC_SMPR3_SMP0

#define ADC_SMPR3_SMP0   ADC_SMPR3_SMP0_Msk

ADC channel 0 sampling time selection

◆ ADC_SMPR3_SMP0_0

#define ADC_SMPR3_SMP0_0   (0x1U << ADC_SMPR3_SMP0_Pos)

0x00000001

◆ ADC_SMPR3_SMP0_1

#define ADC_SMPR3_SMP0_1   (0x2U << ADC_SMPR3_SMP0_Pos)

0x00000002

◆ ADC_SMPR3_SMP0_2

#define ADC_SMPR3_SMP0_2   (0x4U << ADC_SMPR3_SMP0_Pos)

0x00000004

◆ ADC_SMPR3_SMP0_Msk

#define ADC_SMPR3_SMP0_Msk   (0x7U << ADC_SMPR3_SMP0_Pos)

0x00000007

◆ ADC_SMPR3_SMP0_Pos

#define ADC_SMPR3_SMP0_Pos   (0U)

◆ ADC_SMPR3_SMP1

#define ADC_SMPR3_SMP1   ADC_SMPR3_SMP1_Msk

ADC channel 1 sampling time selection

◆ ADC_SMPR3_SMP1_0

#define ADC_SMPR3_SMP1_0   (0x1U << ADC_SMPR3_SMP1_Pos)

0x00000008

◆ ADC_SMPR3_SMP1_1

#define ADC_SMPR3_SMP1_1   (0x2U << ADC_SMPR3_SMP1_Pos)

0x00000010

◆ ADC_SMPR3_SMP1_2

#define ADC_SMPR3_SMP1_2   (0x4U << ADC_SMPR3_SMP1_Pos)

0x00000020

◆ ADC_SMPR3_SMP1_Msk

#define ADC_SMPR3_SMP1_Msk   (0x7U << ADC_SMPR3_SMP1_Pos)

0x00000038

◆ ADC_SMPR3_SMP1_Pos

#define ADC_SMPR3_SMP1_Pos   (3U)

◆ ADC_SMPR3_SMP2

#define ADC_SMPR3_SMP2   ADC_SMPR3_SMP2_Msk

ADC channel 2 sampling time selection

◆ ADC_SMPR3_SMP2_0

#define ADC_SMPR3_SMP2_0   (0x1U << ADC_SMPR3_SMP2_Pos)

0x00000040

◆ ADC_SMPR3_SMP2_1

#define ADC_SMPR3_SMP2_1   (0x2U << ADC_SMPR3_SMP2_Pos)

0x00000080

◆ ADC_SMPR3_SMP2_2

#define ADC_SMPR3_SMP2_2   (0x4U << ADC_SMPR3_SMP2_Pos)

0x00000100

◆ ADC_SMPR3_SMP2_Msk

#define ADC_SMPR3_SMP2_Msk   (0x7U << ADC_SMPR3_SMP2_Pos)

0x000001C0

◆ ADC_SMPR3_SMP2_Pos

#define ADC_SMPR3_SMP2_Pos   (6U)

◆ ADC_SMPR3_SMP3

#define ADC_SMPR3_SMP3   ADC_SMPR3_SMP3_Msk

ADC channel 3 sampling time selection

◆ ADC_SMPR3_SMP3_0

#define ADC_SMPR3_SMP3_0   (0x1U << ADC_SMPR3_SMP3_Pos)

0x00000200

◆ ADC_SMPR3_SMP3_1

#define ADC_SMPR3_SMP3_1   (0x2U << ADC_SMPR3_SMP3_Pos)

0x00000400

◆ ADC_SMPR3_SMP3_2

#define ADC_SMPR3_SMP3_2   (0x4U << ADC_SMPR3_SMP3_Pos)

0x00000800

◆ ADC_SMPR3_SMP3_Msk

#define ADC_SMPR3_SMP3_Msk   (0x7U << ADC_SMPR3_SMP3_Pos)

0x00000E00

◆ ADC_SMPR3_SMP3_Pos

#define ADC_SMPR3_SMP3_Pos   (9U)

◆ ADC_SMPR3_SMP4

#define ADC_SMPR3_SMP4   ADC_SMPR3_SMP4_Msk

ADC channel 4 sampling time selection

◆ ADC_SMPR3_SMP4_0

#define ADC_SMPR3_SMP4_0   (0x1U << ADC_SMPR3_SMP4_Pos)

0x00001000

◆ ADC_SMPR3_SMP4_1

#define ADC_SMPR3_SMP4_1   (0x2U << ADC_SMPR3_SMP4_Pos)

0x00002000

◆ ADC_SMPR3_SMP4_2

#define ADC_SMPR3_SMP4_2   (0x4U << ADC_SMPR3_SMP4_Pos)

0x00004000

◆ ADC_SMPR3_SMP4_Msk

#define ADC_SMPR3_SMP4_Msk   (0x7U << ADC_SMPR3_SMP4_Pos)

0x00007000

◆ ADC_SMPR3_SMP4_Pos

#define ADC_SMPR3_SMP4_Pos   (12U)

◆ ADC_SMPR3_SMP5

#define ADC_SMPR3_SMP5   ADC_SMPR3_SMP5_Msk

ADC channel 5 sampling time selection

◆ ADC_SMPR3_SMP5_0

#define ADC_SMPR3_SMP5_0   (0x1U << ADC_SMPR3_SMP5_Pos)

0x00008000

◆ ADC_SMPR3_SMP5_1

#define ADC_SMPR3_SMP5_1   (0x2U << ADC_SMPR3_SMP5_Pos)

0x00010000

◆ ADC_SMPR3_SMP5_2

#define ADC_SMPR3_SMP5_2   (0x4U << ADC_SMPR3_SMP5_Pos)

0x00020000

◆ ADC_SMPR3_SMP5_Msk

#define ADC_SMPR3_SMP5_Msk   (0x7U << ADC_SMPR3_SMP5_Pos)

0x00038000

◆ ADC_SMPR3_SMP5_Pos

#define ADC_SMPR3_SMP5_Pos   (15U)

◆ ADC_SMPR3_SMP6

#define ADC_SMPR3_SMP6   ADC_SMPR3_SMP6_Msk

ADC channel 6 sampling time selection

◆ ADC_SMPR3_SMP6_0

#define ADC_SMPR3_SMP6_0   (0x1U << ADC_SMPR3_SMP6_Pos)

0x00040000

◆ ADC_SMPR3_SMP6_1

#define ADC_SMPR3_SMP6_1   (0x2U << ADC_SMPR3_SMP6_Pos)

0x00080000

◆ ADC_SMPR3_SMP6_2

#define ADC_SMPR3_SMP6_2   (0x4U << ADC_SMPR3_SMP6_Pos)

0x00100000

◆ ADC_SMPR3_SMP6_Msk

#define ADC_SMPR3_SMP6_Msk   (0x7U << ADC_SMPR3_SMP6_Pos)

0x001C0000

◆ ADC_SMPR3_SMP6_Pos

#define ADC_SMPR3_SMP6_Pos   (18U)

◆ ADC_SMPR3_SMP7

#define ADC_SMPR3_SMP7   ADC_SMPR3_SMP7_Msk

ADC channel 7 sampling time selection

◆ ADC_SMPR3_SMP7_0

#define ADC_SMPR3_SMP7_0   (0x1U << ADC_SMPR3_SMP7_Pos)

0x00200000

◆ ADC_SMPR3_SMP7_1

#define ADC_SMPR3_SMP7_1   (0x2U << ADC_SMPR3_SMP7_Pos)

0x00400000

◆ ADC_SMPR3_SMP7_2

#define ADC_SMPR3_SMP7_2   (0x4U << ADC_SMPR3_SMP7_Pos)

0x00800000

◆ ADC_SMPR3_SMP7_Msk

#define ADC_SMPR3_SMP7_Msk   (0x7U << ADC_SMPR3_SMP7_Pos)

0x00E00000

◆ ADC_SMPR3_SMP7_Pos

#define ADC_SMPR3_SMP7_Pos   (21U)

◆ ADC_SMPR3_SMP8

#define ADC_SMPR3_SMP8   ADC_SMPR3_SMP8_Msk

ADC channel 8 sampling time selection

◆ ADC_SMPR3_SMP8_0

#define ADC_SMPR3_SMP8_0   (0x1U << ADC_SMPR3_SMP8_Pos)

0x01000000

◆ ADC_SMPR3_SMP8_1

#define ADC_SMPR3_SMP8_1   (0x2U << ADC_SMPR3_SMP8_Pos)

0x02000000

◆ ADC_SMPR3_SMP8_2

#define ADC_SMPR3_SMP8_2   (0x4U << ADC_SMPR3_SMP8_Pos)

0x04000000

◆ ADC_SMPR3_SMP8_Msk

#define ADC_SMPR3_SMP8_Msk   (0x7U << ADC_SMPR3_SMP8_Pos)

0x07000000

◆ ADC_SMPR3_SMP8_Pos

#define ADC_SMPR3_SMP8_Pos   (24U)

◆ ADC_SMPR3_SMP9

#define ADC_SMPR3_SMP9   ADC_SMPR3_SMP9_Msk

ADC channel 9 sampling time selection

◆ ADC_SMPR3_SMP9_0

#define ADC_SMPR3_SMP9_0   (0x1U << ADC_SMPR3_SMP9_Pos)

0x08000000

◆ ADC_SMPR3_SMP9_1

#define ADC_SMPR3_SMP9_1   (0x2U << ADC_SMPR3_SMP9_Pos)

0x10000000

◆ ADC_SMPR3_SMP9_2

#define ADC_SMPR3_SMP9_2   (0x4U << ADC_SMPR3_SMP9_Pos)

0x20000000

◆ ADC_SMPR3_SMP9_Msk

#define ADC_SMPR3_SMP9_Msk   (0x7U << ADC_SMPR3_SMP9_Pos)

0x38000000

◆ ADC_SMPR3_SMP9_Pos

#define ADC_SMPR3_SMP9_Pos   (27U)

◆ ADC_SQR1_L

#define ADC_SQR1_L   ADC_SQR1_L_Msk

ADC group regular sequencer scan length

◆ ADC_SQR1_L_0

#define ADC_SQR1_L_0   (0x01U << ADC_SQR1_L_Pos)

0x00100000

◆ ADC_SQR1_L_1

#define ADC_SQR1_L_1   (0x02U << ADC_SQR1_L_Pos)

0x00200000

◆ ADC_SQR1_L_2

#define ADC_SQR1_L_2   (0x04U << ADC_SQR1_L_Pos)

0x00400000

◆ ADC_SQR1_L_3

#define ADC_SQR1_L_3   (0x08U << ADC_SQR1_L_Pos)

0x00800000

◆ ADC_SQR1_L_4

#define ADC_SQR1_L_4   (0x10U << ADC_SQR1_L_Pos)

0x01000000

◆ ADC_SQR1_L_Msk

#define ADC_SQR1_L_Msk   (0x1FU << ADC_SQR1_L_Pos)

0x01F00000

◆ ADC_SQR1_L_Pos

#define ADC_SQR1_L_Pos   (20U)

◆ ADC_SQR1_SQ25

#define ADC_SQR1_SQ25   ADC_SQR1_SQ25_Msk

ADC group regular sequencer rank 25

◆ ADC_SQR1_SQ25_0

#define ADC_SQR1_SQ25_0   (0x01U << ADC_SQR1_SQ25_Pos)

0x00000001

◆ ADC_SQR1_SQ25_1

#define ADC_SQR1_SQ25_1   (0x02U << ADC_SQR1_SQ25_Pos)

0x00000002

◆ ADC_SQR1_SQ25_2

#define ADC_SQR1_SQ25_2   (0x04U << ADC_SQR1_SQ25_Pos)

0x00000004

◆ ADC_SQR1_SQ25_3

#define ADC_SQR1_SQ25_3   (0x08U << ADC_SQR1_SQ25_Pos)

0x00000008

◆ ADC_SQR1_SQ25_4

#define ADC_SQR1_SQ25_4   (0x10U << ADC_SQR1_SQ25_Pos)

0x00000010

◆ ADC_SQR1_SQ25_Msk

#define ADC_SQR1_SQ25_Msk   (0x1FU << ADC_SQR1_SQ25_Pos)

0x0000001F

◆ ADC_SQR1_SQ25_Pos

#define ADC_SQR1_SQ25_Pos   (0U)

◆ ADC_SQR1_SQ26

#define ADC_SQR1_SQ26   ADC_SQR1_SQ26_Msk

ADC group regular sequencer rank 26

◆ ADC_SQR1_SQ26_0

#define ADC_SQR1_SQ26_0   (0x01U << ADC_SQR1_SQ26_Pos)

0x00000020

◆ ADC_SQR1_SQ26_1

#define ADC_SQR1_SQ26_1   (0x02U << ADC_SQR1_SQ26_Pos)

0x00000040

◆ ADC_SQR1_SQ26_2

#define ADC_SQR1_SQ26_2   (0x04U << ADC_SQR1_SQ26_Pos)

0x00000080

◆ ADC_SQR1_SQ26_3

#define ADC_SQR1_SQ26_3   (0x08U << ADC_SQR1_SQ26_Pos)

0x00000100

◆ ADC_SQR1_SQ26_4

#define ADC_SQR1_SQ26_4   (0x10U << ADC_SQR1_SQ26_Pos)

0x00000200

◆ ADC_SQR1_SQ26_Msk

#define ADC_SQR1_SQ26_Msk   (0x1FU << ADC_SQR1_SQ26_Pos)

0x000003E0

◆ ADC_SQR1_SQ26_Pos

#define ADC_SQR1_SQ26_Pos   (5U)

◆ ADC_SQR1_SQ27

#define ADC_SQR1_SQ27   ADC_SQR1_SQ27_Msk

ADC group regular sequencer rank 27

◆ ADC_SQR1_SQ27_0

#define ADC_SQR1_SQ27_0   (0x01U << ADC_SQR1_SQ27_Pos)

0x00000400

◆ ADC_SQR1_SQ27_1

#define ADC_SQR1_SQ27_1   (0x02U << ADC_SQR1_SQ27_Pos)

0x00000800

◆ ADC_SQR1_SQ27_2

#define ADC_SQR1_SQ27_2   (0x04U << ADC_SQR1_SQ27_Pos)

0x00001000

◆ ADC_SQR1_SQ27_3

#define ADC_SQR1_SQ27_3   (0x08U << ADC_SQR1_SQ27_Pos)

0x00002000

◆ ADC_SQR1_SQ27_4

#define ADC_SQR1_SQ27_4   (0x10U << ADC_SQR1_SQ27_Pos)

0x00004000

◆ ADC_SQR1_SQ27_Msk

#define ADC_SQR1_SQ27_Msk   (0x1FU << ADC_SQR1_SQ27_Pos)

0x00007C00

◆ ADC_SQR1_SQ27_Pos

#define ADC_SQR1_SQ27_Pos   (10U)

◆ ADC_SQR1_SQ28

#define ADC_SQR1_SQ28   ADC_SQR1_SQ28_Msk

ADC group regular sequencer rank 28

◆ ADC_SQR1_SQ28_0

#define ADC_SQR1_SQ28_0   (0x01U << ADC_SQR1_SQ28_Pos)

0x00008000

◆ ADC_SQR1_SQ28_1

#define ADC_SQR1_SQ28_1   (0x02U << ADC_SQR1_SQ28_Pos)

0x00010000

◆ ADC_SQR1_SQ28_2

#define ADC_SQR1_SQ28_2   (0x04U << ADC_SQR1_SQ28_Pos)

0x00020000

◆ ADC_SQR1_SQ28_3

#define ADC_SQR1_SQ28_3   (0x08U << ADC_SQR1_SQ28_Pos)

0x00040000

◆ ADC_SQR1_SQ28_4

#define ADC_SQR1_SQ28_4   (0x10U << ADC_SQR1_SQ28_Pos)

0x00080000

◆ ADC_SQR1_SQ28_Msk

#define ADC_SQR1_SQ28_Msk   (0x1FU << ADC_SQR1_SQ28_Pos)

0x000F8000

◆ ADC_SQR1_SQ28_Pos

#define ADC_SQR1_SQ28_Pos   (15U)

◆ ADC_SQR2_SQ19

#define ADC_SQR2_SQ19   ADC_SQR2_SQ19_Msk

ADC group regular sequencer rank 19

◆ ADC_SQR2_SQ19_0

#define ADC_SQR2_SQ19_0   (0x01U << ADC_SQR2_SQ19_Pos)

0x00000001

◆ ADC_SQR2_SQ19_1

#define ADC_SQR2_SQ19_1   (0x02U << ADC_SQR2_SQ19_Pos)

0x00000002

◆ ADC_SQR2_SQ19_2

#define ADC_SQR2_SQ19_2   (0x04U << ADC_SQR2_SQ19_Pos)

0x00000004

◆ ADC_SQR2_SQ19_3

#define ADC_SQR2_SQ19_3   (0x08U << ADC_SQR2_SQ19_Pos)

0x00000008

◆ ADC_SQR2_SQ19_4

#define ADC_SQR2_SQ19_4   (0x10U << ADC_SQR2_SQ19_Pos)

0x00000010

◆ ADC_SQR2_SQ19_Msk

#define ADC_SQR2_SQ19_Msk   (0x1FU << ADC_SQR2_SQ19_Pos)

0x0000001F

◆ ADC_SQR2_SQ19_Pos

#define ADC_SQR2_SQ19_Pos   (0U)

◆ ADC_SQR2_SQ20

#define ADC_SQR2_SQ20   ADC_SQR2_SQ20_Msk

ADC group regular sequencer rank 20

◆ ADC_SQR2_SQ20_0

#define ADC_SQR2_SQ20_0   (0x01U << ADC_SQR2_SQ20_Pos)

0x00000020

◆ ADC_SQR2_SQ20_1

#define ADC_SQR2_SQ20_1   (0x02U << ADC_SQR2_SQ20_Pos)

0x00000040

◆ ADC_SQR2_SQ20_2

#define ADC_SQR2_SQ20_2   (0x04U << ADC_SQR2_SQ20_Pos)

0x00000080

◆ ADC_SQR2_SQ20_3

#define ADC_SQR2_SQ20_3   (0x08U << ADC_SQR2_SQ20_Pos)

0x00000100

◆ ADC_SQR2_SQ20_4

#define ADC_SQR2_SQ20_4   (0x10U << ADC_SQR2_SQ20_Pos)

0x00000200

◆ ADC_SQR2_SQ20_Msk

#define ADC_SQR2_SQ20_Msk   (0x1FU << ADC_SQR2_SQ20_Pos)

0x000003E0

◆ ADC_SQR2_SQ20_Pos

#define ADC_SQR2_SQ20_Pos   (5U)

◆ ADC_SQR2_SQ21

#define ADC_SQR2_SQ21   ADC_SQR2_SQ21_Msk

ADC group regular sequencer rank 21

◆ ADC_SQR2_SQ21_0

#define ADC_SQR2_SQ21_0   (0x01U << ADC_SQR2_SQ21_Pos)

0x00000400

◆ ADC_SQR2_SQ21_1

#define ADC_SQR2_SQ21_1   (0x02U << ADC_SQR2_SQ21_Pos)

0x00000800

◆ ADC_SQR2_SQ21_2

#define ADC_SQR2_SQ21_2   (0x04U << ADC_SQR2_SQ21_Pos)

0x00001000

◆ ADC_SQR2_SQ21_3

#define ADC_SQR2_SQ21_3   (0x08U << ADC_SQR2_SQ21_Pos)

0x00002000

◆ ADC_SQR2_SQ21_4

#define ADC_SQR2_SQ21_4   (0x10U << ADC_SQR2_SQ21_Pos)

0x00004000

◆ ADC_SQR2_SQ21_Msk

#define ADC_SQR2_SQ21_Msk   (0x1FU << ADC_SQR2_SQ21_Pos)

0x00007C00

◆ ADC_SQR2_SQ21_Pos

#define ADC_SQR2_SQ21_Pos   (10U)

◆ ADC_SQR2_SQ22

#define ADC_SQR2_SQ22   ADC_SQR2_SQ22_Msk

ADC group regular sequencer rank 22

◆ ADC_SQR2_SQ22_0

#define ADC_SQR2_SQ22_0   (0x01U << ADC_SQR2_SQ22_Pos)

0x00008000

◆ ADC_SQR2_SQ22_1

#define ADC_SQR2_SQ22_1   (0x02U << ADC_SQR2_SQ22_Pos)

0x00010000

◆ ADC_SQR2_SQ22_2

#define ADC_SQR2_SQ22_2   (0x04U << ADC_SQR2_SQ22_Pos)

0x00020000

◆ ADC_SQR2_SQ22_3

#define ADC_SQR2_SQ22_3   (0x08U << ADC_SQR2_SQ22_Pos)

0x00040000

◆ ADC_SQR2_SQ22_4

#define ADC_SQR2_SQ22_4   (0x10U << ADC_SQR2_SQ22_Pos)

0x00080000

◆ ADC_SQR2_SQ22_Msk

#define ADC_SQR2_SQ22_Msk   (0x1FU << ADC_SQR2_SQ22_Pos)

0x000F8000

◆ ADC_SQR2_SQ22_Pos

#define ADC_SQR2_SQ22_Pos   (15U)

◆ ADC_SQR2_SQ23

#define ADC_SQR2_SQ23   ADC_SQR2_SQ23_Msk

ADC group regular sequencer rank 23

◆ ADC_SQR2_SQ23_0

#define ADC_SQR2_SQ23_0   (0x01U << ADC_SQR2_SQ23_Pos)

0x00100000

◆ ADC_SQR2_SQ23_1

#define ADC_SQR2_SQ23_1   (0x02U << ADC_SQR2_SQ23_Pos)

0x00200000

◆ ADC_SQR2_SQ23_2

#define ADC_SQR2_SQ23_2   (0x04U << ADC_SQR2_SQ23_Pos)

0x00400000

◆ ADC_SQR2_SQ23_3

#define ADC_SQR2_SQ23_3   (0x08U << ADC_SQR2_SQ23_Pos)

0x00800000

◆ ADC_SQR2_SQ23_4

#define ADC_SQR2_SQ23_4   (0x10U << ADC_SQR2_SQ23_Pos)

0x01000000

◆ ADC_SQR2_SQ23_Msk

#define ADC_SQR2_SQ23_Msk   (0x1FU << ADC_SQR2_SQ23_Pos)

0x01F00000

◆ ADC_SQR2_SQ23_Pos

#define ADC_SQR2_SQ23_Pos   (20U)

◆ ADC_SQR2_SQ24

#define ADC_SQR2_SQ24   ADC_SQR2_SQ24_Msk

ADC group regular sequencer rank 24

◆ ADC_SQR2_SQ24_0

#define ADC_SQR2_SQ24_0   (0x01U << ADC_SQR2_SQ24_Pos)

0x02000000

◆ ADC_SQR2_SQ24_1

#define ADC_SQR2_SQ24_1   (0x02U << ADC_SQR2_SQ24_Pos)

0x04000000

◆ ADC_SQR2_SQ24_2

#define ADC_SQR2_SQ24_2   (0x04U << ADC_SQR2_SQ24_Pos)

0x08000000

◆ ADC_SQR2_SQ24_3

#define ADC_SQR2_SQ24_3   (0x08U << ADC_SQR2_SQ24_Pos)

0x10000000

◆ ADC_SQR2_SQ24_4

#define ADC_SQR2_SQ24_4   (0x10U << ADC_SQR2_SQ24_Pos)

0x20000000

◆ ADC_SQR2_SQ24_Msk

#define ADC_SQR2_SQ24_Msk   (0x1FU << ADC_SQR2_SQ24_Pos)

0x3E000000

◆ ADC_SQR2_SQ24_Pos

#define ADC_SQR2_SQ24_Pos   (25U)

◆ ADC_SQR3_SQ13

#define ADC_SQR3_SQ13   ADC_SQR3_SQ13_Msk

ADC group regular sequencer rank 13

◆ ADC_SQR3_SQ13_0

#define ADC_SQR3_SQ13_0   (0x01U << ADC_SQR3_SQ13_Pos)

0x00000001

◆ ADC_SQR3_SQ13_1

#define ADC_SQR3_SQ13_1   (0x02U << ADC_SQR3_SQ13_Pos)

0x00000002

◆ ADC_SQR3_SQ13_2

#define ADC_SQR3_SQ13_2   (0x04U << ADC_SQR3_SQ13_Pos)

0x00000004

◆ ADC_SQR3_SQ13_3

#define ADC_SQR3_SQ13_3   (0x08U << ADC_SQR3_SQ13_Pos)

0x00000008

◆ ADC_SQR3_SQ13_4

#define ADC_SQR3_SQ13_4   (0x10U << ADC_SQR3_SQ13_Pos)

0x00000010

◆ ADC_SQR3_SQ13_Msk

#define ADC_SQR3_SQ13_Msk   (0x1FU << ADC_SQR3_SQ13_Pos)

0x0000001F

◆ ADC_SQR3_SQ13_Pos

#define ADC_SQR3_SQ13_Pos   (0U)

◆ ADC_SQR3_SQ14

#define ADC_SQR3_SQ14   ADC_SQR3_SQ14_Msk

ADC group regular sequencer rank 14

◆ ADC_SQR3_SQ14_0

#define ADC_SQR3_SQ14_0   (0x01U << ADC_SQR3_SQ14_Pos)

0x00000020

◆ ADC_SQR3_SQ14_1

#define ADC_SQR3_SQ14_1   (0x02U << ADC_SQR3_SQ14_Pos)

0x00000040

◆ ADC_SQR3_SQ14_2

#define ADC_SQR3_SQ14_2   (0x04U << ADC_SQR3_SQ14_Pos)

0x00000080

◆ ADC_SQR3_SQ14_3

#define ADC_SQR3_SQ14_3   (0x08U << ADC_SQR3_SQ14_Pos)

0x00000100

◆ ADC_SQR3_SQ14_4

#define ADC_SQR3_SQ14_4   (0x10U << ADC_SQR3_SQ14_Pos)

0x00000200

◆ ADC_SQR3_SQ14_Msk

#define ADC_SQR3_SQ14_Msk   (0x1FU << ADC_SQR3_SQ14_Pos)

0x000003E0

◆ ADC_SQR3_SQ14_Pos

#define ADC_SQR3_SQ14_Pos   (5U)

◆ ADC_SQR3_SQ15

#define ADC_SQR3_SQ15   ADC_SQR3_SQ15_Msk

ADC group regular sequencer rank 15

◆ ADC_SQR3_SQ15_0

#define ADC_SQR3_SQ15_0   (0x01U << ADC_SQR3_SQ15_Pos)

0x00000400

◆ ADC_SQR3_SQ15_1

#define ADC_SQR3_SQ15_1   (0x02U << ADC_SQR3_SQ15_Pos)

0x00000800

◆ ADC_SQR3_SQ15_2

#define ADC_SQR3_SQ15_2   (0x04U << ADC_SQR3_SQ15_Pos)

0x00001000

◆ ADC_SQR3_SQ15_3

#define ADC_SQR3_SQ15_3   (0x08U << ADC_SQR3_SQ15_Pos)

0x00002000

◆ ADC_SQR3_SQ15_4

#define ADC_SQR3_SQ15_4   (0x10U << ADC_SQR3_SQ15_Pos)

0x00004000

◆ ADC_SQR3_SQ15_Msk

#define ADC_SQR3_SQ15_Msk   (0x1FU << ADC_SQR3_SQ15_Pos)

0x00007C00

◆ ADC_SQR3_SQ15_Pos

#define ADC_SQR3_SQ15_Pos   (10U)

◆ ADC_SQR3_SQ16

#define ADC_SQR3_SQ16   ADC_SQR3_SQ16_Msk

ADC group regular sequencer rank 16

◆ ADC_SQR3_SQ16_0

#define ADC_SQR3_SQ16_0   (0x01U << ADC_SQR3_SQ16_Pos)

0x00008000

◆ ADC_SQR3_SQ16_1

#define ADC_SQR3_SQ16_1   (0x02U << ADC_SQR3_SQ16_Pos)

0x00010000

◆ ADC_SQR3_SQ16_2

#define ADC_SQR3_SQ16_2   (0x04U << ADC_SQR3_SQ16_Pos)

0x00020000

◆ ADC_SQR3_SQ16_3

#define ADC_SQR3_SQ16_3   (0x08U << ADC_SQR3_SQ16_Pos)

0x00040000

◆ ADC_SQR3_SQ16_4

#define ADC_SQR3_SQ16_4   (0x10U << ADC_SQR3_SQ16_Pos)

0x00080000

◆ ADC_SQR3_SQ16_Msk

#define ADC_SQR3_SQ16_Msk   (0x1FU << ADC_SQR3_SQ16_Pos)

0x000F8000

◆ ADC_SQR3_SQ16_Pos

#define ADC_SQR3_SQ16_Pos   (15U)

◆ ADC_SQR3_SQ17

#define ADC_SQR3_SQ17   ADC_SQR3_SQ17_Msk

ADC group regular sequencer rank 17

◆ ADC_SQR3_SQ17_0

#define ADC_SQR3_SQ17_0   (0x01U << ADC_SQR3_SQ17_Pos)

0x00100000

◆ ADC_SQR3_SQ17_1

#define ADC_SQR3_SQ17_1   (0x02U << ADC_SQR3_SQ17_Pos)

0x00200000

◆ ADC_SQR3_SQ17_2

#define ADC_SQR3_SQ17_2   (0x04U << ADC_SQR3_SQ17_Pos)

0x00400000

◆ ADC_SQR3_SQ17_3

#define ADC_SQR3_SQ17_3   (0x08U << ADC_SQR3_SQ17_Pos)

0x00800000

◆ ADC_SQR3_SQ17_4

#define ADC_SQR3_SQ17_4   (0x10U << ADC_SQR3_SQ17_Pos)

0x01000000

◆ ADC_SQR3_SQ17_Msk

#define ADC_SQR3_SQ17_Msk   (0x1FU << ADC_SQR3_SQ17_Pos)

0x01F00000

◆ ADC_SQR3_SQ17_Pos

#define ADC_SQR3_SQ17_Pos   (20U)

◆ ADC_SQR3_SQ18

#define ADC_SQR3_SQ18   ADC_SQR3_SQ18_Msk

ADC group regular sequencer rank 18

◆ ADC_SQR3_SQ18_0

#define ADC_SQR3_SQ18_0   (0x01U << ADC_SQR3_SQ18_Pos)

0x02000000

◆ ADC_SQR3_SQ18_1

#define ADC_SQR3_SQ18_1   (0x02U << ADC_SQR3_SQ18_Pos)

0x04000000

◆ ADC_SQR3_SQ18_2

#define ADC_SQR3_SQ18_2   (0x04U << ADC_SQR3_SQ18_Pos)

0x08000000

◆ ADC_SQR3_SQ18_3

#define ADC_SQR3_SQ18_3   (0x08U << ADC_SQR3_SQ18_Pos)

0x10000000

◆ ADC_SQR3_SQ18_4

#define ADC_SQR3_SQ18_4   (0x10U << ADC_SQR3_SQ18_Pos)

0x20000000

◆ ADC_SQR3_SQ18_Msk

#define ADC_SQR3_SQ18_Msk   (0x1FU << ADC_SQR3_SQ18_Pos)

0x3E000000

◆ ADC_SQR3_SQ18_Pos

#define ADC_SQR3_SQ18_Pos   (25U)

◆ ADC_SQR4_SQ10

#define ADC_SQR4_SQ10   ADC_SQR4_SQ10_Msk

ADC group regular sequencer rank 10

◆ ADC_SQR4_SQ10_0

#define ADC_SQR4_SQ10_0   (0x01U << ADC_SQR4_SQ10_Pos)

0x00008000

◆ ADC_SQR4_SQ10_1

#define ADC_SQR4_SQ10_1   (0x02U << ADC_SQR4_SQ10_Pos)

0x00010000

◆ ADC_SQR4_SQ10_2

#define ADC_SQR4_SQ10_2   (0x04U << ADC_SQR4_SQ10_Pos)

0x00020000

◆ ADC_SQR4_SQ10_3

#define ADC_SQR4_SQ10_3   (0x08U << ADC_SQR4_SQ10_Pos)

0x00040000

◆ ADC_SQR4_SQ10_4

#define ADC_SQR4_SQ10_4   (0x10U << ADC_SQR4_SQ10_Pos)

0x00080000

◆ ADC_SQR4_SQ10_Msk

#define ADC_SQR4_SQ10_Msk   (0x1FU << ADC_SQR4_SQ10_Pos)

0x000F8000

◆ ADC_SQR4_SQ10_Pos

#define ADC_SQR4_SQ10_Pos   (15U)

◆ ADC_SQR4_SQ11

#define ADC_SQR4_SQ11   ADC_SQR4_SQ11_Msk

ADC group regular sequencer rank 11

◆ ADC_SQR4_SQ11_0

#define ADC_SQR4_SQ11_0   (0x01U << ADC_SQR4_SQ11_Pos)

0x00100000

◆ ADC_SQR4_SQ11_1

#define ADC_SQR4_SQ11_1   (0x02U << ADC_SQR4_SQ11_Pos)

0x00200000

◆ ADC_SQR4_SQ11_2

#define ADC_SQR4_SQ11_2   (0x04U << ADC_SQR4_SQ11_Pos)

0x00400000

◆ ADC_SQR4_SQ11_3

#define ADC_SQR4_SQ11_3   (0x08U << ADC_SQR4_SQ11_Pos)

0x00800000

◆ ADC_SQR4_SQ11_4

#define ADC_SQR4_SQ11_4   (0x10U << ADC_SQR4_SQ11_Pos)

0x01000000

◆ ADC_SQR4_SQ11_Msk

#define ADC_SQR4_SQ11_Msk   (0x1FU << ADC_SQR4_SQ11_Pos)

0x01F00000

◆ ADC_SQR4_SQ11_Pos

#define ADC_SQR4_SQ11_Pos   (20U)

◆ ADC_SQR4_SQ12

#define ADC_SQR4_SQ12   ADC_SQR4_SQ12_Msk

ADC group regular sequencer rank 12

◆ ADC_SQR4_SQ12_0

#define ADC_SQR4_SQ12_0   (0x01U << ADC_SQR4_SQ12_Pos)

0x02000000

◆ ADC_SQR4_SQ12_1

#define ADC_SQR4_SQ12_1   (0x02U << ADC_SQR4_SQ12_Pos)

0x04000000

◆ ADC_SQR4_SQ12_2

#define ADC_SQR4_SQ12_2   (0x04U << ADC_SQR4_SQ12_Pos)

0x08000000

◆ ADC_SQR4_SQ12_3

#define ADC_SQR4_SQ12_3   (0x08U << ADC_SQR4_SQ12_Pos)

0x10000000

◆ ADC_SQR4_SQ12_4

#define ADC_SQR4_SQ12_4   (0x10U << ADC_SQR4_SQ12_Pos)

0x20000000

◆ ADC_SQR4_SQ12_Msk

#define ADC_SQR4_SQ12_Msk   (0x1FU << ADC_SQR4_SQ12_Pos)

0x3E000000

◆ ADC_SQR4_SQ12_Pos

#define ADC_SQR4_SQ12_Pos   (25U)

◆ ADC_SQR4_SQ7

#define ADC_SQR4_SQ7   ADC_SQR4_SQ7_Msk

ADC group regular sequencer rank 7

◆ ADC_SQR4_SQ7_0

#define ADC_SQR4_SQ7_0   (0x01U << ADC_SQR4_SQ7_Pos)

0x00000001

◆ ADC_SQR4_SQ7_1

#define ADC_SQR4_SQ7_1   (0x02U << ADC_SQR4_SQ7_Pos)

0x00000002

◆ ADC_SQR4_SQ7_2

#define ADC_SQR4_SQ7_2   (0x04U << ADC_SQR4_SQ7_Pos)

0x00000004

◆ ADC_SQR4_SQ7_3

#define ADC_SQR4_SQ7_3   (0x08U << ADC_SQR4_SQ7_Pos)

0x00000008

◆ ADC_SQR4_SQ7_4

#define ADC_SQR4_SQ7_4   (0x10U << ADC_SQR4_SQ7_Pos)

0x00000010

◆ ADC_SQR4_SQ7_Msk

#define ADC_SQR4_SQ7_Msk   (0x1FU << ADC_SQR4_SQ7_Pos)

0x0000001F

◆ ADC_SQR4_SQ7_Pos

#define ADC_SQR4_SQ7_Pos   (0U)

◆ ADC_SQR4_SQ8

#define ADC_SQR4_SQ8   ADC_SQR4_SQ8_Msk

ADC group regular sequencer rank 8

◆ ADC_SQR4_SQ8_0

#define ADC_SQR4_SQ8_0   (0x01U << ADC_SQR4_SQ8_Pos)

0x00000020

◆ ADC_SQR4_SQ8_1

#define ADC_SQR4_SQ8_1   (0x02U << ADC_SQR4_SQ8_Pos)

0x00000040

◆ ADC_SQR4_SQ8_2

#define ADC_SQR4_SQ8_2   (0x04U << ADC_SQR4_SQ8_Pos)

0x00000080

◆ ADC_SQR4_SQ8_3

#define ADC_SQR4_SQ8_3   (0x08U << ADC_SQR4_SQ8_Pos)

0x00000100

◆ ADC_SQR4_SQ8_4

#define ADC_SQR4_SQ8_4   (0x10U << ADC_SQR4_SQ8_Pos)

0x00000200

◆ ADC_SQR4_SQ8_Msk

#define ADC_SQR4_SQ8_Msk   (0x1FU << ADC_SQR4_SQ8_Pos)

0x000003E0

◆ ADC_SQR4_SQ8_Pos

#define ADC_SQR4_SQ8_Pos   (5U)

◆ ADC_SQR4_SQ9

#define ADC_SQR4_SQ9   ADC_SQR4_SQ9_Msk

ADC group regular sequencer rank 9

◆ ADC_SQR4_SQ9_0

#define ADC_SQR4_SQ9_0   (0x01U << ADC_SQR4_SQ9_Pos)

0x00000400

◆ ADC_SQR4_SQ9_1

#define ADC_SQR4_SQ9_1   (0x02U << ADC_SQR4_SQ9_Pos)

0x00000800

◆ ADC_SQR4_SQ9_2

#define ADC_SQR4_SQ9_2   (0x04U << ADC_SQR4_SQ9_Pos)

0x00001000

◆ ADC_SQR4_SQ9_3

#define ADC_SQR4_SQ9_3   (0x08U << ADC_SQR4_SQ9_Pos)

0x00002000

◆ ADC_SQR4_SQ9_4

#define ADC_SQR4_SQ9_4   (0x10U << ADC_SQR4_SQ9_Pos)

0x00004000

◆ ADC_SQR4_SQ9_Msk

#define ADC_SQR4_SQ9_Msk   (0x1FU << ADC_SQR4_SQ9_Pos)

0x00007C00

◆ ADC_SQR4_SQ9_Pos

#define ADC_SQR4_SQ9_Pos   (10U)

◆ ADC_SQR5_SQ1

#define ADC_SQR5_SQ1   ADC_SQR5_SQ1_Msk

ADC group regular sequencer rank 1

◆ ADC_SQR5_SQ1_0

#define ADC_SQR5_SQ1_0   (0x01U << ADC_SQR5_SQ1_Pos)

0x00000001

◆ ADC_SQR5_SQ1_1

#define ADC_SQR5_SQ1_1   (0x02U << ADC_SQR5_SQ1_Pos)

0x00000002

◆ ADC_SQR5_SQ1_2

#define ADC_SQR5_SQ1_2   (0x04U << ADC_SQR5_SQ1_Pos)

0x00000004

◆ ADC_SQR5_SQ1_3

#define ADC_SQR5_SQ1_3   (0x08U << ADC_SQR5_SQ1_Pos)

0x00000008

◆ ADC_SQR5_SQ1_4

#define ADC_SQR5_SQ1_4   (0x10U << ADC_SQR5_SQ1_Pos)

0x00000010

◆ ADC_SQR5_SQ1_Msk

#define ADC_SQR5_SQ1_Msk   (0x1FU << ADC_SQR5_SQ1_Pos)

0x0000001F

◆ ADC_SQR5_SQ1_Pos

#define ADC_SQR5_SQ1_Pos   (0U)

◆ ADC_SQR5_SQ2

#define ADC_SQR5_SQ2   ADC_SQR5_SQ2_Msk

ADC group regular sequencer rank 2

◆ ADC_SQR5_SQ2_0

#define ADC_SQR5_SQ2_0   (0x01U << ADC_SQR5_SQ2_Pos)

0x00000020

◆ ADC_SQR5_SQ2_1

#define ADC_SQR5_SQ2_1   (0x02U << ADC_SQR5_SQ2_Pos)

0x00000040

◆ ADC_SQR5_SQ2_2

#define ADC_SQR5_SQ2_2   (0x04U << ADC_SQR5_SQ2_Pos)

0x00000080

◆ ADC_SQR5_SQ2_3

#define ADC_SQR5_SQ2_3   (0x08U << ADC_SQR5_SQ2_Pos)

0x00000100

◆ ADC_SQR5_SQ2_4

#define ADC_SQR5_SQ2_4   (0x10U << ADC_SQR5_SQ2_Pos)

0x00000200

◆ ADC_SQR5_SQ2_Msk

#define ADC_SQR5_SQ2_Msk   (0x1FU << ADC_SQR5_SQ2_Pos)

0x000003E0

◆ ADC_SQR5_SQ2_Pos

#define ADC_SQR5_SQ2_Pos   (5U)

◆ ADC_SQR5_SQ3

#define ADC_SQR5_SQ3   ADC_SQR5_SQ3_Msk

ADC group regular sequencer rank 3

◆ ADC_SQR5_SQ3_0

#define ADC_SQR5_SQ3_0   (0x01U << ADC_SQR5_SQ3_Pos)

0x00000400

◆ ADC_SQR5_SQ3_1

#define ADC_SQR5_SQ3_1   (0x02U << ADC_SQR5_SQ3_Pos)

0x00000800

◆ ADC_SQR5_SQ3_2

#define ADC_SQR5_SQ3_2   (0x04U << ADC_SQR5_SQ3_Pos)

0x00001000

◆ ADC_SQR5_SQ3_3

#define ADC_SQR5_SQ3_3   (0x08U << ADC_SQR5_SQ3_Pos)

0x00002000

◆ ADC_SQR5_SQ3_4

#define ADC_SQR5_SQ3_4   (0x10U << ADC_SQR5_SQ3_Pos)

0x00004000

◆ ADC_SQR5_SQ3_Msk

#define ADC_SQR5_SQ3_Msk   (0x1FU << ADC_SQR5_SQ3_Pos)

0x00007C00

◆ ADC_SQR5_SQ3_Pos

#define ADC_SQR5_SQ3_Pos   (10U)

◆ ADC_SQR5_SQ4

#define ADC_SQR5_SQ4   ADC_SQR5_SQ4_Msk

ADC group regular sequencer rank 4

◆ ADC_SQR5_SQ4_0

#define ADC_SQR5_SQ4_0   (0x01U << ADC_SQR5_SQ4_Pos)

0x00008000

◆ ADC_SQR5_SQ4_1

#define ADC_SQR5_SQ4_1   (0x02U << ADC_SQR5_SQ4_Pos)

0x00010000

◆ ADC_SQR5_SQ4_2

#define ADC_SQR5_SQ4_2   (0x04U << ADC_SQR5_SQ4_Pos)

0x00020000

◆ ADC_SQR5_SQ4_3

#define ADC_SQR5_SQ4_3   (0x08U << ADC_SQR5_SQ4_Pos)

0x00040000

◆ ADC_SQR5_SQ4_4

#define ADC_SQR5_SQ4_4   (0x10U << ADC_SQR5_SQ4_Pos)

0x00080000

◆ ADC_SQR5_SQ4_Msk

#define ADC_SQR5_SQ4_Msk   (0x1FU << ADC_SQR5_SQ4_Pos)

0x000F8000

◆ ADC_SQR5_SQ4_Pos

#define ADC_SQR5_SQ4_Pos   (15U)

◆ ADC_SQR5_SQ5

#define ADC_SQR5_SQ5   ADC_SQR5_SQ5_Msk

ADC group regular sequencer rank 5

◆ ADC_SQR5_SQ5_0

#define ADC_SQR5_SQ5_0   (0x01U << ADC_SQR5_SQ5_Pos)

0x00100000

◆ ADC_SQR5_SQ5_1

#define ADC_SQR5_SQ5_1   (0x02U << ADC_SQR5_SQ5_Pos)

0x00200000

◆ ADC_SQR5_SQ5_2

#define ADC_SQR5_SQ5_2   (0x04U << ADC_SQR5_SQ5_Pos)

0x00400000

◆ ADC_SQR5_SQ5_3

#define ADC_SQR5_SQ5_3   (0x08U << ADC_SQR5_SQ5_Pos)

0x00800000

◆ ADC_SQR5_SQ5_4

#define ADC_SQR5_SQ5_4   (0x10U << ADC_SQR5_SQ5_Pos)

0x01000000

◆ ADC_SQR5_SQ5_Msk

#define ADC_SQR5_SQ5_Msk   (0x1FU << ADC_SQR5_SQ5_Pos)

0x01F00000

◆ ADC_SQR5_SQ5_Pos

#define ADC_SQR5_SQ5_Pos   (20U)

◆ ADC_SQR5_SQ6

#define ADC_SQR5_SQ6   ADC_SQR5_SQ6_Msk

ADC group regular sequencer rank 6

◆ ADC_SQR5_SQ6_0

#define ADC_SQR5_SQ6_0   (0x01U << ADC_SQR5_SQ6_Pos)

0x02000000

◆ ADC_SQR5_SQ6_1

#define ADC_SQR5_SQ6_1   (0x02U << ADC_SQR5_SQ6_Pos)

0x04000000

◆ ADC_SQR5_SQ6_2

#define ADC_SQR5_SQ6_2   (0x04U << ADC_SQR5_SQ6_Pos)

0x08000000

◆ ADC_SQR5_SQ6_3

#define ADC_SQR5_SQ6_3   (0x08U << ADC_SQR5_SQ6_Pos)

0x10000000

◆ ADC_SQR5_SQ6_4

#define ADC_SQR5_SQ6_4   (0x10U << ADC_SQR5_SQ6_Pos)

0x20000000

◆ ADC_SQR5_SQ6_Msk

#define ADC_SQR5_SQ6_Msk   (0x1FU << ADC_SQR5_SQ6_Pos)

0x3E000000

◆ ADC_SQR5_SQ6_Pos

#define ADC_SQR5_SQ6_Pos   (25U)

◆ ADC_SR_ADONS

#define ADC_SR_ADONS   ADC_SR_ADONS_Msk

ADC ready flag

◆ ADC_SR_ADONS_Msk

#define ADC_SR_ADONS_Msk   (0x1U << ADC_SR_ADONS_Pos)

0x00000040

◆ ADC_SR_ADONS_Pos

#define ADC_SR_ADONS_Pos   (6U)

◆ ADC_SR_AWD

#define ADC_SR_AWD   ADC_SR_AWD_Msk

ADC analog watchdog 1 flag

◆ ADC_SR_AWD_Msk

#define ADC_SR_AWD_Msk   (0x1U << ADC_SR_AWD_Pos)

0x00000001

◆ ADC_SR_AWD_Pos

#define ADC_SR_AWD_Pos   (0U)

◆ ADC_SR_EOC

#define ADC_SR_EOC   (ADC_SR_EOCS)

◆ ADC_SR_EOCS

#define ADC_SR_EOCS   ADC_SR_EOCS_Msk

ADC group regular end of unitary conversion or end of sequence conversions flag

◆ ADC_SR_EOCS_Msk

#define ADC_SR_EOCS_Msk   (0x1U << ADC_SR_EOCS_Pos)

0x00000002

◆ ADC_SR_EOCS_Pos

#define ADC_SR_EOCS_Pos   (1U)

◆ ADC_SR_JCNR

#define ADC_SR_JCNR   ADC_SR_JCNR_Msk

ADC group injected not ready flag

◆ ADC_SR_JCNR_Msk

#define ADC_SR_JCNR_Msk   (0x1U << ADC_SR_JCNR_Pos)

0x00000200

◆ ADC_SR_JCNR_Pos

#define ADC_SR_JCNR_Pos   (9U)

◆ ADC_SR_JEOC

#define ADC_SR_JEOC   (ADC_SR_JEOS)

◆ ADC_SR_JEOS

#define ADC_SR_JEOS   ADC_SR_JEOS_Msk

ADC group injected end of sequence conversions flag

◆ ADC_SR_JEOS_Msk

#define ADC_SR_JEOS_Msk   (0x1U << ADC_SR_JEOS_Pos)

0x00000004

◆ ADC_SR_JEOS_Pos

#define ADC_SR_JEOS_Pos   (2U)

◆ ADC_SR_JSTRT

#define ADC_SR_JSTRT   ADC_SR_JSTRT_Msk

ADC group injected conversion start flag

◆ ADC_SR_JSTRT_Msk

#define ADC_SR_JSTRT_Msk   (0x1U << ADC_SR_JSTRT_Pos)

0x00000008

◆ ADC_SR_JSTRT_Pos

#define ADC_SR_JSTRT_Pos   (3U)

◆ ADC_SR_OVR

#define ADC_SR_OVR   ADC_SR_OVR_Msk

ADC group regular overrun flag

◆ ADC_SR_OVR_Msk

#define ADC_SR_OVR_Msk   (0x1U << ADC_SR_OVR_Pos)

0x00000020

◆ ADC_SR_OVR_Pos

#define ADC_SR_OVR_Pos   (5U)

◆ ADC_SR_RCNR

#define ADC_SR_RCNR   ADC_SR_RCNR_Msk

ADC group regular not ready flag

◆ ADC_SR_RCNR_Msk

#define ADC_SR_RCNR_Msk   (0x1U << ADC_SR_RCNR_Pos)

0x00000100

◆ ADC_SR_RCNR_Pos

#define ADC_SR_RCNR_Pos   (8U)

◆ ADC_SR_STRT

#define ADC_SR_STRT   ADC_SR_STRT_Msk

ADC group regular conversion start flag

◆ ADC_SR_STRT_Msk

#define ADC_SR_STRT_Msk   (0x1U << ADC_SR_STRT_Pos)

0x00000010

◆ ADC_SR_STRT_Pos

#define ADC_SR_STRT_Pos   (4U)

◆ COMP_CSR_10KPD

#define COMP_CSR_10KPD   (0x00000004U)

Comparator 1 input plus 10K pull-down resistor

◆ COMP_CSR_10KPU

#define COMP_CSR_10KPU   (0x00000001U)

Comparator 1 input plus 10K pull-up resistor

◆ COMP_CSR_400KPD

#define COMP_CSR_400KPD   (0x00000008U)

Comparator 1 input plus 400K pull-down resistor

◆ COMP_CSR_400KPU

#define COMP_CSR_400KPU   (0x00000002U)

Comparator 1 input plus 400K pull-up resistor

◆ COMP_CSR_CAIE

#define COMP_CSR_CAIE   COMP_CSR_CAIE_Msk

Bit 29

◆ COMP_CSR_CAIE_Msk

#define COMP_CSR_CAIE_Msk   (0x1U << COMP_CSR_CAIE_Pos)

0x20000000

◆ COMP_CSR_CAIE_Pos

#define COMP_CSR_CAIE_Pos   (29U)

◆ COMP_CSR_CAIF

#define COMP_CSR_CAIF   COMP_CSR_CAIF_Msk

Bit 30

◆ COMP_CSR_CAIF_Msk

#define COMP_CSR_CAIF_Msk   (0x1U << COMP_CSR_CAIF_Pos)

0x40000000

◆ COMP_CSR_CAIF_Pos

#define COMP_CSR_CAIF_Pos   (30U)

◆ COMP_CSR_CMP1EN

#define COMP_CSR_CMP1EN   COMP_CSR_CMP1EN_Msk

Comparator 1 enable

◆ COMP_CSR_CMP1EN_Msk

#define COMP_CSR_CMP1EN_Msk   (0x1U << COMP_CSR_CMP1EN_Pos)

0x00000010

◆ COMP_CSR_CMP1EN_Pos

#define COMP_CSR_CMP1EN_Pos   (4U)

◆ COMP_CSR_CMP1OUT

#define COMP_CSR_CMP1OUT   COMP_CSR_CMP1OUT_Msk

Comparator 1 output level

◆ COMP_CSR_CMP1OUT_Msk

#define COMP_CSR_CMP1OUT_Msk   (0x1U << COMP_CSR_CMP1OUT_Pos)

0x00000080

◆ COMP_CSR_CMP1OUT_Pos

#define COMP_CSR_CMP1OUT_Pos   (7U)

◆ COMP_CSR_CMP2OUT

#define COMP_CSR_CMP2OUT   COMP_CSR_CMP2OUT_Msk

Comparator 2 output level

◆ COMP_CSR_CMP2OUT_Msk

#define COMP_CSR_CMP2OUT_Msk   (0x1U << COMP_CSR_CMP2OUT_Pos)

0x00002000

◆ COMP_CSR_CMP2OUT_Pos

#define COMP_CSR_CMP2OUT_Pos   (13U)

◆ COMP_CSR_FCH3

#define COMP_CSR_FCH3   COMP_CSR_FCH3_Msk

Bit 26

◆ COMP_CSR_FCH3_Msk

#define COMP_CSR_FCH3_Msk   (0x1U << COMP_CSR_FCH3_Pos)

0x04000000

◆ COMP_CSR_FCH3_Pos

#define COMP_CSR_FCH3_Pos   (26U)

◆ COMP_CSR_FCH8

#define COMP_CSR_FCH8   COMP_CSR_FCH8_Msk

Bit 27

◆ COMP_CSR_FCH8_Msk

#define COMP_CSR_FCH8_Msk   (0x1U << COMP_CSR_FCH8_Pos)

0x08000000

◆ COMP_CSR_FCH8_Pos

#define COMP_CSR_FCH8_Pos   (27U)

◆ COMP_CSR_INSEL

#define COMP_CSR_INSEL   COMP_CSR_INSEL_Msk

Comparator 2 input minus selection

◆ COMP_CSR_INSEL_0

#define COMP_CSR_INSEL_0   (0x1U << COMP_CSR_INSEL_Pos)

0x00040000

◆ COMP_CSR_INSEL_1

#define COMP_CSR_INSEL_1   (0x2U << COMP_CSR_INSEL_Pos)

0x00080000

◆ COMP_CSR_INSEL_2

#define COMP_CSR_INSEL_2   (0x4U << COMP_CSR_INSEL_Pos)

0x00100000

◆ COMP_CSR_INSEL_Msk

#define COMP_CSR_INSEL_Msk   (0x7U << COMP_CSR_INSEL_Pos)

0x001C0000

◆ COMP_CSR_INSEL_Pos

#define COMP_CSR_INSEL_Pos   (18U)

◆ COMP_CSR_OUTSEL

#define COMP_CSR_OUTSEL   COMP_CSR_OUTSEL_Msk

Comparator 2 output redirection

◆ COMP_CSR_OUTSEL_0

#define COMP_CSR_OUTSEL_0   (0x1U << COMP_CSR_OUTSEL_Pos)

0x00200000

◆ COMP_CSR_OUTSEL_1

#define COMP_CSR_OUTSEL_1   (0x2U << COMP_CSR_OUTSEL_Pos)

0x00400000

◆ COMP_CSR_OUTSEL_2

#define COMP_CSR_OUTSEL_2   (0x4U << COMP_CSR_OUTSEL_Pos)

0x00800000

◆ COMP_CSR_OUTSEL_Msk

#define COMP_CSR_OUTSEL_Msk   (0x7U << COMP_CSR_OUTSEL_Pos)

0x00E00000

◆ COMP_CSR_OUTSEL_Pos

#define COMP_CSR_OUTSEL_Pos   (21U)

◆ COMP_CSR_RCH13

#define COMP_CSR_RCH13   COMP_CSR_RCH13_Msk

Bit 28

◆ COMP_CSR_RCH13_Msk

#define COMP_CSR_RCH13_Msk   (0x1U << COMP_CSR_RCH13_Pos)

0x10000000

◆ COMP_CSR_RCH13_Pos

#define COMP_CSR_RCH13_Pos   (28U)

◆ COMP_CSR_SPEED

#define COMP_CSR_SPEED   COMP_CSR_SPEED_Msk

Comparator 2 power mode

◆ COMP_CSR_SPEED_Msk

#define COMP_CSR_SPEED_Msk   (0x1U << COMP_CSR_SPEED_Pos)

0x00001000

◆ COMP_CSR_SPEED_Pos

#define COMP_CSR_SPEED_Pos   (12U)

◆ COMP_CSR_SW1

#define COMP_CSR_SW1   COMP_CSR_SW1_Msk

SW1 analog switch enable

◆ COMP_CSR_SW1_Msk

#define COMP_CSR_SW1_Msk   (0x1U << COMP_CSR_SW1_Pos)

0x00000020

◆ COMP_CSR_SW1_Pos

#define COMP_CSR_SW1_Pos   (5U)

◆ COMP_CSR_TSUSP

#define COMP_CSR_TSUSP   COMP_CSR_TSUSP_Msk

Bit 31

◆ COMP_CSR_TSUSP_Msk

#define COMP_CSR_TSUSP_Msk   (0x1U << COMP_CSR_TSUSP_Pos)

0x80000000

◆ COMP_CSR_TSUSP_Pos

#define COMP_CSR_TSUSP_Pos   (31U)

◆ COMP_CSR_VREFOUTEN

#define COMP_CSR_VREFOUTEN   COMP_CSR_VREFOUTEN_Msk

VrefInt output enable on GPIO group 3

◆ COMP_CSR_VREFOUTEN_Msk

#define COMP_CSR_VREFOUTEN_Msk   (0x1U << COMP_CSR_VREFOUTEN_Pos)

0x00010000

◆ COMP_CSR_VREFOUTEN_Pos

#define COMP_CSR_VREFOUTEN_Pos   (16U)

◆ COMP_CSR_WNDWE

#define COMP_CSR_WNDWE   COMP_CSR_WNDWE_Msk

Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef)

◆ COMP_CSR_WNDWE_Msk

#define COMP_CSR_WNDWE_Msk   (0x1U << COMP_CSR_WNDWE_Pos)

0x00020000

◆ COMP_CSR_WNDWE_Pos

#define COMP_CSR_WNDWE_Pos   (17U)

◆ CRC_CR_RESET

#define CRC_CR_RESET   CRC_CR_RESET_Msk

RESET bit

◆ CRC_CR_RESET_Msk

#define CRC_CR_RESET_Msk   (0x1U << CRC_CR_RESET_Pos)

0x00000001

◆ CRC_CR_RESET_Pos

#define CRC_CR_RESET_Pos   (0U)

◆ CRC_DR_DR

#define CRC_DR_DR   CRC_DR_DR_Msk

Data register bits

◆ CRC_DR_DR_Msk

#define CRC_DR_DR_Msk   (0xFFFFFFFFU << CRC_DR_DR_Pos)

0xFFFFFFFF

◆ CRC_DR_DR_Pos

#define CRC_DR_DR_Pos   (0U)

◆ CRC_IDR_IDR

#define CRC_IDR_IDR   CRC_IDR_IDR_Msk

General-purpose 8-bit data register bits

◆ CRC_IDR_IDR_Msk

#define CRC_IDR_IDR_Msk   (0xFFU << CRC_IDR_IDR_Pos)

0x000000FF

◆ CRC_IDR_IDR_Pos

#define CRC_IDR_IDR_Pos   (0U)

◆ DAC_CR_BOFF1

#define DAC_CR_BOFF1   DAC_CR_BOFF1_Msk

DAC channel1 output buffer disable

◆ DAC_CR_BOFF1_Msk

#define DAC_CR_BOFF1_Msk   (0x1U << DAC_CR_BOFF1_Pos)

0x00000002

◆ DAC_CR_BOFF1_Pos

#define DAC_CR_BOFF1_Pos   (1U)

◆ DAC_CR_BOFF2

#define DAC_CR_BOFF2   DAC_CR_BOFF2_Msk

DAC channel2 output buffer disable

◆ DAC_CR_BOFF2_Msk

#define DAC_CR_BOFF2_Msk   (0x1U << DAC_CR_BOFF2_Pos)

0x00020000

◆ DAC_CR_BOFF2_Pos

#define DAC_CR_BOFF2_Pos   (17U)

◆ DAC_CR_DMAEN1

#define DAC_CR_DMAEN1   DAC_CR_DMAEN1_Msk

DAC channel1 DMA enable

◆ DAC_CR_DMAEN1_Msk

#define DAC_CR_DMAEN1_Msk   (0x1U << DAC_CR_DMAEN1_Pos)

0x00001000

◆ DAC_CR_DMAEN1_Pos

#define DAC_CR_DMAEN1_Pos   (12U)

◆ DAC_CR_DMAEN2

#define DAC_CR_DMAEN2   DAC_CR_DMAEN2_Msk

DAC channel2 DMA enabled

◆ DAC_CR_DMAEN2_Msk

#define DAC_CR_DMAEN2_Msk   (0x1U << DAC_CR_DMAEN2_Pos)

0x10000000

◆ DAC_CR_DMAEN2_Pos

#define DAC_CR_DMAEN2_Pos   (28U)

◆ DAC_CR_DMAUDRIE1

#define DAC_CR_DMAUDRIE1   DAC_CR_DMAUDRIE1_Msk

DAC channel1 DMA Interrupt enable

◆ DAC_CR_DMAUDRIE1_Msk

#define DAC_CR_DMAUDRIE1_Msk   (0x1U << DAC_CR_DMAUDRIE1_Pos)

0x00002000

◆ DAC_CR_DMAUDRIE1_Pos

#define DAC_CR_DMAUDRIE1_Pos   (13U)

◆ DAC_CR_DMAUDRIE2

#define DAC_CR_DMAUDRIE2   DAC_CR_DMAUDRIE2_Msk

DAC channel2 DMA underrun interrupt enable

◆ DAC_CR_DMAUDRIE2_Msk

#define DAC_CR_DMAUDRIE2_Msk   (0x1U << DAC_CR_DMAUDRIE2_Pos)

0x20000000

◆ DAC_CR_DMAUDRIE2_Pos

#define DAC_CR_DMAUDRIE2_Pos   (29U)

◆ DAC_CR_EN1

#define DAC_CR_EN1   DAC_CR_EN1_Msk

DAC channel1 enable

◆ DAC_CR_EN1_Msk

#define DAC_CR_EN1_Msk   (0x1U << DAC_CR_EN1_Pos)

0x00000001

◆ DAC_CR_EN1_Pos

#define DAC_CR_EN1_Pos   (0U)

◆ DAC_CR_EN2

#define DAC_CR_EN2   DAC_CR_EN2_Msk

DAC channel2 enable

◆ DAC_CR_EN2_Msk

#define DAC_CR_EN2_Msk   (0x1U << DAC_CR_EN2_Pos)

0x00010000

◆ DAC_CR_EN2_Pos

#define DAC_CR_EN2_Pos   (16U)

◆ DAC_CR_MAMP1

#define DAC_CR_MAMP1   DAC_CR_MAMP1_Msk

MAMP13:0

◆ DAC_CR_MAMP1_0

#define DAC_CR_MAMP1_0   (0x1U << DAC_CR_MAMP1_Pos)

0x00000100

◆ DAC_CR_MAMP1_1

#define DAC_CR_MAMP1_1   (0x2U << DAC_CR_MAMP1_Pos)

0x00000200

◆ DAC_CR_MAMP1_2

#define DAC_CR_MAMP1_2   (0x4U << DAC_CR_MAMP1_Pos)

0x00000400

◆ DAC_CR_MAMP1_3

#define DAC_CR_MAMP1_3   (0x8U << DAC_CR_MAMP1_Pos)

0x00000800

◆ DAC_CR_MAMP1_Msk

#define DAC_CR_MAMP1_Msk   (0xFU << DAC_CR_MAMP1_Pos)

0x00000F00

◆ DAC_CR_MAMP1_Pos

#define DAC_CR_MAMP1_Pos   (8U)

◆ DAC_CR_MAMP2

#define DAC_CR_MAMP2   DAC_CR_MAMP2_Msk

MAMP23:0

◆ DAC_CR_MAMP2_0

#define DAC_CR_MAMP2_0   (0x1U << DAC_CR_MAMP2_Pos)

0x01000000

◆ DAC_CR_MAMP2_1

#define DAC_CR_MAMP2_1   (0x2U << DAC_CR_MAMP2_Pos)

0x02000000

◆ DAC_CR_MAMP2_2

#define DAC_CR_MAMP2_2   (0x4U << DAC_CR_MAMP2_Pos)

0x04000000

◆ DAC_CR_MAMP2_3

#define DAC_CR_MAMP2_3   (0x8U << DAC_CR_MAMP2_Pos)

0x08000000

◆ DAC_CR_MAMP2_Msk

#define DAC_CR_MAMP2_Msk   (0xFU << DAC_CR_MAMP2_Pos)

0x0F000000

◆ DAC_CR_MAMP2_Pos

#define DAC_CR_MAMP2_Pos   (24U)

◆ DAC_CR_TEN1

#define DAC_CR_TEN1   DAC_CR_TEN1_Msk

DAC channel1 Trigger enable

◆ DAC_CR_TEN1_Msk

#define DAC_CR_TEN1_Msk   (0x1U << DAC_CR_TEN1_Pos)

0x00000004

◆ DAC_CR_TEN1_Pos

#define DAC_CR_TEN1_Pos   (2U)

◆ DAC_CR_TEN2

#define DAC_CR_TEN2   DAC_CR_TEN2_Msk

DAC channel2 Trigger enable

◆ DAC_CR_TEN2_Msk

#define DAC_CR_TEN2_Msk   (0x1U << DAC_CR_TEN2_Pos)

0x00040000

◆ DAC_CR_TEN2_Pos

#define DAC_CR_TEN2_Pos   (18U)

◆ DAC_CR_TSEL1

#define DAC_CR_TSEL1   DAC_CR_TSEL1_Msk

TSEL1[2:0] (DAC channel1 Trigger selection)

◆ DAC_CR_TSEL1_0

#define DAC_CR_TSEL1_0   (0x1U << DAC_CR_TSEL1_Pos)

0x00000008

◆ DAC_CR_TSEL1_1

#define DAC_CR_TSEL1_1   (0x2U << DAC_CR_TSEL1_Pos)

0x00000010

◆ DAC_CR_TSEL1_2

#define DAC_CR_TSEL1_2   (0x4U << DAC_CR_TSEL1_Pos)

0x00000020

◆ DAC_CR_TSEL1_Msk

#define DAC_CR_TSEL1_Msk   (0x7U << DAC_CR_TSEL1_Pos)

0x00000038

◆ DAC_CR_TSEL1_Pos

#define DAC_CR_TSEL1_Pos   (3U)

◆ DAC_CR_TSEL2

#define DAC_CR_TSEL2   DAC_CR_TSEL2_Msk

TSEL2[2:0] (DAC channel2 Trigger selection)

◆ DAC_CR_TSEL2_0

#define DAC_CR_TSEL2_0   (0x1U << DAC_CR_TSEL2_Pos)

0x00080000

◆ DAC_CR_TSEL2_1

#define DAC_CR_TSEL2_1   (0x2U << DAC_CR_TSEL2_Pos)

0x00100000

◆ DAC_CR_TSEL2_2

#define DAC_CR_TSEL2_2   (0x4U << DAC_CR_TSEL2_Pos)

0x00200000

◆ DAC_CR_TSEL2_Msk

#define DAC_CR_TSEL2_Msk   (0x7U << DAC_CR_TSEL2_Pos)

0x00380000

◆ DAC_CR_TSEL2_Pos

#define DAC_CR_TSEL2_Pos   (19U)

◆ DAC_CR_WAVE1

#define DAC_CR_WAVE1   DAC_CR_WAVE1_Msk

WAVE11:0

◆ DAC_CR_WAVE1_0

#define DAC_CR_WAVE1_0   (0x1U << DAC_CR_WAVE1_Pos)

0x00000040

◆ DAC_CR_WAVE1_1

#define DAC_CR_WAVE1_1   (0x2U << DAC_CR_WAVE1_Pos)

0x00000080

◆ DAC_CR_WAVE1_Msk

#define DAC_CR_WAVE1_Msk   (0x3U << DAC_CR_WAVE1_Pos)

0x000000C0

◆ DAC_CR_WAVE1_Pos

#define DAC_CR_WAVE1_Pos   (6U)

◆ DAC_CR_WAVE2

#define DAC_CR_WAVE2   DAC_CR_WAVE2_Msk

WAVE21:0

◆ DAC_CR_WAVE2_0

#define DAC_CR_WAVE2_0   (0x1U << DAC_CR_WAVE2_Pos)

0x00400000

◆ DAC_CR_WAVE2_1

#define DAC_CR_WAVE2_1   (0x2U << DAC_CR_WAVE2_Pos)

0x00800000

◆ DAC_CR_WAVE2_Msk

#define DAC_CR_WAVE2_Msk   (0x3U << DAC_CR_WAVE2_Pos)

0x00C00000

◆ DAC_CR_WAVE2_Pos

#define DAC_CR_WAVE2_Pos   (22U)

◆ DAC_DHR12L1_DACC1DHR

#define DAC_DHR12L1_DACC1DHR   DAC_DHR12L1_DACC1DHR_Msk

DAC channel1 12-bit Left aligned data

◆ DAC_DHR12L1_DACC1DHR_Msk

#define DAC_DHR12L1_DACC1DHR_Msk   (0xFFFU << DAC_DHR12L1_DACC1DHR_Pos)

0x0000FFF0

◆ DAC_DHR12L1_DACC1DHR_Pos

#define DAC_DHR12L1_DACC1DHR_Pos   (4U)

◆ DAC_DHR12L2_DACC2DHR

#define DAC_DHR12L2_DACC2DHR   DAC_DHR12L2_DACC2DHR_Msk

DAC channel2 12-bit Left aligned data

◆ DAC_DHR12L2_DACC2DHR_Msk

#define DAC_DHR12L2_DACC2DHR_Msk   (0xFFFU << DAC_DHR12L2_DACC2DHR_Pos)

0x0000FFF0

◆ DAC_DHR12L2_DACC2DHR_Pos

#define DAC_DHR12L2_DACC2DHR_Pos   (4U)

◆ DAC_DHR12LD_DACC1DHR

#define DAC_DHR12LD_DACC1DHR   DAC_DHR12LD_DACC1DHR_Msk

DAC channel1 12-bit Left aligned data

◆ DAC_DHR12LD_DACC1DHR_Msk

#define DAC_DHR12LD_DACC1DHR_Msk   (0xFFFU << DAC_DHR12LD_DACC1DHR_Pos)

0x0000FFF0

◆ DAC_DHR12LD_DACC1DHR_Pos

#define DAC_DHR12LD_DACC1DHR_Pos   (4U)

◆ DAC_DHR12LD_DACC2DHR

#define DAC_DHR12LD_DACC2DHR   DAC_DHR12LD_DACC2DHR_Msk

DAC channel2 12-bit Left aligned data

◆ DAC_DHR12LD_DACC2DHR_Msk

#define DAC_DHR12LD_DACC2DHR_Msk   (0xFFFU << DAC_DHR12LD_DACC2DHR_Pos)

0xFFF00000

◆ DAC_DHR12LD_DACC2DHR_Pos

#define DAC_DHR12LD_DACC2DHR_Pos   (20U)

◆ DAC_DHR12R1_DACC1DHR

#define DAC_DHR12R1_DACC1DHR   DAC_DHR12R1_DACC1DHR_Msk

DAC channel1 12-bit Right aligned data

◆ DAC_DHR12R1_DACC1DHR_Msk

#define DAC_DHR12R1_DACC1DHR_Msk   (0xFFFU << DAC_DHR12R1_DACC1DHR_Pos)

0x00000FFF

◆ DAC_DHR12R1_DACC1DHR_Pos

#define DAC_DHR12R1_DACC1DHR_Pos   (0U)

◆ DAC_DHR12R2_DACC2DHR

#define DAC_DHR12R2_DACC2DHR   DAC_DHR12R2_DACC2DHR_Msk

DAC channel2 12-bit Right aligned data

◆ DAC_DHR12R2_DACC2DHR_Msk

#define DAC_DHR12R2_DACC2DHR_Msk   (0xFFFU << DAC_DHR12R2_DACC2DHR_Pos)

0x00000FFF

◆ DAC_DHR12R2_DACC2DHR_Pos

#define DAC_DHR12R2_DACC2DHR_Pos   (0U)

◆ DAC_DHR12RD_DACC1DHR

#define DAC_DHR12RD_DACC1DHR   DAC_DHR12RD_DACC1DHR_Msk

DAC channel1 12-bit Right aligned data

◆ DAC_DHR12RD_DACC1DHR_Msk

#define DAC_DHR12RD_DACC1DHR_Msk   (0xFFFU << DAC_DHR12RD_DACC1DHR_Pos)

0x00000FFF

◆ DAC_DHR12RD_DACC1DHR_Pos

#define DAC_DHR12RD_DACC1DHR_Pos   (0U)

◆ DAC_DHR12RD_DACC2DHR

#define DAC_DHR12RD_DACC2DHR   DAC_DHR12RD_DACC2DHR_Msk

DAC channel2 12-bit Right aligned data

◆ DAC_DHR12RD_DACC2DHR_Msk

#define DAC_DHR12RD_DACC2DHR_Msk   (0xFFFU << DAC_DHR12RD_DACC2DHR_Pos)

0x0FFF0000

◆ DAC_DHR12RD_DACC2DHR_Pos

#define DAC_DHR12RD_DACC2DHR_Pos   (16U)

◆ DAC_DHR8R1_DACC1DHR

#define DAC_DHR8R1_DACC1DHR   DAC_DHR8R1_DACC1DHR_Msk

DAC channel1 8-bit Right aligned data

◆ DAC_DHR8R1_DACC1DHR_Msk

#define DAC_DHR8R1_DACC1DHR_Msk   (0xFFU << DAC_DHR8R1_DACC1DHR_Pos)

0x000000FF

◆ DAC_DHR8R1_DACC1DHR_Pos

#define DAC_DHR8R1_DACC1DHR_Pos   (0U)

◆ DAC_DHR8R2_DACC2DHR

#define DAC_DHR8R2_DACC2DHR   DAC_DHR8R2_DACC2DHR_Msk

DAC channel2 8-bit Right aligned data

◆ DAC_DHR8R2_DACC2DHR_Msk

#define DAC_DHR8R2_DACC2DHR_Msk   (0xFFU << DAC_DHR8R2_DACC2DHR_Pos)

0x000000FF

◆ DAC_DHR8R2_DACC2DHR_Pos

#define DAC_DHR8R2_DACC2DHR_Pos   (0U)

◆ DAC_DHR8RD_DACC1DHR

#define DAC_DHR8RD_DACC1DHR   DAC_DHR8RD_DACC1DHR_Msk

DAC channel1 8-bit Right aligned data

◆ DAC_DHR8RD_DACC1DHR_Msk

#define DAC_DHR8RD_DACC1DHR_Msk   (0xFFU << DAC_DHR8RD_DACC1DHR_Pos)

0x000000FF

◆ DAC_DHR8RD_DACC1DHR_Pos

#define DAC_DHR8RD_DACC1DHR_Pos   (0U)

◆ DAC_DHR8RD_DACC2DHR

#define DAC_DHR8RD_DACC2DHR   DAC_DHR8RD_DACC2DHR_Msk

DAC channel2 8-bit Right aligned data

◆ DAC_DHR8RD_DACC2DHR_Msk

#define DAC_DHR8RD_DACC2DHR_Msk   (0xFFU << DAC_DHR8RD_DACC2DHR_Pos)

0x0000FF00

◆ DAC_DHR8RD_DACC2DHR_Pos

#define DAC_DHR8RD_DACC2DHR_Pos   (8U)

◆ DAC_DOR1_DACC1DOR

#define DAC_DOR1_DACC1DOR   DAC_DOR1_DACC1DOR_Msk

DAC channel1 data output

◆ DAC_DOR1_DACC1DOR_Msk

#define DAC_DOR1_DACC1DOR_Msk   (0xFFFU << DAC_DOR1_DACC1DOR_Pos)

0x00000FFF

◆ DAC_DOR1_DACC1DOR_Pos

#define DAC_DOR1_DACC1DOR_Pos   (0U)

◆ DAC_DOR2_DACC2DOR

#define DAC_DOR2_DACC2DOR   DAC_DOR2_DACC2DOR_Msk

DAC channel2 data output

◆ DAC_DOR2_DACC2DOR_Msk

#define DAC_DOR2_DACC2DOR_Msk   (0xFFFU << DAC_DOR2_DACC2DOR_Pos)

0x00000FFF

◆ DAC_DOR2_DACC2DOR_Pos

#define DAC_DOR2_DACC2DOR_Pos   (0U)

◆ DAC_SR_DMAUDR1

#define DAC_SR_DMAUDR1   DAC_SR_DMAUDR1_Msk

DAC channel1 DMA underrun flag

◆ DAC_SR_DMAUDR1_Msk

#define DAC_SR_DMAUDR1_Msk   (0x1U << DAC_SR_DMAUDR1_Pos)

0x00002000

◆ DAC_SR_DMAUDR1_Pos

#define DAC_SR_DMAUDR1_Pos   (13U)

◆ DAC_SR_DMAUDR2

#define DAC_SR_DMAUDR2   DAC_SR_DMAUDR2_Msk

DAC channel2 DMA underrun flag

◆ DAC_SR_DMAUDR2_Msk

#define DAC_SR_DMAUDR2_Msk   (0x1U << DAC_SR_DMAUDR2_Pos)

0x20000000

◆ DAC_SR_DMAUDR2_Pos

#define DAC_SR_DMAUDR2_Pos   (29U)

◆ DAC_SWTRIGR_SWTRIG1

#define DAC_SWTRIGR_SWTRIG1   DAC_SWTRIGR_SWTRIG1_Msk

DAC channel1 software trigger

◆ DAC_SWTRIGR_SWTRIG1_Msk

#define DAC_SWTRIGR_SWTRIG1_Msk   (0x1U << DAC_SWTRIGR_SWTRIG1_Pos)

0x00000001

◆ DAC_SWTRIGR_SWTRIG1_Pos

#define DAC_SWTRIGR_SWTRIG1_Pos   (0U)

◆ DAC_SWTRIGR_SWTRIG2

#define DAC_SWTRIGR_SWTRIG2   DAC_SWTRIGR_SWTRIG2_Msk

DAC channel2 software trigger

◆ DAC_SWTRIGR_SWTRIG2_Msk

#define DAC_SWTRIGR_SWTRIG2_Msk   (0x1U << DAC_SWTRIGR_SWTRIG2_Pos)

0x00000002

◆ DAC_SWTRIGR_SWTRIG2_Pos

#define DAC_SWTRIGR_SWTRIG2_Pos   (1U)

◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk

SMBUS timeout mode stopped when Core is halted

◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos)

0x00200000

◆ DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos

#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT_Pos   (21U)

◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT   DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk

SMBUS timeout mode stopped when Core is halted

◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos)

0x00400000

◆ DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos

#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT_Pos   (22U)

◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP   DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk

Debug Independent Watchdog stopped when Core is halted

◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos)

0x00001000

◆ DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_IWDG_STOP_Pos   (12U)

◆ DBGMCU_APB1_FZ_DBG_RTC_STOP

#define DBGMCU_APB1_FZ_DBG_RTC_STOP   DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk

RTC Counter stopped when Core is halted

◆ DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos)

0x00000400

◆ DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_RTC_STOP_Pos   (10U)

◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP   DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk

TIM2 counter stopped when core is halted

◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos)

0x00000001

◆ DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM2_STOP_Pos   (0U)

◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP   DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk

TIM3 counter stopped when core is halted

◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos)

0x00000002

◆ DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM3_STOP_Pos   (1U)

◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP   DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk

TIM4 counter stopped when core is halted

◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos)

0x00000004

◆ DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM4_STOP_Pos   (2U)

◆ DBGMCU_APB1_FZ_DBG_TIM5_STOP

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP   DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk

TIM5 counter stopped when core is halted

◆ DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos)

0x00000008

◆ DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM5_STOP_Pos   (3U)

◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP   DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk

TIM6 counter stopped when core is halted

◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos)

0x00000010

◆ DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM6_STOP_Pos   (4U)

◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP   DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk

TIM7 counter stopped when core is halted

◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos)

0x00000020

◆ DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_TIM7_STOP_Pos   (5U)

◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP   DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk

Debug Window Watchdog stopped when Core is halted

◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Msk   (0x1U << DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos)

0x00000800

◆ DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos

#define DBGMCU_APB1_FZ_DBG_WWDG_STOP_Pos   (11U)

◆ DBGMCU_APB2_FZ_DBG_TIM10_STOP

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP   DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk

TIM10 counter stopped when core is halted

◆ DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Msk   (0x1U << DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos)

0x00000008

◆ DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM10_STOP_Pos   (3U)

◆ DBGMCU_APB2_FZ_DBG_TIM11_STOP

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP   DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk

TIM11 counter stopped when core is halted

◆ DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk   (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos)

0x00000010

◆ DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos   (4U)

◆ DBGMCU_APB2_FZ_DBG_TIM9_STOP

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP   DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk

TIM9 counter stopped when core is halted

◆ DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Msk   (0x1U << DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos)

0x00000004

◆ DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos

#define DBGMCU_APB2_FZ_DBG_TIM9_STOP_Pos   (2U)

◆ DBGMCU_CR_DBG_SLEEP

#define DBGMCU_CR_DBG_SLEEP   DBGMCU_CR_DBG_SLEEP_Msk

Debug Sleep Mode

◆ DBGMCU_CR_DBG_SLEEP_Msk

#define DBGMCU_CR_DBG_SLEEP_Msk   (0x1U << DBGMCU_CR_DBG_SLEEP_Pos)

0x00000001

◆ DBGMCU_CR_DBG_SLEEP_Pos

#define DBGMCU_CR_DBG_SLEEP_Pos   (0U)

◆ DBGMCU_CR_DBG_STANDBY

#define DBGMCU_CR_DBG_STANDBY   DBGMCU_CR_DBG_STANDBY_Msk

Debug Standby mode

◆ DBGMCU_CR_DBG_STANDBY_Msk

#define DBGMCU_CR_DBG_STANDBY_Msk   (0x1U << DBGMCU_CR_DBG_STANDBY_Pos)

0x00000004

◆ DBGMCU_CR_DBG_STANDBY_Pos

#define DBGMCU_CR_DBG_STANDBY_Pos   (2U)

◆ DBGMCU_CR_DBG_STOP

#define DBGMCU_CR_DBG_STOP   DBGMCU_CR_DBG_STOP_Msk

Debug Stop Mode

◆ DBGMCU_CR_DBG_STOP_Msk

#define DBGMCU_CR_DBG_STOP_Msk   (0x1U << DBGMCU_CR_DBG_STOP_Pos)

0x00000002

◆ DBGMCU_CR_DBG_STOP_Pos

#define DBGMCU_CR_DBG_STOP_Pos   (1U)

◆ DBGMCU_CR_TRACE_IOEN

#define DBGMCU_CR_TRACE_IOEN   DBGMCU_CR_TRACE_IOEN_Msk

Trace Pin Assignment Control

◆ DBGMCU_CR_TRACE_IOEN_Msk

#define DBGMCU_CR_TRACE_IOEN_Msk   (0x1U << DBGMCU_CR_TRACE_IOEN_Pos)

0x00000020

◆ DBGMCU_CR_TRACE_IOEN_Pos

#define DBGMCU_CR_TRACE_IOEN_Pos   (5U)

◆ DBGMCU_CR_TRACE_MODE

#define DBGMCU_CR_TRACE_MODE   DBGMCU_CR_TRACE_MODE_Msk

TRACE_MODE[1:0] bits (Trace Pin Assignment Control)

◆ DBGMCU_CR_TRACE_MODE_0

#define DBGMCU_CR_TRACE_MODE_0   (0x1U << DBGMCU_CR_TRACE_MODE_Pos)

0x00000040

◆ DBGMCU_CR_TRACE_MODE_1

#define DBGMCU_CR_TRACE_MODE_1   (0x2U << DBGMCU_CR_TRACE_MODE_Pos)

0x00000080

◆ DBGMCU_CR_TRACE_MODE_Msk

#define DBGMCU_CR_TRACE_MODE_Msk   (0x3U << DBGMCU_CR_TRACE_MODE_Pos)

0x000000C0

◆ DBGMCU_CR_TRACE_MODE_Pos

#define DBGMCU_CR_TRACE_MODE_Pos   (6U)

◆ DBGMCU_IDCODE_DEV_ID

#define DBGMCU_IDCODE_DEV_ID   DBGMCU_IDCODE_DEV_ID_Msk

Device Identifier

◆ DBGMCU_IDCODE_DEV_ID_Msk

#define DBGMCU_IDCODE_DEV_ID_Msk   (0xFFFU << DBGMCU_IDCODE_DEV_ID_Pos)

0x00000FFF

◆ DBGMCU_IDCODE_DEV_ID_Pos

#define DBGMCU_IDCODE_DEV_ID_Pos   (0U)

◆ DBGMCU_IDCODE_REV_ID

#define DBGMCU_IDCODE_REV_ID   DBGMCU_IDCODE_REV_ID_Msk

REV_ID[15:0] bits (Revision Identifier)

◆ DBGMCU_IDCODE_REV_ID_0

#define DBGMCU_IDCODE_REV_ID_0   (0x0001U << DBGMCU_IDCODE_REV_ID_Pos)

0x00010000

◆ DBGMCU_IDCODE_REV_ID_1

#define DBGMCU_IDCODE_REV_ID_1   (0x0002U << DBGMCU_IDCODE_REV_ID_Pos)

0x00020000

◆ DBGMCU_IDCODE_REV_ID_10

#define DBGMCU_IDCODE_REV_ID_10   (0x0400U << DBGMCU_IDCODE_REV_ID_Pos)

0x04000000

◆ DBGMCU_IDCODE_REV_ID_11

#define DBGMCU_IDCODE_REV_ID_11   (0x0800U << DBGMCU_IDCODE_REV_ID_Pos)

0x08000000

◆ DBGMCU_IDCODE_REV_ID_12

#define DBGMCU_IDCODE_REV_ID_12   (0x1000U << DBGMCU_IDCODE_REV_ID_Pos)

0x10000000

◆ DBGMCU_IDCODE_REV_ID_13

#define DBGMCU_IDCODE_REV_ID_13   (0x2000U << DBGMCU_IDCODE_REV_ID_Pos)

0x20000000

◆ DBGMCU_IDCODE_REV_ID_14

#define DBGMCU_IDCODE_REV_ID_14   (0x4000U << DBGMCU_IDCODE_REV_ID_Pos)

0x40000000

◆ DBGMCU_IDCODE_REV_ID_15

#define DBGMCU_IDCODE_REV_ID_15   (0x8000U << DBGMCU_IDCODE_REV_ID_Pos)

0x80000000

◆ DBGMCU_IDCODE_REV_ID_2

#define DBGMCU_IDCODE_REV_ID_2   (0x0004U << DBGMCU_IDCODE_REV_ID_Pos)

0x00040000

◆ DBGMCU_IDCODE_REV_ID_3

#define DBGMCU_IDCODE_REV_ID_3   (0x0008U << DBGMCU_IDCODE_REV_ID_Pos)

0x00080000

◆ DBGMCU_IDCODE_REV_ID_4

#define DBGMCU_IDCODE_REV_ID_4   (0x0010U << DBGMCU_IDCODE_REV_ID_Pos)

0x00100000

◆ DBGMCU_IDCODE_REV_ID_5

#define DBGMCU_IDCODE_REV_ID_5   (0x0020U << DBGMCU_IDCODE_REV_ID_Pos)

0x00200000

◆ DBGMCU_IDCODE_REV_ID_6

#define DBGMCU_IDCODE_REV_ID_6   (0x0040U << DBGMCU_IDCODE_REV_ID_Pos)

0x00400000

◆ DBGMCU_IDCODE_REV_ID_7

#define DBGMCU_IDCODE_REV_ID_7   (0x0080U << DBGMCU_IDCODE_REV_ID_Pos)

0x00800000

◆ DBGMCU_IDCODE_REV_ID_8

#define DBGMCU_IDCODE_REV_ID_8   (0x0100U << DBGMCU_IDCODE_REV_ID_Pos)

0x01000000

◆ DBGMCU_IDCODE_REV_ID_9

#define DBGMCU_IDCODE_REV_ID_9   (0x0200U << DBGMCU_IDCODE_REV_ID_Pos)

0x02000000

◆ DBGMCU_IDCODE_REV_ID_Msk

#define DBGMCU_IDCODE_REV_ID_Msk   (0xFFFFU << DBGMCU_IDCODE_REV_ID_Pos)

0xFFFF0000

◆ DBGMCU_IDCODE_REV_ID_Pos

#define DBGMCU_IDCODE_REV_ID_Pos   (16U)

◆ DMA_CCR_CIRC

#define DMA_CCR_CIRC   DMA_CCR_CIRC_Msk

Circular mode

◆ DMA_CCR_CIRC_Msk

#define DMA_CCR_CIRC_Msk   (0x1U << DMA_CCR_CIRC_Pos)

0x00000020

◆ DMA_CCR_CIRC_Pos

#define DMA_CCR_CIRC_Pos   (5U)

◆ DMA_CCR_DIR

#define DMA_CCR_DIR   DMA_CCR_DIR_Msk

Data transfer direction

◆ DMA_CCR_DIR_Msk

#define DMA_CCR_DIR_Msk   (0x1U << DMA_CCR_DIR_Pos)

0x00000010

◆ DMA_CCR_DIR_Pos

#define DMA_CCR_DIR_Pos   (4U)

◆ DMA_CCR_EN

#define DMA_CCR_EN   DMA_CCR_EN_Msk

Channel enable

◆ DMA_CCR_EN_Msk

#define DMA_CCR_EN_Msk   (0x1U << DMA_CCR_EN_Pos)

0x00000001

◆ DMA_CCR_EN_Pos

#define DMA_CCR_EN_Pos   (0U)

◆ DMA_CCR_HTIE

#define DMA_CCR_HTIE   DMA_CCR_HTIE_Msk

Half Transfer interrupt enable

◆ DMA_CCR_HTIE_Msk

#define DMA_CCR_HTIE_Msk   (0x1U << DMA_CCR_HTIE_Pos)

0x00000004

◆ DMA_CCR_HTIE_Pos

#define DMA_CCR_HTIE_Pos   (2U)

◆ DMA_CCR_MEM2MEM

#define DMA_CCR_MEM2MEM   DMA_CCR_MEM2MEM_Msk

Memory to memory mode

◆ DMA_CCR_MEM2MEM_Msk

#define DMA_CCR_MEM2MEM_Msk   (0x1U << DMA_CCR_MEM2MEM_Pos)

0x00004000

◆ DMA_CCR_MEM2MEM_Pos

#define DMA_CCR_MEM2MEM_Pos   (14U)

◆ DMA_CCR_MINC

#define DMA_CCR_MINC   DMA_CCR_MINC_Msk

Memory increment mode

◆ DMA_CCR_MINC_Msk

#define DMA_CCR_MINC_Msk   (0x1U << DMA_CCR_MINC_Pos)

0x00000080

◆ DMA_CCR_MINC_Pos

#define DMA_CCR_MINC_Pos   (7U)

◆ DMA_CCR_MSIZE

#define DMA_CCR_MSIZE   DMA_CCR_MSIZE_Msk

MSIZE[1:0] bits (Memory size)

◆ DMA_CCR_MSIZE_0

#define DMA_CCR_MSIZE_0   (0x1U << DMA_CCR_MSIZE_Pos)

0x00000400

◆ DMA_CCR_MSIZE_1

#define DMA_CCR_MSIZE_1   (0x2U << DMA_CCR_MSIZE_Pos)

0x00000800

◆ DMA_CCR_MSIZE_Msk

#define DMA_CCR_MSIZE_Msk   (0x3U << DMA_CCR_MSIZE_Pos)

0x00000C00

◆ DMA_CCR_MSIZE_Pos

#define DMA_CCR_MSIZE_Pos   (10U)

◆ DMA_CCR_PINC

#define DMA_CCR_PINC   DMA_CCR_PINC_Msk

Peripheral increment mode

◆ DMA_CCR_PINC_Msk

#define DMA_CCR_PINC_Msk   (0x1U << DMA_CCR_PINC_Pos)

0x00000040

◆ DMA_CCR_PINC_Pos

#define DMA_CCR_PINC_Pos   (6U)

◆ DMA_CCR_PL

#define DMA_CCR_PL   DMA_CCR_PL_Msk

PL[1:0] bits(Channel Priority level)

◆ DMA_CCR_PL_0

#define DMA_CCR_PL_0   (0x1U << DMA_CCR_PL_Pos)

0x00001000

◆ DMA_CCR_PL_1

#define DMA_CCR_PL_1   (0x2U << DMA_CCR_PL_Pos)

0x00002000

◆ DMA_CCR_PL_Msk

#define DMA_CCR_PL_Msk   (0x3U << DMA_CCR_PL_Pos)

0x00003000

◆ DMA_CCR_PL_Pos

#define DMA_CCR_PL_Pos   (12U)

◆ DMA_CCR_PSIZE

#define DMA_CCR_PSIZE   DMA_CCR_PSIZE_Msk

PSIZE[1:0] bits (Peripheral size)

◆ DMA_CCR_PSIZE_0

#define DMA_CCR_PSIZE_0   (0x1U << DMA_CCR_PSIZE_Pos)

0x00000100

◆ DMA_CCR_PSIZE_1

#define DMA_CCR_PSIZE_1   (0x2U << DMA_CCR_PSIZE_Pos)

0x00000200

◆ DMA_CCR_PSIZE_Msk

#define DMA_CCR_PSIZE_Msk   (0x3U << DMA_CCR_PSIZE_Pos)

0x00000300

◆ DMA_CCR_PSIZE_Pos

#define DMA_CCR_PSIZE_Pos   (8U)

◆ DMA_CCR_TCIE

#define DMA_CCR_TCIE   DMA_CCR_TCIE_Msk

Transfer complete interrupt enable

◆ DMA_CCR_TCIE_Msk

#define DMA_CCR_TCIE_Msk   (0x1U << DMA_CCR_TCIE_Pos)

0x00000002

◆ DMA_CCR_TCIE_Pos

#define DMA_CCR_TCIE_Pos   (1U)

◆ DMA_CCR_TEIE

#define DMA_CCR_TEIE   DMA_CCR_TEIE_Msk

Transfer error interrupt enable

◆ DMA_CCR_TEIE_Msk

#define DMA_CCR_TEIE_Msk   (0x1U << DMA_CCR_TEIE_Pos)

0x00000008

◆ DMA_CCR_TEIE_Pos

#define DMA_CCR_TEIE_Pos   (3U)

◆ DMA_CMAR1_MA

#define DMA_CMAR1_MA   DMA_CMAR1_MA_Msk

Memory Address

◆ DMA_CMAR1_MA_Msk

#define DMA_CMAR1_MA_Msk   (0xFFFFFFFFU << DMA_CMAR1_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR1_MA_Pos

#define DMA_CMAR1_MA_Pos   (0U)

◆ DMA_CMAR2_MA

#define DMA_CMAR2_MA   DMA_CMAR2_MA_Msk

Memory Address

◆ DMA_CMAR2_MA_Msk

#define DMA_CMAR2_MA_Msk   (0xFFFFFFFFU << DMA_CMAR2_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR2_MA_Pos

#define DMA_CMAR2_MA_Pos   (0U)

◆ DMA_CMAR3_MA

#define DMA_CMAR3_MA   DMA_CMAR3_MA_Msk

Memory Address

◆ DMA_CMAR3_MA_Msk

#define DMA_CMAR3_MA_Msk   (0xFFFFFFFFU << DMA_CMAR3_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR3_MA_Pos

#define DMA_CMAR3_MA_Pos   (0U)

◆ DMA_CMAR4_MA

#define DMA_CMAR4_MA   DMA_CMAR4_MA_Msk

Memory Address

◆ DMA_CMAR4_MA_Msk

#define DMA_CMAR4_MA_Msk   (0xFFFFFFFFU << DMA_CMAR4_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR4_MA_Pos

#define DMA_CMAR4_MA_Pos   (0U)

◆ DMA_CMAR5_MA

#define DMA_CMAR5_MA   DMA_CMAR5_MA_Msk

Memory Address

◆ DMA_CMAR5_MA_Msk

#define DMA_CMAR5_MA_Msk   (0xFFFFFFFFU << DMA_CMAR5_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR5_MA_Pos

#define DMA_CMAR5_MA_Pos   (0U)

◆ DMA_CMAR6_MA

#define DMA_CMAR6_MA   DMA_CMAR6_MA_Msk

Memory Address

◆ DMA_CMAR6_MA_Msk

#define DMA_CMAR6_MA_Msk   (0xFFFFFFFFU << DMA_CMAR6_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR6_MA_Pos

#define DMA_CMAR6_MA_Pos   (0U)

◆ DMA_CMAR7_MA

#define DMA_CMAR7_MA   DMA_CMAR7_MA_Msk

Memory Address

◆ DMA_CMAR7_MA_Msk

#define DMA_CMAR7_MA_Msk   (0xFFFFFFFFU << DMA_CMAR7_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR7_MA_Pos

#define DMA_CMAR7_MA_Pos   (0U)

◆ DMA_CMAR_MA

#define DMA_CMAR_MA   DMA_CMAR_MA_Msk

Memory Address

◆ DMA_CMAR_MA_Msk

#define DMA_CMAR_MA_Msk   (0xFFFFFFFFU << DMA_CMAR_MA_Pos)

0xFFFFFFFF

◆ DMA_CMAR_MA_Pos

#define DMA_CMAR_MA_Pos   (0U)

◆ DMA_CNDTR1_NDT

#define DMA_CNDTR1_NDT   DMA_CNDTR1_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR1_NDT_Msk

#define DMA_CNDTR1_NDT_Msk   (0xFFFFU << DMA_CNDTR1_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR1_NDT_Pos

#define DMA_CNDTR1_NDT_Pos   (0U)

◆ DMA_CNDTR2_NDT

#define DMA_CNDTR2_NDT   DMA_CNDTR2_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR2_NDT_Msk

#define DMA_CNDTR2_NDT_Msk   (0xFFFFU << DMA_CNDTR2_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR2_NDT_Pos

#define DMA_CNDTR2_NDT_Pos   (0U)

◆ DMA_CNDTR3_NDT

#define DMA_CNDTR3_NDT   DMA_CNDTR3_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR3_NDT_Msk

#define DMA_CNDTR3_NDT_Msk   (0xFFFFU << DMA_CNDTR3_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR3_NDT_Pos

#define DMA_CNDTR3_NDT_Pos   (0U)

◆ DMA_CNDTR4_NDT

#define DMA_CNDTR4_NDT   DMA_CNDTR4_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR4_NDT_Msk

#define DMA_CNDTR4_NDT_Msk   (0xFFFFU << DMA_CNDTR4_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR4_NDT_Pos

#define DMA_CNDTR4_NDT_Pos   (0U)

◆ DMA_CNDTR5_NDT

#define DMA_CNDTR5_NDT   DMA_CNDTR5_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR5_NDT_Msk

#define DMA_CNDTR5_NDT_Msk   (0xFFFFU << DMA_CNDTR5_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR5_NDT_Pos

#define DMA_CNDTR5_NDT_Pos   (0U)

◆ DMA_CNDTR6_NDT

#define DMA_CNDTR6_NDT   DMA_CNDTR6_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR6_NDT_Msk

#define DMA_CNDTR6_NDT_Msk   (0xFFFFU << DMA_CNDTR6_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR6_NDT_Pos

#define DMA_CNDTR6_NDT_Pos   (0U)

◆ DMA_CNDTR7_NDT

#define DMA_CNDTR7_NDT   DMA_CNDTR7_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR7_NDT_Msk

#define DMA_CNDTR7_NDT_Msk   (0xFFFFU << DMA_CNDTR7_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR7_NDT_Pos

#define DMA_CNDTR7_NDT_Pos   (0U)

◆ DMA_CNDTR_NDT

#define DMA_CNDTR_NDT   DMA_CNDTR_NDT_Msk

Number of data to Transfer

◆ DMA_CNDTR_NDT_Msk

#define DMA_CNDTR_NDT_Msk   (0xFFFFU << DMA_CNDTR_NDT_Pos)

0x0000FFFF

◆ DMA_CNDTR_NDT_Pos

#define DMA_CNDTR_NDT_Pos   (0U)

◆ DMA_CPAR1_PA

#define DMA_CPAR1_PA   DMA_CPAR1_PA_Msk

Peripheral Address

◆ DMA_CPAR1_PA_Msk

#define DMA_CPAR1_PA_Msk   (0xFFFFFFFFU << DMA_CPAR1_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR1_PA_Pos

#define DMA_CPAR1_PA_Pos   (0U)

◆ DMA_CPAR2_PA

#define DMA_CPAR2_PA   DMA_CPAR2_PA_Msk

Peripheral Address

◆ DMA_CPAR2_PA_Msk

#define DMA_CPAR2_PA_Msk   (0xFFFFFFFFU << DMA_CPAR2_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR2_PA_Pos

#define DMA_CPAR2_PA_Pos   (0U)

◆ DMA_CPAR3_PA

#define DMA_CPAR3_PA   DMA_CPAR3_PA_Msk

Peripheral Address

◆ DMA_CPAR3_PA_Msk

#define DMA_CPAR3_PA_Msk   (0xFFFFFFFFU << DMA_CPAR3_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR3_PA_Pos

#define DMA_CPAR3_PA_Pos   (0U)

◆ DMA_CPAR4_PA

#define DMA_CPAR4_PA   DMA_CPAR4_PA_Msk

Peripheral Address

◆ DMA_CPAR4_PA_Msk

#define DMA_CPAR4_PA_Msk   (0xFFFFFFFFU << DMA_CPAR4_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR4_PA_Pos

#define DMA_CPAR4_PA_Pos   (0U)

◆ DMA_CPAR5_PA

#define DMA_CPAR5_PA   DMA_CPAR5_PA_Msk

Peripheral Address

◆ DMA_CPAR5_PA_Msk

#define DMA_CPAR5_PA_Msk   (0xFFFFFFFFU << DMA_CPAR5_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR5_PA_Pos

#define DMA_CPAR5_PA_Pos   (0U)

◆ DMA_CPAR6_PA

#define DMA_CPAR6_PA   DMA_CPAR6_PA_Msk

Peripheral Address

◆ DMA_CPAR6_PA_Msk

#define DMA_CPAR6_PA_Msk   (0xFFFFFFFFU << DMA_CPAR6_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR6_PA_Pos

#define DMA_CPAR6_PA_Pos   (0U)

◆ DMA_CPAR7_PA

#define DMA_CPAR7_PA   DMA_CPAR7_PA_Msk

Peripheral Address

◆ DMA_CPAR7_PA_Msk

#define DMA_CPAR7_PA_Msk   (0xFFFFFFFFU << DMA_CPAR7_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR7_PA_Pos

#define DMA_CPAR7_PA_Pos   (0U)

◆ DMA_CPAR_PA

#define DMA_CPAR_PA   DMA_CPAR_PA_Msk

Peripheral Address

◆ DMA_CPAR_PA_Msk

#define DMA_CPAR_PA_Msk   (0xFFFFFFFFU << DMA_CPAR_PA_Pos)

0xFFFFFFFF

◆ DMA_CPAR_PA_Pos

#define DMA_CPAR_PA_Pos   (0U)

◆ DMA_IFCR_CGIF1

#define DMA_IFCR_CGIF1   DMA_IFCR_CGIF1_Msk

Channel 1 Global interrupt clear

◆ DMA_IFCR_CGIF1_Msk

#define DMA_IFCR_CGIF1_Msk   (0x1U << DMA_IFCR_CGIF1_Pos)

0x00000001

◆ DMA_IFCR_CGIF1_Pos

#define DMA_IFCR_CGIF1_Pos   (0U)

◆ DMA_IFCR_CGIF2

#define DMA_IFCR_CGIF2   DMA_IFCR_CGIF2_Msk

Channel 2 Global interrupt clear

◆ DMA_IFCR_CGIF2_Msk

#define DMA_IFCR_CGIF2_Msk   (0x1U << DMA_IFCR_CGIF2_Pos)

0x00000010

◆ DMA_IFCR_CGIF2_Pos

#define DMA_IFCR_CGIF2_Pos   (4U)

◆ DMA_IFCR_CGIF3

#define DMA_IFCR_CGIF3   DMA_IFCR_CGIF3_Msk

Channel 3 Global interrupt clear

◆ DMA_IFCR_CGIF3_Msk

#define DMA_IFCR_CGIF3_Msk   (0x1U << DMA_IFCR_CGIF3_Pos)

0x00000100

◆ DMA_IFCR_CGIF3_Pos

#define DMA_IFCR_CGIF3_Pos   (8U)

◆ DMA_IFCR_CGIF4

#define DMA_IFCR_CGIF4   DMA_IFCR_CGIF4_Msk

Channel 4 Global interrupt clear

◆ DMA_IFCR_CGIF4_Msk

#define DMA_IFCR_CGIF4_Msk   (0x1U << DMA_IFCR_CGIF4_Pos)

0x00001000

◆ DMA_IFCR_CGIF4_Pos

#define DMA_IFCR_CGIF4_Pos   (12U)

◆ DMA_IFCR_CGIF5

#define DMA_IFCR_CGIF5   DMA_IFCR_CGIF5_Msk

Channel 5 Global interrupt clear

◆ DMA_IFCR_CGIF5_Msk

#define DMA_IFCR_CGIF5_Msk   (0x1U << DMA_IFCR_CGIF5_Pos)

0x00010000

◆ DMA_IFCR_CGIF5_Pos

#define DMA_IFCR_CGIF5_Pos   (16U)

◆ DMA_IFCR_CGIF6

#define DMA_IFCR_CGIF6   DMA_IFCR_CGIF6_Msk

Channel 6 Global interrupt clear

◆ DMA_IFCR_CGIF6_Msk

#define DMA_IFCR_CGIF6_Msk   (0x1U << DMA_IFCR_CGIF6_Pos)

0x00100000

◆ DMA_IFCR_CGIF6_Pos

#define DMA_IFCR_CGIF6_Pos   (20U)

◆ DMA_IFCR_CGIF7

#define DMA_IFCR_CGIF7   DMA_IFCR_CGIF7_Msk

Channel 7 Global interrupt clear

◆ DMA_IFCR_CGIF7_Msk

#define DMA_IFCR_CGIF7_Msk   (0x1U << DMA_IFCR_CGIF7_Pos)

0x01000000

◆ DMA_IFCR_CGIF7_Pos

#define DMA_IFCR_CGIF7_Pos   (24U)

◆ DMA_IFCR_CHTIF1

#define DMA_IFCR_CHTIF1   DMA_IFCR_CHTIF1_Msk

Channel 1 Half Transfer clear

◆ DMA_IFCR_CHTIF1_Msk

#define DMA_IFCR_CHTIF1_Msk   (0x1U << DMA_IFCR_CHTIF1_Pos)

0x00000004

◆ DMA_IFCR_CHTIF1_Pos

#define DMA_IFCR_CHTIF1_Pos   (2U)

◆ DMA_IFCR_CHTIF2

#define DMA_IFCR_CHTIF2   DMA_IFCR_CHTIF2_Msk

Channel 2 Half Transfer clear

◆ DMA_IFCR_CHTIF2_Msk

#define DMA_IFCR_CHTIF2_Msk   (0x1U << DMA_IFCR_CHTIF2_Pos)

0x00000040

◆ DMA_IFCR_CHTIF2_Pos

#define DMA_IFCR_CHTIF2_Pos   (6U)

◆ DMA_IFCR_CHTIF3

#define DMA_IFCR_CHTIF3   DMA_IFCR_CHTIF3_Msk

Channel 3 Half Transfer clear

◆ DMA_IFCR_CHTIF3_Msk

#define DMA_IFCR_CHTIF3_Msk   (0x1U << DMA_IFCR_CHTIF3_Pos)

0x00000400

◆ DMA_IFCR_CHTIF3_Pos

#define DMA_IFCR_CHTIF3_Pos   (10U)

◆ DMA_IFCR_CHTIF4

#define DMA_IFCR_CHTIF4   DMA_IFCR_CHTIF4_Msk

Channel 4 Half Transfer clear

◆ DMA_IFCR_CHTIF4_Msk

#define DMA_IFCR_CHTIF4_Msk   (0x1U << DMA_IFCR_CHTIF4_Pos)

0x00004000

◆ DMA_IFCR_CHTIF4_Pos

#define DMA_IFCR_CHTIF4_Pos   (14U)

◆ DMA_IFCR_CHTIF5

#define DMA_IFCR_CHTIF5   DMA_IFCR_CHTIF5_Msk

Channel 5 Half Transfer clear

◆ DMA_IFCR_CHTIF5_Msk

#define DMA_IFCR_CHTIF5_Msk   (0x1U << DMA_IFCR_CHTIF5_Pos)

0x00040000

◆ DMA_IFCR_CHTIF5_Pos

#define DMA_IFCR_CHTIF5_Pos   (18U)

◆ DMA_IFCR_CHTIF6

#define DMA_IFCR_CHTIF6   DMA_IFCR_CHTIF6_Msk

Channel 6 Half Transfer clear

◆ DMA_IFCR_CHTIF6_Msk

#define DMA_IFCR_CHTIF6_Msk   (0x1U << DMA_IFCR_CHTIF6_Pos)

0x00400000

◆ DMA_IFCR_CHTIF6_Pos

#define DMA_IFCR_CHTIF6_Pos   (22U)

◆ DMA_IFCR_CHTIF7

#define DMA_IFCR_CHTIF7   DMA_IFCR_CHTIF7_Msk

Channel 7 Half Transfer clear

◆ DMA_IFCR_CHTIF7_Msk

#define DMA_IFCR_CHTIF7_Msk   (0x1U << DMA_IFCR_CHTIF7_Pos)

0x04000000

◆ DMA_IFCR_CHTIF7_Pos

#define DMA_IFCR_CHTIF7_Pos   (26U)

◆ DMA_IFCR_CTCIF1

#define DMA_IFCR_CTCIF1   DMA_IFCR_CTCIF1_Msk

Channel 1 Transfer Complete clear

◆ DMA_IFCR_CTCIF1_Msk

#define DMA_IFCR_CTCIF1_Msk   (0x1U << DMA_IFCR_CTCIF1_Pos)

0x00000002

◆ DMA_IFCR_CTCIF1_Pos

#define DMA_IFCR_CTCIF1_Pos   (1U)

◆ DMA_IFCR_CTCIF2

#define DMA_IFCR_CTCIF2   DMA_IFCR_CTCIF2_Msk

Channel 2 Transfer Complete clear

◆ DMA_IFCR_CTCIF2_Msk

#define DMA_IFCR_CTCIF2_Msk   (0x1U << DMA_IFCR_CTCIF2_Pos)

0x00000020

◆ DMA_IFCR_CTCIF2_Pos

#define DMA_IFCR_CTCIF2_Pos   (5U)

◆ DMA_IFCR_CTCIF3

#define DMA_IFCR_CTCIF3   DMA_IFCR_CTCIF3_Msk

Channel 3 Transfer Complete clear

◆ DMA_IFCR_CTCIF3_Msk

#define DMA_IFCR_CTCIF3_Msk   (0x1U << DMA_IFCR_CTCIF3_Pos)

0x00000200

◆ DMA_IFCR_CTCIF3_Pos

#define DMA_IFCR_CTCIF3_Pos   (9U)

◆ DMA_IFCR_CTCIF4

#define DMA_IFCR_CTCIF4   DMA_IFCR_CTCIF4_Msk

Channel 4 Transfer Complete clear

◆ DMA_IFCR_CTCIF4_Msk

#define DMA_IFCR_CTCIF4_Msk   (0x1U << DMA_IFCR_CTCIF4_Pos)

0x00002000

◆ DMA_IFCR_CTCIF4_Pos

#define DMA_IFCR_CTCIF4_Pos   (13U)

◆ DMA_IFCR_CTCIF5

#define DMA_IFCR_CTCIF5   DMA_IFCR_CTCIF5_Msk

Channel 5 Transfer Complete clear

◆ DMA_IFCR_CTCIF5_Msk

#define DMA_IFCR_CTCIF5_Msk   (0x1U << DMA_IFCR_CTCIF5_Pos)

0x00020000

◆ DMA_IFCR_CTCIF5_Pos

#define DMA_IFCR_CTCIF5_Pos   (17U)

◆ DMA_IFCR_CTCIF6

#define DMA_IFCR_CTCIF6   DMA_IFCR_CTCIF6_Msk

Channel 6 Transfer Complete clear

◆ DMA_IFCR_CTCIF6_Msk

#define DMA_IFCR_CTCIF6_Msk   (0x1U << DMA_IFCR_CTCIF6_Pos)

0x00200000

◆ DMA_IFCR_CTCIF6_Pos

#define DMA_IFCR_CTCIF6_Pos   (21U)

◆ DMA_IFCR_CTCIF7

#define DMA_IFCR_CTCIF7   DMA_IFCR_CTCIF7_Msk

Channel 7 Transfer Complete clear

◆ DMA_IFCR_CTCIF7_Msk

#define DMA_IFCR_CTCIF7_Msk   (0x1U << DMA_IFCR_CTCIF7_Pos)

0x02000000

◆ DMA_IFCR_CTCIF7_Pos

#define DMA_IFCR_CTCIF7_Pos   (25U)

◆ DMA_IFCR_CTEIF1

#define DMA_IFCR_CTEIF1   DMA_IFCR_CTEIF1_Msk

Channel 1 Transfer Error clear

◆ DMA_IFCR_CTEIF1_Msk

#define DMA_IFCR_CTEIF1_Msk   (0x1U << DMA_IFCR_CTEIF1_Pos)

0x00000008

◆ DMA_IFCR_CTEIF1_Pos

#define DMA_IFCR_CTEIF1_Pos   (3U)

◆ DMA_IFCR_CTEIF2

#define DMA_IFCR_CTEIF2   DMA_IFCR_CTEIF2_Msk

Channel 2 Transfer Error clear

◆ DMA_IFCR_CTEIF2_Msk

#define DMA_IFCR_CTEIF2_Msk   (0x1U << DMA_IFCR_CTEIF2_Pos)

0x00000080

◆ DMA_IFCR_CTEIF2_Pos

#define DMA_IFCR_CTEIF2_Pos   (7U)

◆ DMA_IFCR_CTEIF3

#define DMA_IFCR_CTEIF3   DMA_IFCR_CTEIF3_Msk

Channel 3 Transfer Error clear

◆ DMA_IFCR_CTEIF3_Msk

#define DMA_IFCR_CTEIF3_Msk   (0x1U << DMA_IFCR_CTEIF3_Pos)

0x00000800

◆ DMA_IFCR_CTEIF3_Pos

#define DMA_IFCR_CTEIF3_Pos   (11U)

◆ DMA_IFCR_CTEIF4

#define DMA_IFCR_CTEIF4   DMA_IFCR_CTEIF4_Msk

Channel 4 Transfer Error clear

◆ DMA_IFCR_CTEIF4_Msk

#define DMA_IFCR_CTEIF4_Msk   (0x1U << DMA_IFCR_CTEIF4_Pos)

0x00008000

◆ DMA_IFCR_CTEIF4_Pos

#define DMA_IFCR_CTEIF4_Pos   (15U)

◆ DMA_IFCR_CTEIF5

#define DMA_IFCR_CTEIF5   DMA_IFCR_CTEIF5_Msk

Channel 5 Transfer Error clear

◆ DMA_IFCR_CTEIF5_Msk

#define DMA_IFCR_CTEIF5_Msk   (0x1U << DMA_IFCR_CTEIF5_Pos)

0x00080000

◆ DMA_IFCR_CTEIF5_Pos

#define DMA_IFCR_CTEIF5_Pos   (19U)

◆ DMA_IFCR_CTEIF6

#define DMA_IFCR_CTEIF6   DMA_IFCR_CTEIF6_Msk

Channel 6 Transfer Error clear

◆ DMA_IFCR_CTEIF6_Msk

#define DMA_IFCR_CTEIF6_Msk   (0x1U << DMA_IFCR_CTEIF6_Pos)

0x00800000

◆ DMA_IFCR_CTEIF6_Pos

#define DMA_IFCR_CTEIF6_Pos   (23U)

◆ DMA_IFCR_CTEIF7

#define DMA_IFCR_CTEIF7   DMA_IFCR_CTEIF7_Msk

Channel 7 Transfer Error clear

◆ DMA_IFCR_CTEIF7_Msk

#define DMA_IFCR_CTEIF7_Msk   (0x1U << DMA_IFCR_CTEIF7_Pos)

0x08000000

◆ DMA_IFCR_CTEIF7_Pos

#define DMA_IFCR_CTEIF7_Pos   (27U)

◆ DMA_ISR_GIF1

#define DMA_ISR_GIF1   DMA_ISR_GIF1_Msk

Channel 1 Global interrupt flag

◆ DMA_ISR_GIF1_Msk

#define DMA_ISR_GIF1_Msk   (0x1U << DMA_ISR_GIF1_Pos)

0x00000001

◆ DMA_ISR_GIF1_Pos

#define DMA_ISR_GIF1_Pos   (0U)

◆ DMA_ISR_GIF2

#define DMA_ISR_GIF2   DMA_ISR_GIF2_Msk

Channel 2 Global interrupt flag

◆ DMA_ISR_GIF2_Msk

#define DMA_ISR_GIF2_Msk   (0x1U << DMA_ISR_GIF2_Pos)

0x00000010

◆ DMA_ISR_GIF2_Pos

#define DMA_ISR_GIF2_Pos   (4U)

◆ DMA_ISR_GIF3

#define DMA_ISR_GIF3   DMA_ISR_GIF3_Msk

Channel 3 Global interrupt flag

◆ DMA_ISR_GIF3_Msk

#define DMA_ISR_GIF3_Msk   (0x1U << DMA_ISR_GIF3_Pos)

0x00000100

◆ DMA_ISR_GIF3_Pos

#define DMA_ISR_GIF3_Pos   (8U)

◆ DMA_ISR_GIF4

#define DMA_ISR_GIF4   DMA_ISR_GIF4_Msk

Channel 4 Global interrupt flag

◆ DMA_ISR_GIF4_Msk

#define DMA_ISR_GIF4_Msk   (0x1U << DMA_ISR_GIF4_Pos)

0x00001000

◆ DMA_ISR_GIF4_Pos

#define DMA_ISR_GIF4_Pos   (12U)

◆ DMA_ISR_GIF5

#define DMA_ISR_GIF5   DMA_ISR_GIF5_Msk

Channel 5 Global interrupt flag

◆ DMA_ISR_GIF5_Msk

#define DMA_ISR_GIF5_Msk   (0x1U << DMA_ISR_GIF5_Pos)

0x00010000

◆ DMA_ISR_GIF5_Pos

#define DMA_ISR_GIF5_Pos   (16U)

◆ DMA_ISR_GIF6

#define DMA_ISR_GIF6   DMA_ISR_GIF6_Msk

Channel 6 Global interrupt flag

◆ DMA_ISR_GIF6_Msk

#define DMA_ISR_GIF6_Msk   (0x1U << DMA_ISR_GIF6_Pos)

0x00100000

◆ DMA_ISR_GIF6_Pos

#define DMA_ISR_GIF6_Pos   (20U)

◆ DMA_ISR_GIF7

#define DMA_ISR_GIF7   DMA_ISR_GIF7_Msk

Channel 7 Global interrupt flag

◆ DMA_ISR_GIF7_Msk

#define DMA_ISR_GIF7_Msk   (0x1U << DMA_ISR_GIF7_Pos)

0x01000000

◆ DMA_ISR_GIF7_Pos

#define DMA_ISR_GIF7_Pos   (24U)

◆ DMA_ISR_HTIF1

#define DMA_ISR_HTIF1   DMA_ISR_HTIF1_Msk

Channel 1 Half Transfer flag

◆ DMA_ISR_HTIF1_Msk

#define DMA_ISR_HTIF1_Msk   (0x1U << DMA_ISR_HTIF1_Pos)

0x00000004

◆ DMA_ISR_HTIF1_Pos

#define DMA_ISR_HTIF1_Pos   (2U)

◆ DMA_ISR_HTIF2

#define DMA_ISR_HTIF2   DMA_ISR_HTIF2_Msk

Channel 2 Half Transfer flag

◆ DMA_ISR_HTIF2_Msk

#define DMA_ISR_HTIF2_Msk   (0x1U << DMA_ISR_HTIF2_Pos)

0x00000040

◆ DMA_ISR_HTIF2_Pos

#define DMA_ISR_HTIF2_Pos   (6U)

◆ DMA_ISR_HTIF3

#define DMA_ISR_HTIF3   DMA_ISR_HTIF3_Msk

Channel 3 Half Transfer flag

◆ DMA_ISR_HTIF3_Msk

#define DMA_ISR_HTIF3_Msk   (0x1U << DMA_ISR_HTIF3_Pos)

0x00000400

◆ DMA_ISR_HTIF3_Pos

#define DMA_ISR_HTIF3_Pos   (10U)

◆ DMA_ISR_HTIF4

#define DMA_ISR_HTIF4   DMA_ISR_HTIF4_Msk

Channel 4 Half Transfer flag

◆ DMA_ISR_HTIF4_Msk

#define DMA_ISR_HTIF4_Msk   (0x1U << DMA_ISR_HTIF4_Pos)

0x00004000

◆ DMA_ISR_HTIF4_Pos

#define DMA_ISR_HTIF4_Pos   (14U)

◆ DMA_ISR_HTIF5

#define DMA_ISR_HTIF5   DMA_ISR_HTIF5_Msk

Channel 5 Half Transfer flag

◆ DMA_ISR_HTIF5_Msk

#define DMA_ISR_HTIF5_Msk   (0x1U << DMA_ISR_HTIF5_Pos)

0x00040000

◆ DMA_ISR_HTIF5_Pos

#define DMA_ISR_HTIF5_Pos   (18U)

◆ DMA_ISR_HTIF6

#define DMA_ISR_HTIF6   DMA_ISR_HTIF6_Msk

Channel 6 Half Transfer flag

◆ DMA_ISR_HTIF6_Msk

#define DMA_ISR_HTIF6_Msk   (0x1U << DMA_ISR_HTIF6_Pos)

0x00400000

◆ DMA_ISR_HTIF6_Pos

#define DMA_ISR_HTIF6_Pos   (22U)

◆ DMA_ISR_HTIF7

#define DMA_ISR_HTIF7   DMA_ISR_HTIF7_Msk

Channel 7 Half Transfer flag

◆ DMA_ISR_HTIF7_Msk

#define DMA_ISR_HTIF7_Msk   (0x1U << DMA_ISR_HTIF7_Pos)

0x04000000

◆ DMA_ISR_HTIF7_Pos

#define DMA_ISR_HTIF7_Pos   (26U)

◆ DMA_ISR_TCIF1

#define DMA_ISR_TCIF1   DMA_ISR_TCIF1_Msk

Channel 1 Transfer Complete flag

◆ DMA_ISR_TCIF1_Msk

#define DMA_ISR_TCIF1_Msk   (0x1U << DMA_ISR_TCIF1_Pos)

0x00000002

◆ DMA_ISR_TCIF1_Pos

#define DMA_ISR_TCIF1_Pos   (1U)

◆ DMA_ISR_TCIF2

#define DMA_ISR_TCIF2   DMA_ISR_TCIF2_Msk

Channel 2 Transfer Complete flag

◆ DMA_ISR_TCIF2_Msk

#define DMA_ISR_TCIF2_Msk   (0x1U << DMA_ISR_TCIF2_Pos)

0x00000020

◆ DMA_ISR_TCIF2_Pos

#define DMA_ISR_TCIF2_Pos   (5U)

◆ DMA_ISR_TCIF3

#define DMA_ISR_TCIF3   DMA_ISR_TCIF3_Msk

Channel 3 Transfer Complete flag

◆ DMA_ISR_TCIF3_Msk

#define DMA_ISR_TCIF3_Msk   (0x1U << DMA_ISR_TCIF3_Pos)

0x00000200

◆ DMA_ISR_TCIF3_Pos

#define DMA_ISR_TCIF3_Pos   (9U)

◆ DMA_ISR_TCIF4

#define DMA_ISR_TCIF4   DMA_ISR_TCIF4_Msk

Channel 4 Transfer Complete flag

◆ DMA_ISR_TCIF4_Msk

#define DMA_ISR_TCIF4_Msk   (0x1U << DMA_ISR_TCIF4_Pos)

0x00002000

◆ DMA_ISR_TCIF4_Pos

#define DMA_ISR_TCIF4_Pos   (13U)

◆ DMA_ISR_TCIF5

#define DMA_ISR_TCIF5   DMA_ISR_TCIF5_Msk

Channel 5 Transfer Complete flag

◆ DMA_ISR_TCIF5_Msk

#define DMA_ISR_TCIF5_Msk   (0x1U << DMA_ISR_TCIF5_Pos)

0x00020000

◆ DMA_ISR_TCIF5_Pos

#define DMA_ISR_TCIF5_Pos   (17U)

◆ DMA_ISR_TCIF6

#define DMA_ISR_TCIF6   DMA_ISR_TCIF6_Msk

Channel 6 Transfer Complete flag

◆ DMA_ISR_TCIF6_Msk

#define DMA_ISR_TCIF6_Msk   (0x1U << DMA_ISR_TCIF6_Pos)

0x00200000

◆ DMA_ISR_TCIF6_Pos

#define DMA_ISR_TCIF6_Pos   (21U)

◆ DMA_ISR_TCIF7

#define DMA_ISR_TCIF7   DMA_ISR_TCIF7_Msk

Channel 7 Transfer Complete flag

◆ DMA_ISR_TCIF7_Msk

#define DMA_ISR_TCIF7_Msk   (0x1U << DMA_ISR_TCIF7_Pos)

0x02000000

◆ DMA_ISR_TCIF7_Pos

#define DMA_ISR_TCIF7_Pos   (25U)

◆ DMA_ISR_TEIF1

#define DMA_ISR_TEIF1   DMA_ISR_TEIF1_Msk

Channel 1 Transfer Error flag

◆ DMA_ISR_TEIF1_Msk

#define DMA_ISR_TEIF1_Msk   (0x1U << DMA_ISR_TEIF1_Pos)

0x00000008

◆ DMA_ISR_TEIF1_Pos

#define DMA_ISR_TEIF1_Pos   (3U)

◆ DMA_ISR_TEIF2

#define DMA_ISR_TEIF2   DMA_ISR_TEIF2_Msk

Channel 2 Transfer Error flag

◆ DMA_ISR_TEIF2_Msk

#define DMA_ISR_TEIF2_Msk   (0x1U << DMA_ISR_TEIF2_Pos)

0x00000080

◆ DMA_ISR_TEIF2_Pos

#define DMA_ISR_TEIF2_Pos   (7U)

◆ DMA_ISR_TEIF3

#define DMA_ISR_TEIF3   DMA_ISR_TEIF3_Msk

Channel 3 Transfer Error flag

◆ DMA_ISR_TEIF3_Msk

#define DMA_ISR_TEIF3_Msk   (0x1U << DMA_ISR_TEIF3_Pos)

0x00000800

◆ DMA_ISR_TEIF3_Pos

#define DMA_ISR_TEIF3_Pos   (11U)

◆ DMA_ISR_TEIF4

#define DMA_ISR_TEIF4   DMA_ISR_TEIF4_Msk

Channel 4 Transfer Error flag

◆ DMA_ISR_TEIF4_Msk

#define DMA_ISR_TEIF4_Msk   (0x1U << DMA_ISR_TEIF4_Pos)

0x00008000

◆ DMA_ISR_TEIF4_Pos

#define DMA_ISR_TEIF4_Pos   (15U)

◆ DMA_ISR_TEIF5

#define DMA_ISR_TEIF5   DMA_ISR_TEIF5_Msk

Channel 5 Transfer Error flag

◆ DMA_ISR_TEIF5_Msk

#define DMA_ISR_TEIF5_Msk   (0x1U << DMA_ISR_TEIF5_Pos)

0x00080000

◆ DMA_ISR_TEIF5_Pos

#define DMA_ISR_TEIF5_Pos   (19U)

◆ DMA_ISR_TEIF6

#define DMA_ISR_TEIF6   DMA_ISR_TEIF6_Msk

Channel 6 Transfer Error flag

◆ DMA_ISR_TEIF6_Msk

#define DMA_ISR_TEIF6_Msk   (0x1U << DMA_ISR_TEIF6_Pos)

0x00800000

◆ DMA_ISR_TEIF6_Pos

#define DMA_ISR_TEIF6_Pos   (23U)

◆ DMA_ISR_TEIF7

#define DMA_ISR_TEIF7   DMA_ISR_TEIF7_Msk

Channel 7 Transfer Error flag

◆ DMA_ISR_TEIF7_Msk

#define DMA_ISR_TEIF7_Msk   (0x1U << DMA_ISR_TEIF7_Pos)

0x08000000

◆ DMA_ISR_TEIF7_Pos

#define DMA_ISR_TEIF7_Pos   (27U)

◆ EXTI_EMR_EM0

#define EXTI_EMR_EM0   EXTI_EMR_MR0

◆ EXTI_EMR_EM1

#define EXTI_EMR_EM1   EXTI_EMR_MR1

◆ EXTI_EMR_EM10

#define EXTI_EMR_EM10   EXTI_EMR_MR10

◆ EXTI_EMR_EM11

#define EXTI_EMR_EM11   EXTI_EMR_MR11

◆ EXTI_EMR_EM12

#define EXTI_EMR_EM12   EXTI_EMR_MR12

◆ EXTI_EMR_EM13

#define EXTI_EMR_EM13   EXTI_EMR_MR13

◆ EXTI_EMR_EM14

#define EXTI_EMR_EM14   EXTI_EMR_MR14

◆ EXTI_EMR_EM15

#define EXTI_EMR_EM15   EXTI_EMR_MR15

◆ EXTI_EMR_EM16

#define EXTI_EMR_EM16   EXTI_EMR_MR16

◆ EXTI_EMR_EM17

#define EXTI_EMR_EM17   EXTI_EMR_MR17

◆ EXTI_EMR_EM18

#define EXTI_EMR_EM18   EXTI_EMR_MR18

◆ EXTI_EMR_EM19

#define EXTI_EMR_EM19   EXTI_EMR_MR19

◆ EXTI_EMR_EM2

#define EXTI_EMR_EM2   EXTI_EMR_MR2

◆ EXTI_EMR_EM20

#define EXTI_EMR_EM20   EXTI_EMR_MR20

◆ EXTI_EMR_EM21

#define EXTI_EMR_EM21   EXTI_EMR_MR21

◆ EXTI_EMR_EM22

#define EXTI_EMR_EM22   EXTI_EMR_MR22

◆ EXTI_EMR_EM23

#define EXTI_EMR_EM23   EXTI_EMR_MR23

◆ EXTI_EMR_EM3

#define EXTI_EMR_EM3   EXTI_EMR_MR3

◆ EXTI_EMR_EM4

#define EXTI_EMR_EM4   EXTI_EMR_MR4

◆ EXTI_EMR_EM5

#define EXTI_EMR_EM5   EXTI_EMR_MR5

◆ EXTI_EMR_EM6

#define EXTI_EMR_EM6   EXTI_EMR_MR6

◆ EXTI_EMR_EM7

#define EXTI_EMR_EM7   EXTI_EMR_MR7

◆ EXTI_EMR_EM8

#define EXTI_EMR_EM8   EXTI_EMR_MR8

◆ EXTI_EMR_EM9

#define EXTI_EMR_EM9   EXTI_EMR_MR9

◆ EXTI_EMR_MR0

#define EXTI_EMR_MR0   EXTI_EMR_MR0_Msk

Event Mask on line 0

◆ EXTI_EMR_MR0_Msk

#define EXTI_EMR_MR0_Msk   (0x1U << EXTI_EMR_MR0_Pos)

0x00000001

◆ EXTI_EMR_MR0_Pos

#define EXTI_EMR_MR0_Pos   (0U)

◆ EXTI_EMR_MR1

#define EXTI_EMR_MR1   EXTI_EMR_MR1_Msk

Event Mask on line 1

◆ EXTI_EMR_MR10

#define EXTI_EMR_MR10   EXTI_EMR_MR10_Msk

Event Mask on line 10

◆ EXTI_EMR_MR10_Msk

#define EXTI_EMR_MR10_Msk   (0x1U << EXTI_EMR_MR10_Pos)

0x00000400

◆ EXTI_EMR_MR10_Pos

#define EXTI_EMR_MR10_Pos   (10U)

◆ EXTI_EMR_MR11

#define EXTI_EMR_MR11   EXTI_EMR_MR11_Msk

Event Mask on line 11

◆ EXTI_EMR_MR11_Msk

#define EXTI_EMR_MR11_Msk   (0x1U << EXTI_EMR_MR11_Pos)

0x00000800

◆ EXTI_EMR_MR11_Pos

#define EXTI_EMR_MR11_Pos   (11U)

◆ EXTI_EMR_MR12

#define EXTI_EMR_MR12   EXTI_EMR_MR12_Msk

Event Mask on line 12

◆ EXTI_EMR_MR12_Msk

#define EXTI_EMR_MR12_Msk   (0x1U << EXTI_EMR_MR12_Pos)

0x00001000

◆ EXTI_EMR_MR12_Pos

#define EXTI_EMR_MR12_Pos   (12U)

◆ EXTI_EMR_MR13

#define EXTI_EMR_MR13   EXTI_EMR_MR13_Msk

Event Mask on line 13

◆ EXTI_EMR_MR13_Msk

#define EXTI_EMR_MR13_Msk   (0x1U << EXTI_EMR_MR13_Pos)

0x00002000

◆ EXTI_EMR_MR13_Pos

#define EXTI_EMR_MR13_Pos   (13U)

◆ EXTI_EMR_MR14

#define EXTI_EMR_MR14   EXTI_EMR_MR14_Msk

Event Mask on line 14

◆ EXTI_EMR_MR14_Msk

#define EXTI_EMR_MR14_Msk   (0x1U << EXTI_EMR_MR14_Pos)

0x00004000

◆ EXTI_EMR_MR14_Pos

#define EXTI_EMR_MR14_Pos   (14U)

◆ EXTI_EMR_MR15

#define EXTI_EMR_MR15   EXTI_EMR_MR15_Msk

Event Mask on line 15

◆ EXTI_EMR_MR15_Msk

#define EXTI_EMR_MR15_Msk   (0x1U << EXTI_EMR_MR15_Pos)

0x00008000

◆ EXTI_EMR_MR15_Pos

#define EXTI_EMR_MR15_Pos   (15U)

◆ EXTI_EMR_MR16

#define EXTI_EMR_MR16   EXTI_EMR_MR16_Msk

Event Mask on line 16

◆ EXTI_EMR_MR16_Msk

#define EXTI_EMR_MR16_Msk   (0x1U << EXTI_EMR_MR16_Pos)

0x00010000

◆ EXTI_EMR_MR16_Pos

#define EXTI_EMR_MR16_Pos   (16U)

◆ EXTI_EMR_MR17

#define EXTI_EMR_MR17   EXTI_EMR_MR17_Msk

Event Mask on line 17

◆ EXTI_EMR_MR17_Msk

#define EXTI_EMR_MR17_Msk   (0x1U << EXTI_EMR_MR17_Pos)

0x00020000

◆ EXTI_EMR_MR17_Pos

#define EXTI_EMR_MR17_Pos   (17U)

◆ EXTI_EMR_MR18

#define EXTI_EMR_MR18   EXTI_EMR_MR18_Msk

Event Mask on line 18

◆ EXTI_EMR_MR18_Msk

#define EXTI_EMR_MR18_Msk   (0x1U << EXTI_EMR_MR18_Pos)

0x00040000

◆ EXTI_EMR_MR18_Pos

#define EXTI_EMR_MR18_Pos   (18U)

◆ EXTI_EMR_MR19

#define EXTI_EMR_MR19   EXTI_EMR_MR19_Msk

Event Mask on line 19

◆ EXTI_EMR_MR19_Msk

#define EXTI_EMR_MR19_Msk   (0x1U << EXTI_EMR_MR19_Pos)

0x00080000

◆ EXTI_EMR_MR19_Pos

#define EXTI_EMR_MR19_Pos   (19U)

◆ EXTI_EMR_MR1_Msk

#define EXTI_EMR_MR1_Msk   (0x1U << EXTI_EMR_MR1_Pos)

0x00000002

◆ EXTI_EMR_MR1_Pos

#define EXTI_EMR_MR1_Pos   (1U)

◆ EXTI_EMR_MR2

#define EXTI_EMR_MR2   EXTI_EMR_MR2_Msk

Event Mask on line 2

◆ EXTI_EMR_MR20

#define EXTI_EMR_MR20   EXTI_EMR_MR20_Msk

Event Mask on line 20

◆ EXTI_EMR_MR20_Msk

#define EXTI_EMR_MR20_Msk   (0x1U << EXTI_EMR_MR20_Pos)

0x00100000

◆ EXTI_EMR_MR20_Pos

#define EXTI_EMR_MR20_Pos   (20U)

◆ EXTI_EMR_MR21

#define EXTI_EMR_MR21   EXTI_EMR_MR21_Msk

Event Mask on line 21

◆ EXTI_EMR_MR21_Msk

#define EXTI_EMR_MR21_Msk   (0x1U << EXTI_EMR_MR21_Pos)

0x00200000

◆ EXTI_EMR_MR21_Pos

#define EXTI_EMR_MR21_Pos   (21U)

◆ EXTI_EMR_MR22

#define EXTI_EMR_MR22   EXTI_EMR_MR22_Msk

Event Mask on line 22

◆ EXTI_EMR_MR22_Msk

#define EXTI_EMR_MR22_Msk   (0x1U << EXTI_EMR_MR22_Pos)

0x00400000

◆ EXTI_EMR_MR22_Pos

#define EXTI_EMR_MR22_Pos   (22U)

◆ EXTI_EMR_MR23

#define EXTI_EMR_MR23   EXTI_EMR_MR23_Msk

Event Mask on line 23

◆ EXTI_EMR_MR23_Msk

#define EXTI_EMR_MR23_Msk   (0x1U << EXTI_EMR_MR23_Pos)

0x00800000

◆ EXTI_EMR_MR23_Pos

#define EXTI_EMR_MR23_Pos   (23U)

◆ EXTI_EMR_MR2_Msk

#define EXTI_EMR_MR2_Msk   (0x1U << EXTI_EMR_MR2_Pos)

0x00000004

◆ EXTI_EMR_MR2_Pos

#define EXTI_EMR_MR2_Pos   (2U)

◆ EXTI_EMR_MR3

#define EXTI_EMR_MR3   EXTI_EMR_MR3_Msk

Event Mask on line 3

◆ EXTI_EMR_MR3_Msk

#define EXTI_EMR_MR3_Msk   (0x1U << EXTI_EMR_MR3_Pos)

0x00000008

◆ EXTI_EMR_MR3_Pos

#define EXTI_EMR_MR3_Pos   (3U)

◆ EXTI_EMR_MR4

#define EXTI_EMR_MR4   EXTI_EMR_MR4_Msk

Event Mask on line 4

◆ EXTI_EMR_MR4_Msk

#define EXTI_EMR_MR4_Msk   (0x1U << EXTI_EMR_MR4_Pos)

0x00000010

◆ EXTI_EMR_MR4_Pos

#define EXTI_EMR_MR4_Pos   (4U)

◆ EXTI_EMR_MR5

#define EXTI_EMR_MR5   EXTI_EMR_MR5_Msk

Event Mask on line 5

◆ EXTI_EMR_MR5_Msk

#define EXTI_EMR_MR5_Msk   (0x1U << EXTI_EMR_MR5_Pos)

0x00000020

◆ EXTI_EMR_MR5_Pos

#define EXTI_EMR_MR5_Pos   (5U)

◆ EXTI_EMR_MR6

#define EXTI_EMR_MR6   EXTI_EMR_MR6_Msk

Event Mask on line 6

◆ EXTI_EMR_MR6_Msk

#define EXTI_EMR_MR6_Msk   (0x1U << EXTI_EMR_MR6_Pos)

0x00000040

◆ EXTI_EMR_MR6_Pos

#define EXTI_EMR_MR6_Pos   (6U)

◆ EXTI_EMR_MR7

#define EXTI_EMR_MR7   EXTI_EMR_MR7_Msk

Event Mask on line 7

◆ EXTI_EMR_MR7_Msk

#define EXTI_EMR_MR7_Msk   (0x1U << EXTI_EMR_MR7_Pos)

0x00000080

◆ EXTI_EMR_MR7_Pos

#define EXTI_EMR_MR7_Pos   (7U)

◆ EXTI_EMR_MR8

#define EXTI_EMR_MR8   EXTI_EMR_MR8_Msk

Event Mask on line 8

◆ EXTI_EMR_MR8_Msk

#define EXTI_EMR_MR8_Msk   (0x1U << EXTI_EMR_MR8_Pos)

0x00000100

◆ EXTI_EMR_MR8_Pos

#define EXTI_EMR_MR8_Pos   (8U)

◆ EXTI_EMR_MR9

#define EXTI_EMR_MR9   EXTI_EMR_MR9_Msk

Event Mask on line 9

◆ EXTI_EMR_MR9_Msk

#define EXTI_EMR_MR9_Msk   (0x1U << EXTI_EMR_MR9_Pos)

0x00000200

◆ EXTI_EMR_MR9_Pos

#define EXTI_EMR_MR9_Pos   (9U)

◆ EXTI_FTSR_FT0

#define EXTI_FTSR_FT0   EXTI_FTSR_TR0

◆ EXTI_FTSR_FT1

#define EXTI_FTSR_FT1   EXTI_FTSR_TR1

◆ EXTI_FTSR_FT10

#define EXTI_FTSR_FT10   EXTI_FTSR_TR10

◆ EXTI_FTSR_FT11

#define EXTI_FTSR_FT11   EXTI_FTSR_TR11

◆ EXTI_FTSR_FT12

#define EXTI_FTSR_FT12   EXTI_FTSR_TR12

◆ EXTI_FTSR_FT13

#define EXTI_FTSR_FT13   EXTI_FTSR_TR13

◆ EXTI_FTSR_FT14

#define EXTI_FTSR_FT14   EXTI_FTSR_TR14

◆ EXTI_FTSR_FT15

#define EXTI_FTSR_FT15   EXTI_FTSR_TR15

◆ EXTI_FTSR_FT16

#define EXTI_FTSR_FT16   EXTI_FTSR_TR16

◆ EXTI_FTSR_FT17

#define EXTI_FTSR_FT17   EXTI_FTSR_TR17

◆ EXTI_FTSR_FT18

#define EXTI_FTSR_FT18   EXTI_FTSR_TR18

◆ EXTI_FTSR_FT19

#define EXTI_FTSR_FT19   EXTI_FTSR_TR19

◆ EXTI_FTSR_FT2

#define EXTI_FTSR_FT2   EXTI_FTSR_TR2

◆ EXTI_FTSR_FT20

#define EXTI_FTSR_FT20   EXTI_FTSR_TR20

◆ EXTI_FTSR_FT21

#define EXTI_FTSR_FT21   EXTI_FTSR_TR21

◆ EXTI_FTSR_FT22

#define EXTI_FTSR_FT22   EXTI_FTSR_TR22

◆ EXTI_FTSR_FT23

#define EXTI_FTSR_FT23   EXTI_FTSR_TR23

◆ EXTI_FTSR_FT3

#define EXTI_FTSR_FT3   EXTI_FTSR_TR3

◆ EXTI_FTSR_FT4

#define EXTI_FTSR_FT4   EXTI_FTSR_TR4

◆ EXTI_FTSR_FT5

#define EXTI_FTSR_FT5   EXTI_FTSR_TR5

◆ EXTI_FTSR_FT6

#define EXTI_FTSR_FT6   EXTI_FTSR_TR6

◆ EXTI_FTSR_FT7

#define EXTI_FTSR_FT7   EXTI_FTSR_TR7

◆ EXTI_FTSR_FT8

#define EXTI_FTSR_FT8   EXTI_FTSR_TR8

◆ EXTI_FTSR_FT9

#define EXTI_FTSR_FT9   EXTI_FTSR_TR9

◆ EXTI_FTSR_TR0

#define EXTI_FTSR_TR0   EXTI_FTSR_TR0_Msk

Falling trigger event configuration bit of line 0

◆ EXTI_FTSR_TR0_Msk

#define EXTI_FTSR_TR0_Msk   (0x1U << EXTI_FTSR_TR0_Pos)

0x00000001

◆ EXTI_FTSR_TR0_Pos

#define EXTI_FTSR_TR0_Pos   (0U)

◆ EXTI_FTSR_TR1

#define EXTI_FTSR_TR1   EXTI_FTSR_TR1_Msk

Falling trigger event configuration bit of line 1

◆ EXTI_FTSR_TR10

#define EXTI_FTSR_TR10   EXTI_FTSR_TR10_Msk

Falling trigger event configuration bit of line 10

◆ EXTI_FTSR_TR10_Msk

#define EXTI_FTSR_TR10_Msk   (0x1U << EXTI_FTSR_TR10_Pos)

0x00000400

◆ EXTI_FTSR_TR10_Pos

#define EXTI_FTSR_TR10_Pos   (10U)

◆ EXTI_FTSR_TR11

#define EXTI_FTSR_TR11   EXTI_FTSR_TR11_Msk

Falling trigger event configuration bit of line 11

◆ EXTI_FTSR_TR11_Msk

#define EXTI_FTSR_TR11_Msk   (0x1U << EXTI_FTSR_TR11_Pos)

0x00000800

◆ EXTI_FTSR_TR11_Pos

#define EXTI_FTSR_TR11_Pos   (11U)

◆ EXTI_FTSR_TR12

#define EXTI_FTSR_TR12   EXTI_FTSR_TR12_Msk

Falling trigger event configuration bit of line 12

◆ EXTI_FTSR_TR12_Msk

#define EXTI_FTSR_TR12_Msk   (0x1U << EXTI_FTSR_TR12_Pos)

0x00001000

◆ EXTI_FTSR_TR12_Pos

#define EXTI_FTSR_TR12_Pos   (12U)

◆ EXTI_FTSR_TR13

#define EXTI_FTSR_TR13   EXTI_FTSR_TR13_Msk

Falling trigger event configuration bit of line 13

◆ EXTI_FTSR_TR13_Msk

#define EXTI_FTSR_TR13_Msk   (0x1U << EXTI_FTSR_TR13_Pos)

0x00002000

◆ EXTI_FTSR_TR13_Pos

#define EXTI_FTSR_TR13_Pos   (13U)

◆ EXTI_FTSR_TR14

#define EXTI_FTSR_TR14   EXTI_FTSR_TR14_Msk

Falling trigger event configuration bit of line 14

◆ EXTI_FTSR_TR14_Msk

#define EXTI_FTSR_TR14_Msk   (0x1U << EXTI_FTSR_TR14_Pos)

0x00004000

◆ EXTI_FTSR_TR14_Pos

#define EXTI_FTSR_TR14_Pos   (14U)

◆ EXTI_FTSR_TR15

#define EXTI_FTSR_TR15   EXTI_FTSR_TR15_Msk

Falling trigger event configuration bit of line 15

◆ EXTI_FTSR_TR15_Msk

#define EXTI_FTSR_TR15_Msk   (0x1U << EXTI_FTSR_TR15_Pos)

0x00008000

◆ EXTI_FTSR_TR15_Pos

#define EXTI_FTSR_TR15_Pos   (15U)

◆ EXTI_FTSR_TR16

#define EXTI_FTSR_TR16   EXTI_FTSR_TR16_Msk

Falling trigger event configuration bit of line 16

◆ EXTI_FTSR_TR16_Msk

#define EXTI_FTSR_TR16_Msk   (0x1U << EXTI_FTSR_TR16_Pos)

0x00010000

◆ EXTI_FTSR_TR16_Pos

#define EXTI_FTSR_TR16_Pos   (16U)

◆ EXTI_FTSR_TR17

#define EXTI_FTSR_TR17   EXTI_FTSR_TR17_Msk

Falling trigger event configuration bit of line 17

◆ EXTI_FTSR_TR17_Msk

#define EXTI_FTSR_TR17_Msk   (0x1U << EXTI_FTSR_TR17_Pos)

0x00020000

◆ EXTI_FTSR_TR17_Pos

#define EXTI_FTSR_TR17_Pos   (17U)

◆ EXTI_FTSR_TR18

#define EXTI_FTSR_TR18   EXTI_FTSR_TR18_Msk

Falling trigger event configuration bit of line 18

◆ EXTI_FTSR_TR18_Msk

#define EXTI_FTSR_TR18_Msk   (0x1U << EXTI_FTSR_TR18_Pos)

0x00040000

◆ EXTI_FTSR_TR18_Pos

#define EXTI_FTSR_TR18_Pos   (18U)

◆ EXTI_FTSR_TR19

#define EXTI_FTSR_TR19   EXTI_FTSR_TR19_Msk

Falling trigger event configuration bit of line 19

◆ EXTI_FTSR_TR19_Msk

#define EXTI_FTSR_TR19_Msk   (0x1U << EXTI_FTSR_TR19_Pos)

0x00080000

◆ EXTI_FTSR_TR19_Pos

#define EXTI_FTSR_TR19_Pos   (19U)

◆ EXTI_FTSR_TR1_Msk

#define EXTI_FTSR_TR1_Msk   (0x1U << EXTI_FTSR_TR1_Pos)

0x00000002

◆ EXTI_FTSR_TR1_Pos

#define EXTI_FTSR_TR1_Pos   (1U)

◆ EXTI_FTSR_TR2

#define EXTI_FTSR_TR2   EXTI_FTSR_TR2_Msk

Falling trigger event configuration bit of line 2

◆ EXTI_FTSR_TR20

#define EXTI_FTSR_TR20   EXTI_FTSR_TR20_Msk

Falling trigger event configuration bit of line 20

◆ EXTI_FTSR_TR20_Msk

#define EXTI_FTSR_TR20_Msk   (0x1U << EXTI_FTSR_TR20_Pos)

0x00100000

◆ EXTI_FTSR_TR20_Pos

#define EXTI_FTSR_TR20_Pos   (20U)

◆ EXTI_FTSR_TR21

#define EXTI_FTSR_TR21   EXTI_FTSR_TR21_Msk

Falling trigger event configuration bit of line 21

◆ EXTI_FTSR_TR21_Msk

#define EXTI_FTSR_TR21_Msk   (0x1U << EXTI_FTSR_TR21_Pos)

0x00200000

◆ EXTI_FTSR_TR21_Pos

#define EXTI_FTSR_TR21_Pos   (21U)

◆ EXTI_FTSR_TR22

#define EXTI_FTSR_TR22   EXTI_FTSR_TR22_Msk

Falling trigger event configuration bit of line 22

◆ EXTI_FTSR_TR22_Msk

#define EXTI_FTSR_TR22_Msk   (0x1U << EXTI_FTSR_TR22_Pos)

0x00400000

◆ EXTI_FTSR_TR22_Pos

#define EXTI_FTSR_TR22_Pos   (22U)

◆ EXTI_FTSR_TR23

#define EXTI_FTSR_TR23   EXTI_FTSR_TR23_Msk

Falling trigger event configuration bit of line 23

◆ EXTI_FTSR_TR23_Msk

#define EXTI_FTSR_TR23_Msk   (0x1U << EXTI_FTSR_TR23_Pos)

0x00800000

◆ EXTI_FTSR_TR23_Pos

#define EXTI_FTSR_TR23_Pos   (23U)

◆ EXTI_FTSR_TR2_Msk

#define EXTI_FTSR_TR2_Msk   (0x1U << EXTI_FTSR_TR2_Pos)

0x00000004

◆ EXTI_FTSR_TR2_Pos

#define EXTI_FTSR_TR2_Pos   (2U)

◆ EXTI_FTSR_TR3

#define EXTI_FTSR_TR3   EXTI_FTSR_TR3_Msk

Falling trigger event configuration bit of line 3

◆ EXTI_FTSR_TR3_Msk

#define EXTI_FTSR_TR3_Msk   (0x1U << EXTI_FTSR_TR3_Pos)

0x00000008

◆ EXTI_FTSR_TR3_Pos

#define EXTI_FTSR_TR3_Pos   (3U)

◆ EXTI_FTSR_TR4

#define EXTI_FTSR_TR4   EXTI_FTSR_TR4_Msk

Falling trigger event configuration bit of line 4

◆ EXTI_FTSR_TR4_Msk

#define EXTI_FTSR_TR4_Msk   (0x1U << EXTI_FTSR_TR4_Pos)

0x00000010

◆ EXTI_FTSR_TR4_Pos

#define EXTI_FTSR_TR4_Pos   (4U)

◆ EXTI_FTSR_TR5

#define EXTI_FTSR_TR5   EXTI_FTSR_TR5_Msk

Falling trigger event configuration bit of line 5

◆ EXTI_FTSR_TR5_Msk

#define EXTI_FTSR_TR5_Msk   (0x1U << EXTI_FTSR_TR5_Pos)

0x00000020

◆ EXTI_FTSR_TR5_Pos

#define EXTI_FTSR_TR5_Pos   (5U)

◆ EXTI_FTSR_TR6

#define EXTI_FTSR_TR6   EXTI_FTSR_TR6_Msk

Falling trigger event configuration bit of line 6

◆ EXTI_FTSR_TR6_Msk

#define EXTI_FTSR_TR6_Msk   (0x1U << EXTI_FTSR_TR6_Pos)

0x00000040

◆ EXTI_FTSR_TR6_Pos

#define EXTI_FTSR_TR6_Pos   (6U)

◆ EXTI_FTSR_TR7

#define EXTI_FTSR_TR7   EXTI_FTSR_TR7_Msk

Falling trigger event configuration bit of line 7

◆ EXTI_FTSR_TR7_Msk

#define EXTI_FTSR_TR7_Msk   (0x1U << EXTI_FTSR_TR7_Pos)

0x00000080

◆ EXTI_FTSR_TR7_Pos

#define EXTI_FTSR_TR7_Pos   (7U)

◆ EXTI_FTSR_TR8

#define EXTI_FTSR_TR8   EXTI_FTSR_TR8_Msk

Falling trigger event configuration bit of line 8

◆ EXTI_FTSR_TR8_Msk

#define EXTI_FTSR_TR8_Msk   (0x1U << EXTI_FTSR_TR8_Pos)

0x00000100

◆ EXTI_FTSR_TR8_Pos

#define EXTI_FTSR_TR8_Pos   (8U)

◆ EXTI_FTSR_TR9

#define EXTI_FTSR_TR9   EXTI_FTSR_TR9_Msk

Falling trigger event configuration bit of line 9

◆ EXTI_FTSR_TR9_Msk

#define EXTI_FTSR_TR9_Msk   (0x1U << EXTI_FTSR_TR9_Pos)

0x00000200

◆ EXTI_FTSR_TR9_Pos

#define EXTI_FTSR_TR9_Pos   (9U)

◆ EXTI_IMR_IM

#define EXTI_IMR_IM   EXTI_IMR_IM_Msk

Interrupt Mask All

◆ EXTI_IMR_IM0

#define EXTI_IMR_IM0   EXTI_IMR_MR0

◆ EXTI_IMR_IM1

#define EXTI_IMR_IM1   EXTI_IMR_MR1

◆ EXTI_IMR_IM10

#define EXTI_IMR_IM10   EXTI_IMR_MR10

◆ EXTI_IMR_IM11

#define EXTI_IMR_IM11   EXTI_IMR_MR11

◆ EXTI_IMR_IM12

#define EXTI_IMR_IM12   EXTI_IMR_MR12

◆ EXTI_IMR_IM13

#define EXTI_IMR_IM13   EXTI_IMR_MR13

◆ EXTI_IMR_IM14

#define EXTI_IMR_IM14   EXTI_IMR_MR14

◆ EXTI_IMR_IM15

#define EXTI_IMR_IM15   EXTI_IMR_MR15

◆ EXTI_IMR_IM16

#define EXTI_IMR_IM16   EXTI_IMR_MR16

◆ EXTI_IMR_IM17

#define EXTI_IMR_IM17   EXTI_IMR_MR17

◆ EXTI_IMR_IM18

#define EXTI_IMR_IM18   EXTI_IMR_MR18

◆ EXTI_IMR_IM19

#define EXTI_IMR_IM19   EXTI_IMR_MR19

◆ EXTI_IMR_IM2

#define EXTI_IMR_IM2   EXTI_IMR_MR2

◆ EXTI_IMR_IM20

#define EXTI_IMR_IM20   EXTI_IMR_MR20

◆ EXTI_IMR_IM21

#define EXTI_IMR_IM21   EXTI_IMR_MR21

◆ EXTI_IMR_IM22

#define EXTI_IMR_IM22   EXTI_IMR_MR22

◆ EXTI_IMR_IM23

#define EXTI_IMR_IM23   EXTI_IMR_MR23

◆ EXTI_IMR_IM3

#define EXTI_IMR_IM3   EXTI_IMR_MR3

◆ EXTI_IMR_IM4

#define EXTI_IMR_IM4   EXTI_IMR_MR4

◆ EXTI_IMR_IM5

#define EXTI_IMR_IM5   EXTI_IMR_MR5

◆ EXTI_IMR_IM6

#define EXTI_IMR_IM6   EXTI_IMR_MR6

◆ EXTI_IMR_IM7

#define EXTI_IMR_IM7   EXTI_IMR_MR7

◆ EXTI_IMR_IM8

#define EXTI_IMR_IM8   EXTI_IMR_MR8

◆ EXTI_IMR_IM9

#define EXTI_IMR_IM9   EXTI_IMR_MR9

◆ EXTI_IMR_IM_Msk

#define EXTI_IMR_IM_Msk   (0xFFFFFFU << EXTI_IMR_IM_Pos)

0x00FFFFFF

◆ EXTI_IMR_IM_Pos

#define EXTI_IMR_IM_Pos   (0U)

◆ EXTI_IMR_MR0

#define EXTI_IMR_MR0   EXTI_IMR_MR0_Msk

Interrupt Mask on line 0

◆ EXTI_IMR_MR0_Msk

#define EXTI_IMR_MR0_Msk   (0x1U << EXTI_IMR_MR0_Pos)

0x00000001

◆ EXTI_IMR_MR0_Pos

#define EXTI_IMR_MR0_Pos   (0U)

◆ EXTI_IMR_MR1

#define EXTI_IMR_MR1   EXTI_IMR_MR1_Msk

Interrupt Mask on line 1

◆ EXTI_IMR_MR10

#define EXTI_IMR_MR10   EXTI_IMR_MR10_Msk

Interrupt Mask on line 10

◆ EXTI_IMR_MR10_Msk

#define EXTI_IMR_MR10_Msk   (0x1U << EXTI_IMR_MR10_Pos)

0x00000400

◆ EXTI_IMR_MR10_Pos

#define EXTI_IMR_MR10_Pos   (10U)

◆ EXTI_IMR_MR11

#define EXTI_IMR_MR11   EXTI_IMR_MR11_Msk

Interrupt Mask on line 11

◆ EXTI_IMR_MR11_Msk

#define EXTI_IMR_MR11_Msk   (0x1U << EXTI_IMR_MR11_Pos)

0x00000800

◆ EXTI_IMR_MR11_Pos

#define EXTI_IMR_MR11_Pos   (11U)

◆ EXTI_IMR_MR12

#define EXTI_IMR_MR12   EXTI_IMR_MR12_Msk

Interrupt Mask on line 12

◆ EXTI_IMR_MR12_Msk

#define EXTI_IMR_MR12_Msk   (0x1U << EXTI_IMR_MR12_Pos)

0x00001000

◆ EXTI_IMR_MR12_Pos

#define EXTI_IMR_MR12_Pos   (12U)

◆ EXTI_IMR_MR13

#define EXTI_IMR_MR13   EXTI_IMR_MR13_Msk

Interrupt Mask on line 13

◆ EXTI_IMR_MR13_Msk

#define EXTI_IMR_MR13_Msk   (0x1U << EXTI_IMR_MR13_Pos)

0x00002000

◆ EXTI_IMR_MR13_Pos

#define EXTI_IMR_MR13_Pos   (13U)

◆ EXTI_IMR_MR14

#define EXTI_IMR_MR14   EXTI_IMR_MR14_Msk

Interrupt Mask on line 14

◆ EXTI_IMR_MR14_Msk

#define EXTI_IMR_MR14_Msk   (0x1U << EXTI_IMR_MR14_Pos)

0x00004000

◆ EXTI_IMR_MR14_Pos

#define EXTI_IMR_MR14_Pos   (14U)

◆ EXTI_IMR_MR15

#define EXTI_IMR_MR15   EXTI_IMR_MR15_Msk

Interrupt Mask on line 15

◆ EXTI_IMR_MR15_Msk

#define EXTI_IMR_MR15_Msk   (0x1U << EXTI_IMR_MR15_Pos)

0x00008000

◆ EXTI_IMR_MR15_Pos

#define EXTI_IMR_MR15_Pos   (15U)

◆ EXTI_IMR_MR16

#define EXTI_IMR_MR16   EXTI_IMR_MR16_Msk

Interrupt Mask on line 16

◆ EXTI_IMR_MR16_Msk

#define EXTI_IMR_MR16_Msk   (0x1U << EXTI_IMR_MR16_Pos)

0x00010000

◆ EXTI_IMR_MR16_Pos

#define EXTI_IMR_MR16_Pos   (16U)

◆ EXTI_IMR_MR17

#define EXTI_IMR_MR17   EXTI_IMR_MR17_Msk

Interrupt Mask on line 17

◆ EXTI_IMR_MR17_Msk

#define EXTI_IMR_MR17_Msk   (0x1U << EXTI_IMR_MR17_Pos)

0x00020000

◆ EXTI_IMR_MR17_Pos

#define EXTI_IMR_MR17_Pos   (17U)

◆ EXTI_IMR_MR18

#define EXTI_IMR_MR18   EXTI_IMR_MR18_Msk

Interrupt Mask on line 18

◆ EXTI_IMR_MR18_Msk

#define EXTI_IMR_MR18_Msk   (0x1U << EXTI_IMR_MR18_Pos)

0x00040000

◆ EXTI_IMR_MR18_Pos

#define EXTI_IMR_MR18_Pos   (18U)

◆ EXTI_IMR_MR19

#define EXTI_IMR_MR19   EXTI_IMR_MR19_Msk

Interrupt Mask on line 19

◆ EXTI_IMR_MR19_Msk

#define EXTI_IMR_MR19_Msk   (0x1U << EXTI_IMR_MR19_Pos)

0x00080000

◆ EXTI_IMR_MR19_Pos

#define EXTI_IMR_MR19_Pos   (19U)

◆ EXTI_IMR_MR1_Msk

#define EXTI_IMR_MR1_Msk   (0x1U << EXTI_IMR_MR1_Pos)

0x00000002

◆ EXTI_IMR_MR1_Pos

#define EXTI_IMR_MR1_Pos   (1U)

◆ EXTI_IMR_MR2

#define EXTI_IMR_MR2   EXTI_IMR_MR2_Msk

Interrupt Mask on line 2

◆ EXTI_IMR_MR20

#define EXTI_IMR_MR20   EXTI_IMR_MR20_Msk

Interrupt Mask on line 20

◆ EXTI_IMR_MR20_Msk

#define EXTI_IMR_MR20_Msk   (0x1U << EXTI_IMR_MR20_Pos)

0x00100000

◆ EXTI_IMR_MR20_Pos

#define EXTI_IMR_MR20_Pos   (20U)

◆ EXTI_IMR_MR21

#define EXTI_IMR_MR21   EXTI_IMR_MR21_Msk

Interrupt Mask on line 21

◆ EXTI_IMR_MR21_Msk

#define EXTI_IMR_MR21_Msk   (0x1U << EXTI_IMR_MR21_Pos)

0x00200000

◆ EXTI_IMR_MR21_Pos

#define EXTI_IMR_MR21_Pos   (21U)

◆ EXTI_IMR_MR22

#define EXTI_IMR_MR22   EXTI_IMR_MR22_Msk

Interrupt Mask on line 22

◆ EXTI_IMR_MR22_Msk

#define EXTI_IMR_MR22_Msk   (0x1U << EXTI_IMR_MR22_Pos)

0x00400000

◆ EXTI_IMR_MR22_Pos

#define EXTI_IMR_MR22_Pos   (22U)

◆ EXTI_IMR_MR23

#define EXTI_IMR_MR23   EXTI_IMR_MR23_Msk

Interrupt Mask on line 23

◆ EXTI_IMR_MR23_Msk

#define EXTI_IMR_MR23_Msk   (0x1U << EXTI_IMR_MR23_Pos)

0x00800000

◆ EXTI_IMR_MR23_Pos

#define EXTI_IMR_MR23_Pos   (23U)

◆ EXTI_IMR_MR2_Msk

#define EXTI_IMR_MR2_Msk   (0x1U << EXTI_IMR_MR2_Pos)

0x00000004

◆ EXTI_IMR_MR2_Pos

#define EXTI_IMR_MR2_Pos   (2U)

◆ EXTI_IMR_MR3

#define EXTI_IMR_MR3   EXTI_IMR_MR3_Msk

Interrupt Mask on line 3

◆ EXTI_IMR_MR3_Msk

#define EXTI_IMR_MR3_Msk   (0x1U << EXTI_IMR_MR3_Pos)

0x00000008

◆ EXTI_IMR_MR3_Pos

#define EXTI_IMR_MR3_Pos   (3U)

◆ EXTI_IMR_MR4

#define EXTI_IMR_MR4   EXTI_IMR_MR4_Msk

Interrupt Mask on line 4

◆ EXTI_IMR_MR4_Msk

#define EXTI_IMR_MR4_Msk   (0x1U << EXTI_IMR_MR4_Pos)

0x00000010

◆ EXTI_IMR_MR4_Pos

#define EXTI_IMR_MR4_Pos   (4U)

◆ EXTI_IMR_MR5

#define EXTI_IMR_MR5   EXTI_IMR_MR5_Msk

Interrupt Mask on line 5

◆ EXTI_IMR_MR5_Msk

#define EXTI_IMR_MR5_Msk   (0x1U << EXTI_IMR_MR5_Pos)

0x00000020

◆ EXTI_IMR_MR5_Pos

#define EXTI_IMR_MR5_Pos   (5U)

◆ EXTI_IMR_MR6

#define EXTI_IMR_MR6   EXTI_IMR_MR6_Msk

Interrupt Mask on line 6

◆ EXTI_IMR_MR6_Msk

#define EXTI_IMR_MR6_Msk   (0x1U << EXTI_IMR_MR6_Pos)

0x00000040

◆ EXTI_IMR_MR6_Pos

#define EXTI_IMR_MR6_Pos   (6U)

◆ EXTI_IMR_MR7

#define EXTI_IMR_MR7   EXTI_IMR_MR7_Msk

Interrupt Mask on line 7

◆ EXTI_IMR_MR7_Msk

#define EXTI_IMR_MR7_Msk   (0x1U << EXTI_IMR_MR7_Pos)

0x00000080

◆ EXTI_IMR_MR7_Pos

#define EXTI_IMR_MR7_Pos   (7U)

◆ EXTI_IMR_MR8

#define EXTI_IMR_MR8   EXTI_IMR_MR8_Msk

Interrupt Mask on line 8

◆ EXTI_IMR_MR8_Msk

#define EXTI_IMR_MR8_Msk   (0x1U << EXTI_IMR_MR8_Pos)

0x00000100

◆ EXTI_IMR_MR8_Pos

#define EXTI_IMR_MR8_Pos   (8U)

◆ EXTI_IMR_MR9

#define EXTI_IMR_MR9   EXTI_IMR_MR9_Msk

Interrupt Mask on line 9

◆ EXTI_IMR_MR9_Msk

#define EXTI_IMR_MR9_Msk   (0x1U << EXTI_IMR_MR9_Pos)

0x00000200

◆ EXTI_IMR_MR9_Pos

#define EXTI_IMR_MR9_Pos   (9U)

◆ EXTI_PR_PIF0

#define EXTI_PR_PIF0   EXTI_PR_PR0

◆ EXTI_PR_PIF1

#define EXTI_PR_PIF1   EXTI_PR_PR1

◆ EXTI_PR_PIF10

#define EXTI_PR_PIF10   EXTI_PR_PR10

◆ EXTI_PR_PIF11

#define EXTI_PR_PIF11   EXTI_PR_PR11

◆ EXTI_PR_PIF12

#define EXTI_PR_PIF12   EXTI_PR_PR12

◆ EXTI_PR_PIF13

#define EXTI_PR_PIF13   EXTI_PR_PR13

◆ EXTI_PR_PIF14

#define EXTI_PR_PIF14   EXTI_PR_PR14

◆ EXTI_PR_PIF15

#define EXTI_PR_PIF15   EXTI_PR_PR15

◆ EXTI_PR_PIF16

#define EXTI_PR_PIF16   EXTI_PR_PR16

◆ EXTI_PR_PIF17

#define EXTI_PR_PIF17   EXTI_PR_PR17

◆ EXTI_PR_PIF18

#define EXTI_PR_PIF18   EXTI_PR_PR18

◆ EXTI_PR_PIF19

#define EXTI_PR_PIF19   EXTI_PR_PR19

◆ EXTI_PR_PIF2

#define EXTI_PR_PIF2   EXTI_PR_PR2

◆ EXTI_PR_PIF20

#define EXTI_PR_PIF20   EXTI_PR_PR20

◆ EXTI_PR_PIF21

#define EXTI_PR_PIF21   EXTI_PR_PR21

◆ EXTI_PR_PIF22

#define EXTI_PR_PIF22   EXTI_PR_PR22

◆ EXTI_PR_PIF23

#define EXTI_PR_PIF23   EXTI_PR_PR23

◆ EXTI_PR_PIF3

#define EXTI_PR_PIF3   EXTI_PR_PR3

◆ EXTI_PR_PIF4

#define EXTI_PR_PIF4   EXTI_PR_PR4

◆ EXTI_PR_PIF5

#define EXTI_PR_PIF5   EXTI_PR_PR5

◆ EXTI_PR_PIF6

#define EXTI_PR_PIF6   EXTI_PR_PR6

◆ EXTI_PR_PIF7

#define EXTI_PR_PIF7   EXTI_PR_PR7

◆ EXTI_PR_PIF8

#define EXTI_PR_PIF8   EXTI_PR_PR8

◆ EXTI_PR_PIF9

#define EXTI_PR_PIF9   EXTI_PR_PR9

◆ EXTI_PR_PR0

#define EXTI_PR_PR0   EXTI_PR_PR0_Msk

Pending bit for line 0

◆ EXTI_PR_PR0_Msk

#define EXTI_PR_PR0_Msk   (0x1U << EXTI_PR_PR0_Pos)

0x00000001

◆ EXTI_PR_PR0_Pos

#define EXTI_PR_PR0_Pos   (0U)

◆ EXTI_PR_PR1

#define EXTI_PR_PR1   EXTI_PR_PR1_Msk

Pending bit for line 1

◆ EXTI_PR_PR10

#define EXTI_PR_PR10   EXTI_PR_PR10_Msk

Pending bit for line 10

◆ EXTI_PR_PR10_Msk

#define EXTI_PR_PR10_Msk   (0x1U << EXTI_PR_PR10_Pos)

0x00000400

◆ EXTI_PR_PR10_Pos

#define EXTI_PR_PR10_Pos   (10U)

◆ EXTI_PR_PR11

#define EXTI_PR_PR11   EXTI_PR_PR11_Msk

Pending bit for line 11

◆ EXTI_PR_PR11_Msk

#define EXTI_PR_PR11_Msk   (0x1U << EXTI_PR_PR11_Pos)

0x00000800

◆ EXTI_PR_PR11_Pos

#define EXTI_PR_PR11_Pos   (11U)

◆ EXTI_PR_PR12

#define EXTI_PR_PR12   EXTI_PR_PR12_Msk

Pending bit for line 12

◆ EXTI_PR_PR12_Msk

#define EXTI_PR_PR12_Msk   (0x1U << EXTI_PR_PR12_Pos)

0x00001000

◆ EXTI_PR_PR12_Pos

#define EXTI_PR_PR12_Pos   (12U)

◆ EXTI_PR_PR13

#define EXTI_PR_PR13   EXTI_PR_PR13_Msk

Pending bit for line 13

◆ EXTI_PR_PR13_Msk

#define EXTI_PR_PR13_Msk   (0x1U << EXTI_PR_PR13_Pos)

0x00002000

◆ EXTI_PR_PR13_Pos

#define EXTI_PR_PR13_Pos   (13U)

◆ EXTI_PR_PR14

#define EXTI_PR_PR14   EXTI_PR_PR14_Msk

Pending bit for line 14

◆ EXTI_PR_PR14_Msk

#define EXTI_PR_PR14_Msk   (0x1U << EXTI_PR_PR14_Pos)

0x00004000

◆ EXTI_PR_PR14_Pos

#define EXTI_PR_PR14_Pos   (14U)

◆ EXTI_PR_PR15

#define EXTI_PR_PR15   EXTI_PR_PR15_Msk

Pending bit for line 15

◆ EXTI_PR_PR15_Msk

#define EXTI_PR_PR15_Msk   (0x1U << EXTI_PR_PR15_Pos)

0x00008000

◆ EXTI_PR_PR15_Pos

#define EXTI_PR_PR15_Pos   (15U)

◆ EXTI_PR_PR16

#define EXTI_PR_PR16   EXTI_PR_PR16_Msk

Pending bit for line 16

◆ EXTI_PR_PR16_Msk

#define EXTI_PR_PR16_Msk   (0x1U << EXTI_PR_PR16_Pos)

0x00010000

◆ EXTI_PR_PR16_Pos

#define EXTI_PR_PR16_Pos   (16U)

◆ EXTI_PR_PR17

#define EXTI_PR_PR17   EXTI_PR_PR17_Msk

Pending bit for line 17

◆ EXTI_PR_PR17_Msk

#define EXTI_PR_PR17_Msk   (0x1U << EXTI_PR_PR17_Pos)

0x00020000

◆ EXTI_PR_PR17_Pos

#define EXTI_PR_PR17_Pos   (17U)

◆ EXTI_PR_PR18

#define EXTI_PR_PR18   EXTI_PR_PR18_Msk

Pending bit for line 18

◆ EXTI_PR_PR18_Msk

#define EXTI_PR_PR18_Msk   (0x1U << EXTI_PR_PR18_Pos)

0x00040000

◆ EXTI_PR_PR18_Pos

#define EXTI_PR_PR18_Pos   (18U)

◆ EXTI_PR_PR19

#define EXTI_PR_PR19   EXTI_PR_PR19_Msk

Pending bit for line 19

◆ EXTI_PR_PR19_Msk

#define EXTI_PR_PR19_Msk   (0x1U << EXTI_PR_PR19_Pos)

0x00080000

◆ EXTI_PR_PR19_Pos

#define EXTI_PR_PR19_Pos   (19U)

◆ EXTI_PR_PR1_Msk

#define EXTI_PR_PR1_Msk   (0x1U << EXTI_PR_PR1_Pos)

0x00000002

◆ EXTI_PR_PR1_Pos

#define EXTI_PR_PR1_Pos   (1U)

◆ EXTI_PR_PR2

#define EXTI_PR_PR2   EXTI_PR_PR2_Msk

Pending bit for line 2

◆ EXTI_PR_PR20

#define EXTI_PR_PR20   EXTI_PR_PR20_Msk

Pending bit for line 20

◆ EXTI_PR_PR20_Msk

#define EXTI_PR_PR20_Msk   (0x1U << EXTI_PR_PR20_Pos)

0x00100000

◆ EXTI_PR_PR20_Pos

#define EXTI_PR_PR20_Pos   (20U)

◆ EXTI_PR_PR21

#define EXTI_PR_PR21   EXTI_PR_PR21_Msk

Pending bit for line 21

◆ EXTI_PR_PR21_Msk

#define EXTI_PR_PR21_Msk   (0x1U << EXTI_PR_PR21_Pos)

0x00200000

◆ EXTI_PR_PR21_Pos

#define EXTI_PR_PR21_Pos   (21U)

◆ EXTI_PR_PR22

#define EXTI_PR_PR22   EXTI_PR_PR22_Msk

Pending bit for line 22

◆ EXTI_PR_PR22_Msk

#define EXTI_PR_PR22_Msk   (0x1U << EXTI_PR_PR22_Pos)

0x00400000

◆ EXTI_PR_PR22_Pos

#define EXTI_PR_PR22_Pos   (22U)

◆ EXTI_PR_PR23

#define EXTI_PR_PR23   EXTI_PR_PR23_Msk

Pending bit for line 23

◆ EXTI_PR_PR23_Msk

#define EXTI_PR_PR23_Msk   (0x1U << EXTI_PR_PR23_Pos)

0x00800000

◆ EXTI_PR_PR23_Pos

#define EXTI_PR_PR23_Pos   (23U)

◆ EXTI_PR_PR2_Msk

#define EXTI_PR_PR2_Msk   (0x1U << EXTI_PR_PR2_Pos)

0x00000004

◆ EXTI_PR_PR2_Pos

#define EXTI_PR_PR2_Pos   (2U)

◆ EXTI_PR_PR3

#define EXTI_PR_PR3   EXTI_PR_PR3_Msk

Pending bit for line 3

◆ EXTI_PR_PR3_Msk

#define EXTI_PR_PR3_Msk   (0x1U << EXTI_PR_PR3_Pos)

0x00000008

◆ EXTI_PR_PR3_Pos

#define EXTI_PR_PR3_Pos   (3U)

◆ EXTI_PR_PR4

#define EXTI_PR_PR4   EXTI_PR_PR4_Msk

Pending bit for line 4

◆ EXTI_PR_PR4_Msk

#define EXTI_PR_PR4_Msk   (0x1U << EXTI_PR_PR4_Pos)

0x00000010

◆ EXTI_PR_PR4_Pos

#define EXTI_PR_PR4_Pos   (4U)

◆ EXTI_PR_PR5

#define EXTI_PR_PR5   EXTI_PR_PR5_Msk

Pending bit for line 5

◆ EXTI_PR_PR5_Msk

#define EXTI_PR_PR5_Msk   (0x1U << EXTI_PR_PR5_Pos)

0x00000020

◆ EXTI_PR_PR5_Pos

#define EXTI_PR_PR5_Pos   (5U)

◆ EXTI_PR_PR6

#define EXTI_PR_PR6   EXTI_PR_PR6_Msk

Pending bit for line 6

◆ EXTI_PR_PR6_Msk

#define EXTI_PR_PR6_Msk   (0x1U << EXTI_PR_PR6_Pos)

0x00000040

◆ EXTI_PR_PR6_Pos

#define EXTI_PR_PR6_Pos   (6U)

◆ EXTI_PR_PR7

#define EXTI_PR_PR7   EXTI_PR_PR7_Msk

Pending bit for line 7

◆ EXTI_PR_PR7_Msk

#define EXTI_PR_PR7_Msk   (0x1U << EXTI_PR_PR7_Pos)

0x00000080

◆ EXTI_PR_PR7_Pos

#define EXTI_PR_PR7_Pos   (7U)

◆ EXTI_PR_PR8

#define EXTI_PR_PR8   EXTI_PR_PR8_Msk

Pending bit for line 8

◆ EXTI_PR_PR8_Msk

#define EXTI_PR_PR8_Msk   (0x1U << EXTI_PR_PR8_Pos)

0x00000100

◆ EXTI_PR_PR8_Pos

#define EXTI_PR_PR8_Pos   (8U)

◆ EXTI_PR_PR9

#define EXTI_PR_PR9   EXTI_PR_PR9_Msk

Pending bit for line 9

◆ EXTI_PR_PR9_Msk

#define EXTI_PR_PR9_Msk   (0x1U << EXTI_PR_PR9_Pos)

0x00000200

◆ EXTI_PR_PR9_Pos

#define EXTI_PR_PR9_Pos   (9U)

◆ EXTI_RTSR_RT0

#define EXTI_RTSR_RT0   EXTI_RTSR_TR0

◆ EXTI_RTSR_RT1

#define EXTI_RTSR_RT1   EXTI_RTSR_TR1

◆ EXTI_RTSR_RT10

#define EXTI_RTSR_RT10   EXTI_RTSR_TR10

◆ EXTI_RTSR_RT11

#define EXTI_RTSR_RT11   EXTI_RTSR_TR11

◆ EXTI_RTSR_RT12

#define EXTI_RTSR_RT12   EXTI_RTSR_TR12

◆ EXTI_RTSR_RT13

#define EXTI_RTSR_RT13   EXTI_RTSR_TR13

◆ EXTI_RTSR_RT14

#define EXTI_RTSR_RT14   EXTI_RTSR_TR14

◆ EXTI_RTSR_RT15

#define EXTI_RTSR_RT15   EXTI_RTSR_TR15

◆ EXTI_RTSR_RT16

#define EXTI_RTSR_RT16   EXTI_RTSR_TR16

◆ EXTI_RTSR_RT17

#define EXTI_RTSR_RT17   EXTI_RTSR_TR17

◆ EXTI_RTSR_RT18

#define EXTI_RTSR_RT18   EXTI_RTSR_TR18

◆ EXTI_RTSR_RT19

#define EXTI_RTSR_RT19   EXTI_RTSR_TR19

◆ EXTI_RTSR_RT2

#define EXTI_RTSR_RT2   EXTI_RTSR_TR2

◆ EXTI_RTSR_RT20

#define EXTI_RTSR_RT20   EXTI_RTSR_TR20

◆ EXTI_RTSR_RT21

#define EXTI_RTSR_RT21   EXTI_RTSR_TR21

◆ EXTI_RTSR_RT22

#define EXTI_RTSR_RT22   EXTI_RTSR_TR22

◆ EXTI_RTSR_RT23

#define EXTI_RTSR_RT23   EXTI_RTSR_TR23

◆ EXTI_RTSR_RT3

#define EXTI_RTSR_RT3   EXTI_RTSR_TR3

◆ EXTI_RTSR_RT4

#define EXTI_RTSR_RT4   EXTI_RTSR_TR4

◆ EXTI_RTSR_RT5

#define EXTI_RTSR_RT5   EXTI_RTSR_TR5

◆ EXTI_RTSR_RT6

#define EXTI_RTSR_RT6   EXTI_RTSR_TR6

◆ EXTI_RTSR_RT7

#define EXTI_RTSR_RT7   EXTI_RTSR_TR7

◆ EXTI_RTSR_RT8

#define EXTI_RTSR_RT8   EXTI_RTSR_TR8

◆ EXTI_RTSR_RT9

#define EXTI_RTSR_RT9   EXTI_RTSR_TR9

◆ EXTI_RTSR_TR0

#define EXTI_RTSR_TR0   EXTI_RTSR_TR0_Msk

Rising trigger event configuration bit of line 0

◆ EXTI_RTSR_TR0_Msk

#define EXTI_RTSR_TR0_Msk   (0x1U << EXTI_RTSR_TR0_Pos)

0x00000001

◆ EXTI_RTSR_TR0_Pos

#define EXTI_RTSR_TR0_Pos   (0U)

◆ EXTI_RTSR_TR1

#define EXTI_RTSR_TR1   EXTI_RTSR_TR1_Msk

Rising trigger event configuration bit of line 1

◆ EXTI_RTSR_TR10

#define EXTI_RTSR_TR10   EXTI_RTSR_TR10_Msk

Rising trigger event configuration bit of line 10

◆ EXTI_RTSR_TR10_Msk

#define EXTI_RTSR_TR10_Msk   (0x1U << EXTI_RTSR_TR10_Pos)

0x00000400

◆ EXTI_RTSR_TR10_Pos

#define EXTI_RTSR_TR10_Pos   (10U)

◆ EXTI_RTSR_TR11

#define EXTI_RTSR_TR11   EXTI_RTSR_TR11_Msk

Rising trigger event configuration bit of line 11

◆ EXTI_RTSR_TR11_Msk

#define EXTI_RTSR_TR11_Msk   (0x1U << EXTI_RTSR_TR11_Pos)

0x00000800

◆ EXTI_RTSR_TR11_Pos

#define EXTI_RTSR_TR11_Pos   (11U)

◆ EXTI_RTSR_TR12

#define EXTI_RTSR_TR12   EXTI_RTSR_TR12_Msk

Rising trigger event configuration bit of line 12

◆ EXTI_RTSR_TR12_Msk

#define EXTI_RTSR_TR12_Msk   (0x1U << EXTI_RTSR_TR12_Pos)

0x00001000

◆ EXTI_RTSR_TR12_Pos

#define EXTI_RTSR_TR12_Pos   (12U)

◆ EXTI_RTSR_TR13

#define EXTI_RTSR_TR13   EXTI_RTSR_TR13_Msk

Rising trigger event configuration bit of line 13

◆ EXTI_RTSR_TR13_Msk

#define EXTI_RTSR_TR13_Msk   (0x1U << EXTI_RTSR_TR13_Pos)

0x00002000

◆ EXTI_RTSR_TR13_Pos

#define EXTI_RTSR_TR13_Pos   (13U)

◆ EXTI_RTSR_TR14

#define EXTI_RTSR_TR14   EXTI_RTSR_TR14_Msk

Rising trigger event configuration bit of line 14

◆ EXTI_RTSR_TR14_Msk

#define EXTI_RTSR_TR14_Msk   (0x1U << EXTI_RTSR_TR14_Pos)

0x00004000

◆ EXTI_RTSR_TR14_Pos

#define EXTI_RTSR_TR14_Pos   (14U)

◆ EXTI_RTSR_TR15

#define EXTI_RTSR_TR15   EXTI_RTSR_TR15_Msk

Rising trigger event configuration bit of line 15

◆ EXTI_RTSR_TR15_Msk

#define EXTI_RTSR_TR15_Msk   (0x1U << EXTI_RTSR_TR15_Pos)

0x00008000

◆ EXTI_RTSR_TR15_Pos

#define EXTI_RTSR_TR15_Pos   (15U)

◆ EXTI_RTSR_TR16

#define EXTI_RTSR_TR16   EXTI_RTSR_TR16_Msk

Rising trigger event configuration bit of line 16

◆ EXTI_RTSR_TR16_Msk

#define EXTI_RTSR_TR16_Msk   (0x1U << EXTI_RTSR_TR16_Pos)

0x00010000

◆ EXTI_RTSR_TR16_Pos

#define EXTI_RTSR_TR16_Pos   (16U)

◆ EXTI_RTSR_TR17

#define EXTI_RTSR_TR17   EXTI_RTSR_TR17_Msk

Rising trigger event configuration bit of line 17

◆ EXTI_RTSR_TR17_Msk

#define EXTI_RTSR_TR17_Msk   (0x1U << EXTI_RTSR_TR17_Pos)

0x00020000

◆ EXTI_RTSR_TR17_Pos

#define EXTI_RTSR_TR17_Pos   (17U)

◆ EXTI_RTSR_TR18

#define EXTI_RTSR_TR18   EXTI_RTSR_TR18_Msk

Rising trigger event configuration bit of line 18

◆ EXTI_RTSR_TR18_Msk

#define EXTI_RTSR_TR18_Msk   (0x1U << EXTI_RTSR_TR18_Pos)

0x00040000

◆ EXTI_RTSR_TR18_Pos

#define EXTI_RTSR_TR18_Pos   (18U)

◆ EXTI_RTSR_TR19

#define EXTI_RTSR_TR19   EXTI_RTSR_TR19_Msk

Rising trigger event configuration bit of line 19

◆ EXTI_RTSR_TR19_Msk

#define EXTI_RTSR_TR19_Msk   (0x1U << EXTI_RTSR_TR19_Pos)

0x00080000

◆ EXTI_RTSR_TR19_Pos

#define EXTI_RTSR_TR19_Pos   (19U)

◆ EXTI_RTSR_TR1_Msk

#define EXTI_RTSR_TR1_Msk   (0x1U << EXTI_RTSR_TR1_Pos)

0x00000002

◆ EXTI_RTSR_TR1_Pos

#define EXTI_RTSR_TR1_Pos   (1U)

◆ EXTI_RTSR_TR2

#define EXTI_RTSR_TR2   EXTI_RTSR_TR2_Msk

Rising trigger event configuration bit of line 2

◆ EXTI_RTSR_TR20

#define EXTI_RTSR_TR20   EXTI_RTSR_TR20_Msk

Rising trigger event configuration bit of line 20

◆ EXTI_RTSR_TR20_Msk

#define EXTI_RTSR_TR20_Msk   (0x1U << EXTI_RTSR_TR20_Pos)

0x00100000

◆ EXTI_RTSR_TR20_Pos

#define EXTI_RTSR_TR20_Pos   (20U)

◆ EXTI_RTSR_TR21

#define EXTI_RTSR_TR21   EXTI_RTSR_TR21_Msk

Rising trigger event configuration bit of line 21

◆ EXTI_RTSR_TR21_Msk

#define EXTI_RTSR_TR21_Msk   (0x1U << EXTI_RTSR_TR21_Pos)

0x00200000

◆ EXTI_RTSR_TR21_Pos

#define EXTI_RTSR_TR21_Pos   (21U)

◆ EXTI_RTSR_TR22

#define EXTI_RTSR_TR22   EXTI_RTSR_TR22_Msk

Rising trigger event configuration bit of line 22

◆ EXTI_RTSR_TR22_Msk

#define EXTI_RTSR_TR22_Msk   (0x1U << EXTI_RTSR_TR22_Pos)

0x00400000

◆ EXTI_RTSR_TR22_Pos

#define EXTI_RTSR_TR22_Pos   (22U)

◆ EXTI_RTSR_TR23

#define EXTI_RTSR_TR23   EXTI_RTSR_TR23_Msk

Rising trigger event configuration bit of line 23

◆ EXTI_RTSR_TR23_Msk

#define EXTI_RTSR_TR23_Msk   (0x1U << EXTI_RTSR_TR23_Pos)

0x00800000

◆ EXTI_RTSR_TR23_Pos

#define EXTI_RTSR_TR23_Pos   (23U)

◆ EXTI_RTSR_TR2_Msk

#define EXTI_RTSR_TR2_Msk   (0x1U << EXTI_RTSR_TR2_Pos)

0x00000004

◆ EXTI_RTSR_TR2_Pos

#define EXTI_RTSR_TR2_Pos   (2U)

◆ EXTI_RTSR_TR3

#define EXTI_RTSR_TR3   EXTI_RTSR_TR3_Msk

Rising trigger event configuration bit of line 3

◆ EXTI_RTSR_TR3_Msk

#define EXTI_RTSR_TR3_Msk   (0x1U << EXTI_RTSR_TR3_Pos)

0x00000008

◆ EXTI_RTSR_TR3_Pos

#define EXTI_RTSR_TR3_Pos   (3U)

◆ EXTI_RTSR_TR4

#define EXTI_RTSR_TR4   EXTI_RTSR_TR4_Msk

Rising trigger event configuration bit of line 4

◆ EXTI_RTSR_TR4_Msk

#define EXTI_RTSR_TR4_Msk   (0x1U << EXTI_RTSR_TR4_Pos)

0x00000010

◆ EXTI_RTSR_TR4_Pos

#define EXTI_RTSR_TR4_Pos   (4U)

◆ EXTI_RTSR_TR5

#define EXTI_RTSR_TR5   EXTI_RTSR_TR5_Msk

Rising trigger event configuration bit of line 5

◆ EXTI_RTSR_TR5_Msk

#define EXTI_RTSR_TR5_Msk   (0x1U << EXTI_RTSR_TR5_Pos)

0x00000020

◆ EXTI_RTSR_TR5_Pos

#define EXTI_RTSR_TR5_Pos   (5U)

◆ EXTI_RTSR_TR6

#define EXTI_RTSR_TR6   EXTI_RTSR_TR6_Msk

Rising trigger event configuration bit of line 6

◆ EXTI_RTSR_TR6_Msk

#define EXTI_RTSR_TR6_Msk   (0x1U << EXTI_RTSR_TR6_Pos)

0x00000040

◆ EXTI_RTSR_TR6_Pos

#define EXTI_RTSR_TR6_Pos   (6U)

◆ EXTI_RTSR_TR7

#define EXTI_RTSR_TR7   EXTI_RTSR_TR7_Msk

Rising trigger event configuration bit of line 7

◆ EXTI_RTSR_TR7_Msk

#define EXTI_RTSR_TR7_Msk   (0x1U << EXTI_RTSR_TR7_Pos)

0x00000080

◆ EXTI_RTSR_TR7_Pos

#define EXTI_RTSR_TR7_Pos   (7U)

◆ EXTI_RTSR_TR8

#define EXTI_RTSR_TR8   EXTI_RTSR_TR8_Msk

Rising trigger event configuration bit of line 8

◆ EXTI_RTSR_TR8_Msk

#define EXTI_RTSR_TR8_Msk   (0x1U << EXTI_RTSR_TR8_Pos)

0x00000100

◆ EXTI_RTSR_TR8_Pos

#define EXTI_RTSR_TR8_Pos   (8U)

◆ EXTI_RTSR_TR9

#define EXTI_RTSR_TR9   EXTI_RTSR_TR9_Msk

Rising trigger event configuration bit of line 9

◆ EXTI_RTSR_TR9_Msk

#define EXTI_RTSR_TR9_Msk   (0x1U << EXTI_RTSR_TR9_Pos)

0x00000200

◆ EXTI_RTSR_TR9_Pos

#define EXTI_RTSR_TR9_Pos   (9U)

◆ EXTI_SWIER_SWI0

#define EXTI_SWIER_SWI0   EXTI_SWIER_SWIER0

◆ EXTI_SWIER_SWI1

#define EXTI_SWIER_SWI1   EXTI_SWIER_SWIER1

◆ EXTI_SWIER_SWI10

#define EXTI_SWIER_SWI10   EXTI_SWIER_SWIER10

◆ EXTI_SWIER_SWI11

#define EXTI_SWIER_SWI11   EXTI_SWIER_SWIER11

◆ EXTI_SWIER_SWI12

#define EXTI_SWIER_SWI12   EXTI_SWIER_SWIER12

◆ EXTI_SWIER_SWI13

#define EXTI_SWIER_SWI13   EXTI_SWIER_SWIER13

◆ EXTI_SWIER_SWI14

#define EXTI_SWIER_SWI14   EXTI_SWIER_SWIER14

◆ EXTI_SWIER_SWI15

#define EXTI_SWIER_SWI15   EXTI_SWIER_SWIER15

◆ EXTI_SWIER_SWI16

#define EXTI_SWIER_SWI16   EXTI_SWIER_SWIER16

◆ EXTI_SWIER_SWI17

#define EXTI_SWIER_SWI17   EXTI_SWIER_SWIER17

◆ EXTI_SWIER_SWI18

#define EXTI_SWIER_SWI18   EXTI_SWIER_SWIER18

◆ EXTI_SWIER_SWI19

#define EXTI_SWIER_SWI19   EXTI_SWIER_SWIER19

◆ EXTI_SWIER_SWI2

#define EXTI_SWIER_SWI2   EXTI_SWIER_SWIER2

◆ EXTI_SWIER_SWI20

#define EXTI_SWIER_SWI20   EXTI_SWIER_SWIER20

◆ EXTI_SWIER_SWI21

#define EXTI_SWIER_SWI21   EXTI_SWIER_SWIER21

◆ EXTI_SWIER_SWI22

#define EXTI_SWIER_SWI22   EXTI_SWIER_SWIER22

◆ EXTI_SWIER_SWI23

#define EXTI_SWIER_SWI23   EXTI_SWIER_SWIER23

◆ EXTI_SWIER_SWI3

#define EXTI_SWIER_SWI3   EXTI_SWIER_SWIER3

◆ EXTI_SWIER_SWI4

#define EXTI_SWIER_SWI4   EXTI_SWIER_SWIER4

◆ EXTI_SWIER_SWI5

#define EXTI_SWIER_SWI5   EXTI_SWIER_SWIER5

◆ EXTI_SWIER_SWI6

#define EXTI_SWIER_SWI6   EXTI_SWIER_SWIER6

◆ EXTI_SWIER_SWI7

#define EXTI_SWIER_SWI7   EXTI_SWIER_SWIER7

◆ EXTI_SWIER_SWI8

#define EXTI_SWIER_SWI8   EXTI_SWIER_SWIER8

◆ EXTI_SWIER_SWI9

#define EXTI_SWIER_SWI9   EXTI_SWIER_SWIER9

◆ EXTI_SWIER_SWIER0

#define EXTI_SWIER_SWIER0   EXTI_SWIER_SWIER0_Msk

Software Interrupt on line 0

◆ EXTI_SWIER_SWIER0_Msk

#define EXTI_SWIER_SWIER0_Msk   (0x1U << EXTI_SWIER_SWIER0_Pos)

0x00000001

◆ EXTI_SWIER_SWIER0_Pos

#define EXTI_SWIER_SWIER0_Pos   (0U)

◆ EXTI_SWIER_SWIER1

#define EXTI_SWIER_SWIER1   EXTI_SWIER_SWIER1_Msk

Software Interrupt on line 1

◆ EXTI_SWIER_SWIER10

#define EXTI_SWIER_SWIER10   EXTI_SWIER_SWIER10_Msk

Software Interrupt on line 10

◆ EXTI_SWIER_SWIER10_Msk

#define EXTI_SWIER_SWIER10_Msk   (0x1U << EXTI_SWIER_SWIER10_Pos)

0x00000400

◆ EXTI_SWIER_SWIER10_Pos

#define EXTI_SWIER_SWIER10_Pos   (10U)

◆ EXTI_SWIER_SWIER11

#define EXTI_SWIER_SWIER11   EXTI_SWIER_SWIER11_Msk

Software Interrupt on line 11

◆ EXTI_SWIER_SWIER11_Msk

#define EXTI_SWIER_SWIER11_Msk   (0x1U << EXTI_SWIER_SWIER11_Pos)

0x00000800

◆ EXTI_SWIER_SWIER11_Pos

#define EXTI_SWIER_SWIER11_Pos   (11U)

◆ EXTI_SWIER_SWIER12

#define EXTI_SWIER_SWIER12   EXTI_SWIER_SWIER12_Msk

Software Interrupt on line 12

◆ EXTI_SWIER_SWIER12_Msk

#define EXTI_SWIER_SWIER12_Msk   (0x1U << EXTI_SWIER_SWIER12_Pos)

0x00001000

◆ EXTI_SWIER_SWIER12_Pos

#define EXTI_SWIER_SWIER12_Pos   (12U)

◆ EXTI_SWIER_SWIER13

#define EXTI_SWIER_SWIER13   EXTI_SWIER_SWIER13_Msk

Software Interrupt on line 13

◆ EXTI_SWIER_SWIER13_Msk

#define EXTI_SWIER_SWIER13_Msk   (0x1U << EXTI_SWIER_SWIER13_Pos)

0x00002000

◆ EXTI_SWIER_SWIER13_Pos

#define EXTI_SWIER_SWIER13_Pos   (13U)

◆ EXTI_SWIER_SWIER14

#define EXTI_SWIER_SWIER14   EXTI_SWIER_SWIER14_Msk

Software Interrupt on line 14

◆ EXTI_SWIER_SWIER14_Msk

#define EXTI_SWIER_SWIER14_Msk   (0x1U << EXTI_SWIER_SWIER14_Pos)

0x00004000

◆ EXTI_SWIER_SWIER14_Pos

#define EXTI_SWIER_SWIER14_Pos   (14U)

◆ EXTI_SWIER_SWIER15

#define EXTI_SWIER_SWIER15   EXTI_SWIER_SWIER15_Msk

Software Interrupt on line 15

◆ EXTI_SWIER_SWIER15_Msk

#define EXTI_SWIER_SWIER15_Msk   (0x1U << EXTI_SWIER_SWIER15_Pos)

0x00008000

◆ EXTI_SWIER_SWIER15_Pos

#define EXTI_SWIER_SWIER15_Pos   (15U)

◆ EXTI_SWIER_SWIER16

#define EXTI_SWIER_SWIER16   EXTI_SWIER_SWIER16_Msk

Software Interrupt on line 16

◆ EXTI_SWIER_SWIER16_Msk

#define EXTI_SWIER_SWIER16_Msk   (0x1U << EXTI_SWIER_SWIER16_Pos)

0x00010000

◆ EXTI_SWIER_SWIER16_Pos

#define EXTI_SWIER_SWIER16_Pos   (16U)

◆ EXTI_SWIER_SWIER17

#define EXTI_SWIER_SWIER17   EXTI_SWIER_SWIER17_Msk

Software Interrupt on line 17

◆ EXTI_SWIER_SWIER17_Msk

#define EXTI_SWIER_SWIER17_Msk   (0x1U << EXTI_SWIER_SWIER17_Pos)

0x00020000

◆ EXTI_SWIER_SWIER17_Pos

#define EXTI_SWIER_SWIER17_Pos   (17U)

◆ EXTI_SWIER_SWIER18

#define EXTI_SWIER_SWIER18   EXTI_SWIER_SWIER18_Msk

Software Interrupt on line 18

◆ EXTI_SWIER_SWIER18_Msk

#define EXTI_SWIER_SWIER18_Msk   (0x1U << EXTI_SWIER_SWIER18_Pos)

0x00040000

◆ EXTI_SWIER_SWIER18_Pos

#define EXTI_SWIER_SWIER18_Pos   (18U)

◆ EXTI_SWIER_SWIER19

#define EXTI_SWIER_SWIER19   EXTI_SWIER_SWIER19_Msk

Software Interrupt on line 19

◆ EXTI_SWIER_SWIER19_Msk

#define EXTI_SWIER_SWIER19_Msk   (0x1U << EXTI_SWIER_SWIER19_Pos)

0x00080000

◆ EXTI_SWIER_SWIER19_Pos

#define EXTI_SWIER_SWIER19_Pos   (19U)

◆ EXTI_SWIER_SWIER1_Msk

#define EXTI_SWIER_SWIER1_Msk   (0x1U << EXTI_SWIER_SWIER1_Pos)

0x00000002

◆ EXTI_SWIER_SWIER1_Pos

#define EXTI_SWIER_SWIER1_Pos   (1U)

◆ EXTI_SWIER_SWIER2

#define EXTI_SWIER_SWIER2   EXTI_SWIER_SWIER2_Msk

Software Interrupt on line 2

◆ EXTI_SWIER_SWIER20

#define EXTI_SWIER_SWIER20   EXTI_SWIER_SWIER20_Msk

Software Interrupt on line 20

◆ EXTI_SWIER_SWIER20_Msk

#define EXTI_SWIER_SWIER20_Msk   (0x1U << EXTI_SWIER_SWIER20_Pos)

0x00100000

◆ EXTI_SWIER_SWIER20_Pos

#define EXTI_SWIER_SWIER20_Pos   (20U)

◆ EXTI_SWIER_SWIER21

#define EXTI_SWIER_SWIER21   EXTI_SWIER_SWIER21_Msk

Software Interrupt on line 21

◆ EXTI_SWIER_SWIER21_Msk

#define EXTI_SWIER_SWIER21_Msk   (0x1U << EXTI_SWIER_SWIER21_Pos)

0x00200000

◆ EXTI_SWIER_SWIER21_Pos

#define EXTI_SWIER_SWIER21_Pos   (21U)

◆ EXTI_SWIER_SWIER22

#define EXTI_SWIER_SWIER22   EXTI_SWIER_SWIER22_Msk

Software Interrupt on line 22

◆ EXTI_SWIER_SWIER22_Msk

#define EXTI_SWIER_SWIER22_Msk   (0x1U << EXTI_SWIER_SWIER22_Pos)

0x00400000

◆ EXTI_SWIER_SWIER22_Pos

#define EXTI_SWIER_SWIER22_Pos   (22U)

◆ EXTI_SWIER_SWIER23

#define EXTI_SWIER_SWIER23   EXTI_SWIER_SWIER23_Msk

Software Interrupt on line 23

◆ EXTI_SWIER_SWIER23_Msk

#define EXTI_SWIER_SWIER23_Msk   (0x1U << EXTI_SWIER_SWIER23_Pos)

0x00800000

◆ EXTI_SWIER_SWIER23_Pos

#define EXTI_SWIER_SWIER23_Pos   (23U)

◆ EXTI_SWIER_SWIER2_Msk

#define EXTI_SWIER_SWIER2_Msk   (0x1U << EXTI_SWIER_SWIER2_Pos)

0x00000004

◆ EXTI_SWIER_SWIER2_Pos

#define EXTI_SWIER_SWIER2_Pos   (2U)

◆ EXTI_SWIER_SWIER3

#define EXTI_SWIER_SWIER3   EXTI_SWIER_SWIER3_Msk

Software Interrupt on line 3

◆ EXTI_SWIER_SWIER3_Msk

#define EXTI_SWIER_SWIER3_Msk   (0x1U << EXTI_SWIER_SWIER3_Pos)

0x00000008

◆ EXTI_SWIER_SWIER3_Pos

#define EXTI_SWIER_SWIER3_Pos   (3U)

◆ EXTI_SWIER_SWIER4

#define EXTI_SWIER_SWIER4   EXTI_SWIER_SWIER4_Msk

Software Interrupt on line 4

◆ EXTI_SWIER_SWIER4_Msk

#define EXTI_SWIER_SWIER4_Msk   (0x1U << EXTI_SWIER_SWIER4_Pos)

0x00000010

◆ EXTI_SWIER_SWIER4_Pos

#define EXTI_SWIER_SWIER4_Pos   (4U)

◆ EXTI_SWIER_SWIER5

#define EXTI_SWIER_SWIER5   EXTI_SWIER_SWIER5_Msk

Software Interrupt on line 5

◆ EXTI_SWIER_SWIER5_Msk

#define EXTI_SWIER_SWIER5_Msk   (0x1U << EXTI_SWIER_SWIER5_Pos)

0x00000020

◆ EXTI_SWIER_SWIER5_Pos

#define EXTI_SWIER_SWIER5_Pos   (5U)

◆ EXTI_SWIER_SWIER6

#define EXTI_SWIER_SWIER6   EXTI_SWIER_SWIER6_Msk

Software Interrupt on line 6

◆ EXTI_SWIER_SWIER6_Msk

#define EXTI_SWIER_SWIER6_Msk   (0x1U << EXTI_SWIER_SWIER6_Pos)

0x00000040

◆ EXTI_SWIER_SWIER6_Pos

#define EXTI_SWIER_SWIER6_Pos   (6U)

◆ EXTI_SWIER_SWIER7

#define EXTI_SWIER_SWIER7   EXTI_SWIER_SWIER7_Msk

Software Interrupt on line 7

◆ EXTI_SWIER_SWIER7_Msk

#define EXTI_SWIER_SWIER7_Msk   (0x1U << EXTI_SWIER_SWIER7_Pos)

0x00000080

◆ EXTI_SWIER_SWIER7_Pos

#define EXTI_SWIER_SWIER7_Pos   (7U)

◆ EXTI_SWIER_SWIER8

#define EXTI_SWIER_SWIER8   EXTI_SWIER_SWIER8_Msk

Software Interrupt on line 8

◆ EXTI_SWIER_SWIER8_Msk

#define EXTI_SWIER_SWIER8_Msk   (0x1U << EXTI_SWIER_SWIER8_Pos)

0x00000100

◆ EXTI_SWIER_SWIER8_Pos

#define EXTI_SWIER_SWIER8_Pos   (8U)

◆ EXTI_SWIER_SWIER9

#define EXTI_SWIER_SWIER9   EXTI_SWIER_SWIER9_Msk

Software Interrupt on line 9

◆ EXTI_SWIER_SWIER9_Msk

#define EXTI_SWIER_SWIER9_Msk   (0x1U << EXTI_SWIER_SWIER9_Pos)

0x00000200

◆ EXTI_SWIER_SWIER9_Pos

#define EXTI_SWIER_SWIER9_Pos   (9U)

◆ FLASH_ACR_ACC64

#define FLASH_ACR_ACC64   FLASH_ACR_ACC64_Msk

Access 64 bits

◆ FLASH_ACR_ACC64_Msk

#define FLASH_ACR_ACC64_Msk   (0x1U << FLASH_ACR_ACC64_Pos)

0x00000004

◆ FLASH_ACR_ACC64_Pos

#define FLASH_ACR_ACC64_Pos   (2U)

◆ FLASH_ACR_LATENCY

#define FLASH_ACR_LATENCY   FLASH_ACR_LATENCY_Msk

Latency

◆ FLASH_ACR_LATENCY_Msk

#define FLASH_ACR_LATENCY_Msk   (0x1U << FLASH_ACR_LATENCY_Pos)

0x00000001

◆ FLASH_ACR_LATENCY_Pos

#define FLASH_ACR_LATENCY_Pos   (0U)

◆ FLASH_ACR_PRFTEN

#define FLASH_ACR_PRFTEN   FLASH_ACR_PRFTEN_Msk

Prefetch Buffer Enable

◆ FLASH_ACR_PRFTEN_Msk

#define FLASH_ACR_PRFTEN_Msk   (0x1U << FLASH_ACR_PRFTEN_Pos)

0x00000002

◆ FLASH_ACR_PRFTEN_Pos

#define FLASH_ACR_PRFTEN_Pos   (1U)

◆ FLASH_ACR_RUN_PD

#define FLASH_ACR_RUN_PD   FLASH_ACR_RUN_PD_Msk

Flash mode during RUN mode

◆ FLASH_ACR_RUN_PD_Msk

#define FLASH_ACR_RUN_PD_Msk   (0x1U << FLASH_ACR_RUN_PD_Pos)

0x00000010

◆ FLASH_ACR_RUN_PD_Pos

#define FLASH_ACR_RUN_PD_Pos   (4U)

◆ FLASH_ACR_SLEEP_PD

#define FLASH_ACR_SLEEP_PD   FLASH_ACR_SLEEP_PD_Msk

Flash mode during sleep mode

◆ FLASH_ACR_SLEEP_PD_Msk

#define FLASH_ACR_SLEEP_PD_Msk   (0x1U << FLASH_ACR_SLEEP_PD_Pos)

0x00000008

◆ FLASH_ACR_SLEEP_PD_Pos

#define FLASH_ACR_SLEEP_PD_Pos   (3U)

◆ FLASH_OBR_BOR_LEV

#define FLASH_OBR_BOR_LEV   FLASH_OBR_BOR_LEV_Msk

BOR_LEV[3:0] Brown Out Reset Threshold Level

◆ FLASH_OBR_BOR_LEV_Msk

#define FLASH_OBR_BOR_LEV_Msk   (0xFU << FLASH_OBR_BOR_LEV_Pos)

0x000F0000

◆ FLASH_OBR_BOR_LEV_Pos

#define FLASH_OBR_BOR_LEV_Pos   (16U)

◆ FLASH_OBR_IWDG_SW

#define FLASH_OBR_IWDG_SW   FLASH_OBR_IWDG_SW_Msk

IWDG_SW

◆ FLASH_OBR_IWDG_SW_Msk

#define FLASH_OBR_IWDG_SW_Msk   (0x1U << FLASH_OBR_IWDG_SW_Pos)

0x00100000

◆ FLASH_OBR_IWDG_SW_Pos

#define FLASH_OBR_IWDG_SW_Pos   (20U)

◆ FLASH_OBR_nRST_BFB2

#define FLASH_OBR_nRST_BFB2   FLASH_OBR_nRST_BFB2_Msk

BFB2

◆ FLASH_OBR_nRST_BFB2_Msk

#define FLASH_OBR_nRST_BFB2_Msk   (0x1U << FLASH_OBR_nRST_BFB2_Pos)

0x00800000

◆ FLASH_OBR_nRST_BFB2_Pos

#define FLASH_OBR_nRST_BFB2_Pos   (23U)

◆ FLASH_OBR_nRST_STDBY

#define FLASH_OBR_nRST_STDBY   FLASH_OBR_nRST_STDBY_Msk

nRST_STDBY

◆ FLASH_OBR_nRST_STDBY_Msk

#define FLASH_OBR_nRST_STDBY_Msk   (0x1U << FLASH_OBR_nRST_STDBY_Pos)

0x00400000

◆ FLASH_OBR_nRST_STDBY_Pos

#define FLASH_OBR_nRST_STDBY_Pos   (22U)

◆ FLASH_OBR_nRST_STOP

#define FLASH_OBR_nRST_STOP   FLASH_OBR_nRST_STOP_Msk

nRST_STOP

◆ FLASH_OBR_nRST_STOP_Msk

#define FLASH_OBR_nRST_STOP_Msk   (0x1U << FLASH_OBR_nRST_STOP_Pos)

0x00200000

◆ FLASH_OBR_nRST_STOP_Pos

#define FLASH_OBR_nRST_STOP_Pos   (21U)

◆ FLASH_OBR_RDPRT

#define FLASH_OBR_RDPRT   FLASH_OBR_RDPRT_Msk

Read Protection

◆ FLASH_OBR_RDPRT_Msk

#define FLASH_OBR_RDPRT_Msk   (0xFFU << FLASH_OBR_RDPRT_Pos)

0x000000FF

◆ FLASH_OBR_RDPRT_Pos

#define FLASH_OBR_RDPRT_Pos   (0U)

◆ FLASH_OBR_USER

#define FLASH_OBR_USER   FLASH_OBR_USER_Msk

User Option Bytes

◆ FLASH_OBR_USER_Msk

#define FLASH_OBR_USER_Msk   (0xFU << FLASH_OBR_USER_Pos)

0x00F00000

◆ FLASH_OBR_USER_Pos

#define FLASH_OBR_USER_Pos   (20U)

◆ FLASH_OPTKEYR_OPTKEYR

#define FLASH_OPTKEYR_OPTKEYR   FLASH_OPTKEYR_OPTKEYR_Msk

Option bytes matrix Key

◆ FLASH_OPTKEYR_OPTKEYR_Msk

#define FLASH_OPTKEYR_OPTKEYR_Msk   (0xFFFFFFFFU << FLASH_OPTKEYR_OPTKEYR_Pos)

0xFFFFFFFF

◆ FLASH_OPTKEYR_OPTKEYR_Pos

#define FLASH_OPTKEYR_OPTKEYR_Pos   (0U)

◆ FLASH_PDKEYR_PDKEYR

#define FLASH_PDKEYR_PDKEYR   FLASH_PDKEYR_PDKEYR_Msk

FLASH_PEC and data matrix Key

◆ FLASH_PDKEYR_PDKEYR_Msk

#define FLASH_PDKEYR_PDKEYR_Msk   (0xFFFFFFFFU << FLASH_PDKEYR_PDKEYR_Pos)

0xFFFFFFFF

◆ FLASH_PDKEYR_PDKEYR_Pos

#define FLASH_PDKEYR_PDKEYR_Pos   (0U)

◆ FLASH_PECR_DATA

#define FLASH_PECR_DATA   FLASH_PECR_DATA_Msk

Data matrix selection

◆ FLASH_PECR_DATA_Msk

#define FLASH_PECR_DATA_Msk   (0x1U << FLASH_PECR_DATA_Pos)

0x00000010

◆ FLASH_PECR_DATA_Pos

#define FLASH_PECR_DATA_Pos   (4U)

◆ FLASH_PECR_EOPIE

#define FLASH_PECR_EOPIE   FLASH_PECR_EOPIE_Msk

End of programming interrupt

◆ FLASH_PECR_EOPIE_Msk

#define FLASH_PECR_EOPIE_Msk   (0x1U << FLASH_PECR_EOPIE_Pos)

0x00010000

◆ FLASH_PECR_EOPIE_Pos

#define FLASH_PECR_EOPIE_Pos   (16U)

◆ FLASH_PECR_ERASE

#define FLASH_PECR_ERASE   FLASH_PECR_ERASE_Msk

Page erasing mode

◆ FLASH_PECR_ERASE_Msk

#define FLASH_PECR_ERASE_Msk   (0x1U << FLASH_PECR_ERASE_Pos)

0x00000200

◆ FLASH_PECR_ERASE_Pos

#define FLASH_PECR_ERASE_Pos   (9U)

◆ FLASH_PECR_ERRIE

#define FLASH_PECR_ERRIE   FLASH_PECR_ERRIE_Msk

Error interrupt

◆ FLASH_PECR_ERRIE_Msk

#define FLASH_PECR_ERRIE_Msk   (0x1U << FLASH_PECR_ERRIE_Pos)

0x00020000

◆ FLASH_PECR_ERRIE_Pos

#define FLASH_PECR_ERRIE_Pos   (17U)

◆ FLASH_PECR_FPRG

#define FLASH_PECR_FPRG   FLASH_PECR_FPRG_Msk

Fast Page/Half Page programming mode

◆ FLASH_PECR_FPRG_Msk

#define FLASH_PECR_FPRG_Msk   (0x1U << FLASH_PECR_FPRG_Pos)

0x00000400

◆ FLASH_PECR_FPRG_Pos

#define FLASH_PECR_FPRG_Pos   (10U)

◆ FLASH_PECR_FTDW

#define FLASH_PECR_FTDW   FLASH_PECR_FTDW_Msk

Fixed Time Data write for Word/Half Word/Byte programming

◆ FLASH_PECR_FTDW_Msk

#define FLASH_PECR_FTDW_Msk   (0x1U << FLASH_PECR_FTDW_Pos)

0x00000100

◆ FLASH_PECR_FTDW_Pos

#define FLASH_PECR_FTDW_Pos   (8U)

◆ FLASH_PECR_OBL_LAUNCH

#define FLASH_PECR_OBL_LAUNCH   FLASH_PECR_OBL_LAUNCH_Msk

Launch the option byte loading

◆ FLASH_PECR_OBL_LAUNCH_Msk

#define FLASH_PECR_OBL_LAUNCH_Msk   (0x1U << FLASH_PECR_OBL_LAUNCH_Pos)

0x00040000

◆ FLASH_PECR_OBL_LAUNCH_Pos

#define FLASH_PECR_OBL_LAUNCH_Pos   (18U)

◆ FLASH_PECR_OPTLOCK

#define FLASH_PECR_OPTLOCK   FLASH_PECR_OPTLOCK_Msk

Option byte matrix Lock

◆ FLASH_PECR_OPTLOCK_Msk

#define FLASH_PECR_OPTLOCK_Msk   (0x1U << FLASH_PECR_OPTLOCK_Pos)

0x00000004

◆ FLASH_PECR_OPTLOCK_Pos

#define FLASH_PECR_OPTLOCK_Pos   (2U)

◆ FLASH_PECR_PARALLBANK

#define FLASH_PECR_PARALLBANK   FLASH_PECR_PARALLBANK_Msk

Parallel Bank mode

◆ FLASH_PECR_PARALLBANK_Msk

#define FLASH_PECR_PARALLBANK_Msk   (0x1U << FLASH_PECR_PARALLBANK_Pos)

0x00008000

◆ FLASH_PECR_PARALLBANK_Pos

#define FLASH_PECR_PARALLBANK_Pos   (15U)

◆ FLASH_PECR_PELOCK

#define FLASH_PECR_PELOCK   FLASH_PECR_PELOCK_Msk

FLASH_PECR and Flash data Lock

◆ FLASH_PECR_PELOCK_Msk

#define FLASH_PECR_PELOCK_Msk   (0x1U << FLASH_PECR_PELOCK_Pos)

0x00000001

◆ FLASH_PECR_PELOCK_Pos

#define FLASH_PECR_PELOCK_Pos   (0U)

◆ FLASH_PECR_PRGLOCK

#define FLASH_PECR_PRGLOCK   FLASH_PECR_PRGLOCK_Msk

Program matrix Lock

◆ FLASH_PECR_PRGLOCK_Msk

#define FLASH_PECR_PRGLOCK_Msk   (0x1U << FLASH_PECR_PRGLOCK_Pos)

0x00000002

◆ FLASH_PECR_PRGLOCK_Pos

#define FLASH_PECR_PRGLOCK_Pos   (1U)

◆ FLASH_PECR_PROG

#define FLASH_PECR_PROG   FLASH_PECR_PROG_Msk

Program matrix selection

◆ FLASH_PECR_PROG_Msk

#define FLASH_PECR_PROG_Msk   (0x1U << FLASH_PECR_PROG_Pos)

0x00000008

◆ FLASH_PECR_PROG_Pos

#define FLASH_PECR_PROG_Pos   (3U)

◆ FLASH_PEKEYR_PEKEYR

#define FLASH_PEKEYR_PEKEYR   FLASH_PEKEYR_PEKEYR_Msk

FLASH_PEC and data matrix Key

◆ FLASH_PEKEYR_PEKEYR_Msk

#define FLASH_PEKEYR_PEKEYR_Msk   (0xFFFFFFFFU << FLASH_PEKEYR_PEKEYR_Pos)

0xFFFFFFFF

◆ FLASH_PEKEYR_PEKEYR_Pos

#define FLASH_PEKEYR_PEKEYR_Pos   (0U)

◆ FLASH_PRGKEYR_PRGKEYR

#define FLASH_PRGKEYR_PRGKEYR   FLASH_PRGKEYR_PRGKEYR_Msk

Program matrix Key

◆ FLASH_PRGKEYR_PRGKEYR_Msk

#define FLASH_PRGKEYR_PRGKEYR_Msk   (0xFFFFFFFFU << FLASH_PRGKEYR_PRGKEYR_Pos)

0xFFFFFFFF

◆ FLASH_PRGKEYR_PRGKEYR_Pos

#define FLASH_PRGKEYR_PRGKEYR_Pos   (0U)

◆ FLASH_SR_BSY

#define FLASH_SR_BSY   FLASH_SR_BSY_Msk

Busy

◆ FLASH_SR_BSY_Msk

#define FLASH_SR_BSY_Msk   (0x1U << FLASH_SR_BSY_Pos)

0x00000001

◆ FLASH_SR_BSY_Pos

#define FLASH_SR_BSY_Pos   (0U)

◆ FLASH_SR_ENDHV

#define FLASH_SR_ENDHV   FLASH_SR_ENDHV_Msk

End of high voltage

◆ FLASH_SR_ENDHV_Msk

#define FLASH_SR_ENDHV_Msk   (0x1U << FLASH_SR_ENDHV_Pos)

0x00000004

◆ FLASH_SR_ENDHV_Pos

#define FLASH_SR_ENDHV_Pos   (2U)

◆ FLASH_SR_EOP

#define FLASH_SR_EOP   FLASH_SR_EOP_Msk

End Of Programming

◆ FLASH_SR_EOP_Msk

#define FLASH_SR_EOP_Msk   (0x1U << FLASH_SR_EOP_Pos)

0x00000002

◆ FLASH_SR_EOP_Pos

#define FLASH_SR_EOP_Pos   (1U)

◆ FLASH_SR_OPTVERR

#define FLASH_SR_OPTVERR   FLASH_SR_OPTVERR_Msk

Option validity error

◆ FLASH_SR_OPTVERR_Msk

#define FLASH_SR_OPTVERR_Msk   (0x1U << FLASH_SR_OPTVERR_Pos)

0x00000800

◆ FLASH_SR_OPTVERR_Pos

#define FLASH_SR_OPTVERR_Pos   (11U)

◆ FLASH_SR_OPTVERRUSR

#define FLASH_SR_OPTVERRUSR   FLASH_SR_OPTVERRUSR_Msk

Option User validity error

◆ FLASH_SR_OPTVERRUSR_Msk

#define FLASH_SR_OPTVERRUSR_Msk   (0x1U << FLASH_SR_OPTVERRUSR_Pos)

0x00001000

◆ FLASH_SR_OPTVERRUSR_Pos

#define FLASH_SR_OPTVERRUSR_Pos   (12U)

◆ FLASH_SR_PGAERR

#define FLASH_SR_PGAERR   FLASH_SR_PGAERR_Msk

Programming Alignment Error

◆ FLASH_SR_PGAERR_Msk

#define FLASH_SR_PGAERR_Msk   (0x1U << FLASH_SR_PGAERR_Pos)

0x00000200

◆ FLASH_SR_PGAERR_Pos

#define FLASH_SR_PGAERR_Pos   (9U)

◆ FLASH_SR_READY

#define FLASH_SR_READY   FLASH_SR_READY_Msk

Flash ready after low power mode

◆ FLASH_SR_READY_Msk

#define FLASH_SR_READY_Msk   (0x1U << FLASH_SR_READY_Pos)

0x00000008

◆ FLASH_SR_READY_Pos

#define FLASH_SR_READY_Pos   (3U)

◆ FLASH_SR_SIZERR

#define FLASH_SR_SIZERR   FLASH_SR_SIZERR_Msk

Size error

◆ FLASH_SR_SIZERR_Msk

#define FLASH_SR_SIZERR_Msk   (0x1U << FLASH_SR_SIZERR_Pos)

0x00000400

◆ FLASH_SR_SIZERR_Pos

#define FLASH_SR_SIZERR_Pos   (10U)

◆ FLASH_SR_WRPERR

#define FLASH_SR_WRPERR   FLASH_SR_WRPERR_Msk

Write protected error

◆ FLASH_SR_WRPERR_Msk

#define FLASH_SR_WRPERR_Msk   (0x1U << FLASH_SR_WRPERR_Pos)

0x00000100

◆ FLASH_SR_WRPERR_Pos

#define FLASH_SR_WRPERR_Pos   (8U)

◆ FLASH_WRPR1_WRP

#define FLASH_WRPR1_WRP   FLASH_WRPR1_WRP_Msk

Write Protect sectors 0 to 31

◆ FLASH_WRPR1_WRP_Msk

#define FLASH_WRPR1_WRP_Msk   (0xFFFFFFFFU << FLASH_WRPR1_WRP_Pos)

0xFFFFFFFF

◆ FLASH_WRPR1_WRP_Pos

#define FLASH_WRPR1_WRP_Pos   (0U)

◆ FLASH_WRPR2_WRP

#define FLASH_WRPR2_WRP   FLASH_WRPR2_WRP_Msk

Write Protect sectors 32 to 63

◆ FLASH_WRPR2_WRP_Msk

#define FLASH_WRPR2_WRP_Msk   (0xFFFFFFFFU << FLASH_WRPR2_WRP_Pos)

0xFFFFFFFF

◆ FLASH_WRPR2_WRP_Pos

#define FLASH_WRPR2_WRP_Pos   (0U)

◆ FLASH_WRPR3_WRP

#define FLASH_WRPR3_WRP   FLASH_WRPR3_WRP_Msk

Write Protect sectors 64 to 95

◆ FLASH_WRPR3_WRP_Msk

#define FLASH_WRPR3_WRP_Msk   (0xFFFFFFFFU << FLASH_WRPR3_WRP_Pos)

0xFFFFFFFF

◆ FLASH_WRPR3_WRP_Pos

#define FLASH_WRPR3_WRP_Pos   (0U)

◆ FLASH_WRPR4_WRP

#define FLASH_WRPR4_WRP   FLASH_WRPR4_WRP_Msk

Write Protect sectors 96 to 127

◆ FLASH_WRPR4_WRP_Msk

#define FLASH_WRPR4_WRP_Msk   (0xFFFFFFFFU << FLASH_WRPR4_WRP_Pos)

0xFFFFFFFF

◆ FLASH_WRPR4_WRP_Pos

#define FLASH_WRPR4_WRP_Pos   (0U)

◆ GPIO_AFRH_AFSEL10

#define GPIO_AFRH_AFSEL10   GPIO_AFRH_AFSEL10_Msk

◆ GPIO_AFRH_AFSEL10_Msk

#define GPIO_AFRH_AFSEL10_Msk   (0xFU << GPIO_AFRH_AFSEL10_Pos)

0x00000F00

◆ GPIO_AFRH_AFSEL10_Pos

#define GPIO_AFRH_AFSEL10_Pos   (8U)

◆ GPIO_AFRH_AFSEL11

#define GPIO_AFRH_AFSEL11   GPIO_AFRH_AFSEL11_Msk

◆ GPIO_AFRH_AFSEL11_Msk

#define GPIO_AFRH_AFSEL11_Msk   (0xFU << GPIO_AFRH_AFSEL11_Pos)

0x0000F000

◆ GPIO_AFRH_AFSEL11_Pos

#define GPIO_AFRH_AFSEL11_Pos   (12U)

◆ GPIO_AFRH_AFSEL12

#define GPIO_AFRH_AFSEL12   GPIO_AFRH_AFSEL12_Msk

◆ GPIO_AFRH_AFSEL12_Msk

#define GPIO_AFRH_AFSEL12_Msk   (0xFU << GPIO_AFRH_AFSEL12_Pos)

0x000F0000

◆ GPIO_AFRH_AFSEL12_Pos

#define GPIO_AFRH_AFSEL12_Pos   (16U)

◆ GPIO_AFRH_AFSEL13

#define GPIO_AFRH_AFSEL13   GPIO_AFRH_AFSEL13_Msk

◆ GPIO_AFRH_AFSEL13_Msk

#define GPIO_AFRH_AFSEL13_Msk   (0xFU << GPIO_AFRH_AFSEL13_Pos)

0x00F00000

◆ GPIO_AFRH_AFSEL13_Pos

#define GPIO_AFRH_AFSEL13_Pos   (20U)

◆ GPIO_AFRH_AFSEL14

#define GPIO_AFRH_AFSEL14   GPIO_AFRH_AFSEL14_Msk

◆ GPIO_AFRH_AFSEL14_Msk

#define GPIO_AFRH_AFSEL14_Msk   (0xFU << GPIO_AFRH_AFSEL14_Pos)

0x0F000000

◆ GPIO_AFRH_AFSEL14_Pos

#define GPIO_AFRH_AFSEL14_Pos   (24U)

◆ GPIO_AFRH_AFSEL15

#define GPIO_AFRH_AFSEL15   GPIO_AFRH_AFSEL15_Msk

◆ GPIO_AFRH_AFSEL15_Msk

#define GPIO_AFRH_AFSEL15_Msk   (0xFU << GPIO_AFRH_AFSEL15_Pos)

0xF0000000

◆ GPIO_AFRH_AFSEL15_Pos

#define GPIO_AFRH_AFSEL15_Pos   (28U)

◆ GPIO_AFRH_AFSEL8

#define GPIO_AFRH_AFSEL8   GPIO_AFRH_AFSEL8_Msk

◆ GPIO_AFRH_AFSEL8_Msk

#define GPIO_AFRH_AFSEL8_Msk   (0xFU << GPIO_AFRH_AFSEL8_Pos)

0x0000000F

◆ GPIO_AFRH_AFSEL8_Pos

#define GPIO_AFRH_AFSEL8_Pos   (0U)

◆ GPIO_AFRH_AFSEL9

#define GPIO_AFRH_AFSEL9   GPIO_AFRH_AFSEL9_Msk

◆ GPIO_AFRH_AFSEL9_Msk

#define GPIO_AFRH_AFSEL9_Msk   (0xFU << GPIO_AFRH_AFSEL9_Pos)

0x000000F0

◆ GPIO_AFRH_AFSEL9_Pos

#define GPIO_AFRH_AFSEL9_Pos   (4U)

◆ GPIO_AFRL_AFSEL0

#define GPIO_AFRL_AFSEL0   GPIO_AFRL_AFSEL0_Msk

◆ GPIO_AFRL_AFSEL0_Msk

#define GPIO_AFRL_AFSEL0_Msk   (0xFU << GPIO_AFRL_AFSEL0_Pos)

0x0000000F

◆ GPIO_AFRL_AFSEL0_Pos

#define GPIO_AFRL_AFSEL0_Pos   (0U)

◆ GPIO_AFRL_AFSEL1

#define GPIO_AFRL_AFSEL1   GPIO_AFRL_AFSEL1_Msk

◆ GPIO_AFRL_AFSEL1_Msk

#define GPIO_AFRL_AFSEL1_Msk   (0xFU << GPIO_AFRL_AFSEL1_Pos)

0x000000F0

◆ GPIO_AFRL_AFSEL1_Pos

#define GPIO_AFRL_AFSEL1_Pos   (4U)

◆ GPIO_AFRL_AFSEL2

#define GPIO_AFRL_AFSEL2   GPIO_AFRL_AFSEL2_Msk

◆ GPIO_AFRL_AFSEL2_Msk

#define GPIO_AFRL_AFSEL2_Msk   (0xFU << GPIO_AFRL_AFSEL2_Pos)

0x00000F00

◆ GPIO_AFRL_AFSEL2_Pos

#define GPIO_AFRL_AFSEL2_Pos   (8U)

◆ GPIO_AFRL_AFSEL3

#define GPIO_AFRL_AFSEL3   GPIO_AFRL_AFSEL3_Msk

◆ GPIO_AFRL_AFSEL3_Msk

#define GPIO_AFRL_AFSEL3_Msk   (0xFU << GPIO_AFRL_AFSEL3_Pos)

0x0000F000

◆ GPIO_AFRL_AFSEL3_Pos

#define GPIO_AFRL_AFSEL3_Pos   (12U)

◆ GPIO_AFRL_AFSEL4

#define GPIO_AFRL_AFSEL4   GPIO_AFRL_AFSEL4_Msk

◆ GPIO_AFRL_AFSEL4_Msk

#define GPIO_AFRL_AFSEL4_Msk   (0xFU << GPIO_AFRL_AFSEL4_Pos)

0x000F0000

◆ GPIO_AFRL_AFSEL4_Pos

#define GPIO_AFRL_AFSEL4_Pos   (16U)

◆ GPIO_AFRL_AFSEL5

#define GPIO_AFRL_AFSEL5   GPIO_AFRL_AFSEL5_Msk

◆ GPIO_AFRL_AFSEL5_Msk

#define GPIO_AFRL_AFSEL5_Msk   (0xFU << GPIO_AFRL_AFSEL5_Pos)

0x00F00000

◆ GPIO_AFRL_AFSEL5_Pos

#define GPIO_AFRL_AFSEL5_Pos   (20U)

◆ GPIO_AFRL_AFSEL6

#define GPIO_AFRL_AFSEL6   GPIO_AFRL_AFSEL6_Msk

◆ GPIO_AFRL_AFSEL6_Msk

#define GPIO_AFRL_AFSEL6_Msk   (0xFU << GPIO_AFRL_AFSEL6_Pos)

0x0F000000

◆ GPIO_AFRL_AFSEL6_Pos

#define GPIO_AFRL_AFSEL6_Pos   (24U)

◆ GPIO_AFRL_AFSEL7

#define GPIO_AFRL_AFSEL7   GPIO_AFRL_AFSEL7_Msk

◆ GPIO_AFRL_AFSEL7_Msk

#define GPIO_AFRL_AFSEL7_Msk   (0xFU << GPIO_AFRL_AFSEL7_Pos)

0xF0000000

◆ GPIO_AFRL_AFSEL7_Pos

#define GPIO_AFRL_AFSEL7_Pos   (28U)

◆ GPIO_BRR_BR_0

#define GPIO_BRR_BR_0   (0x00000001U)

◆ GPIO_BRR_BR_1

#define GPIO_BRR_BR_1   (0x00000002U)

◆ GPIO_BRR_BR_10

#define GPIO_BRR_BR_10   (0x00000400U)

◆ GPIO_BRR_BR_11

#define GPIO_BRR_BR_11   (0x00000800U)

◆ GPIO_BRR_BR_12

#define GPIO_BRR_BR_12   (0x00001000U)

◆ GPIO_BRR_BR_13

#define GPIO_BRR_BR_13   (0x00002000U)

◆ GPIO_BRR_BR_14

#define GPIO_BRR_BR_14   (0x00004000U)

◆ GPIO_BRR_BR_15

#define GPIO_BRR_BR_15   (0x00008000U)

◆ GPIO_BRR_BR_2

#define GPIO_BRR_BR_2   (0x00000004U)

◆ GPIO_BRR_BR_3

#define GPIO_BRR_BR_3   (0x00000008U)

◆ GPIO_BRR_BR_4

#define GPIO_BRR_BR_4   (0x00000010U)

◆ GPIO_BRR_BR_5

#define GPIO_BRR_BR_5   (0x00000020U)

◆ GPIO_BRR_BR_6

#define GPIO_BRR_BR_6   (0x00000040U)

◆ GPIO_BRR_BR_7

#define GPIO_BRR_BR_7   (0x00000080U)

◆ GPIO_BRR_BR_8

#define GPIO_BRR_BR_8   (0x00000100U)

◆ GPIO_BRR_BR_9

#define GPIO_BRR_BR_9   (0x00000200U)

◆ GPIO_BSRR_BR_0

#define GPIO_BSRR_BR_0   (0x00010000U)

◆ GPIO_BSRR_BR_1

#define GPIO_BSRR_BR_1   (0x00020000U)

◆ GPIO_BSRR_BR_10

#define GPIO_BSRR_BR_10   (0x04000000U)

◆ GPIO_BSRR_BR_11

#define GPIO_BSRR_BR_11   (0x08000000U)

◆ GPIO_BSRR_BR_12

#define GPIO_BSRR_BR_12   (0x10000000U)

◆ GPIO_BSRR_BR_13

#define GPIO_BSRR_BR_13   (0x20000000U)

◆ GPIO_BSRR_BR_14

#define GPIO_BSRR_BR_14   (0x40000000U)

◆ GPIO_BSRR_BR_15

#define GPIO_BSRR_BR_15   (0x80000000U)

◆ GPIO_BSRR_BR_2

#define GPIO_BSRR_BR_2   (0x00040000U)

◆ GPIO_BSRR_BR_3

#define GPIO_BSRR_BR_3   (0x00080000U)

◆ GPIO_BSRR_BR_4

#define GPIO_BSRR_BR_4   (0x00100000U)

◆ GPIO_BSRR_BR_5

#define GPIO_BSRR_BR_5   (0x00200000U)

◆ GPIO_BSRR_BR_6

#define GPIO_BSRR_BR_6   (0x00400000U)

◆ GPIO_BSRR_BR_7

#define GPIO_BSRR_BR_7   (0x00800000U)

◆ GPIO_BSRR_BR_8

#define GPIO_BSRR_BR_8   (0x01000000U)

◆ GPIO_BSRR_BR_9

#define GPIO_BSRR_BR_9   (0x02000000U)

◆ GPIO_BSRR_BS_0

#define GPIO_BSRR_BS_0   (0x00000001U)

◆ GPIO_BSRR_BS_1

#define GPIO_BSRR_BS_1   (0x00000002U)

◆ GPIO_BSRR_BS_10

#define GPIO_BSRR_BS_10   (0x00000400U)

◆ GPIO_BSRR_BS_11

#define GPIO_BSRR_BS_11   (0x00000800U)

◆ GPIO_BSRR_BS_12

#define GPIO_BSRR_BS_12   (0x00001000U)

◆ GPIO_BSRR_BS_13

#define GPIO_BSRR_BS_13   (0x00002000U)

◆ GPIO_BSRR_BS_14

#define GPIO_BSRR_BS_14   (0x00004000U)

◆ GPIO_BSRR_BS_15

#define GPIO_BSRR_BS_15   (0x00008000U)

◆ GPIO_BSRR_BS_2

#define GPIO_BSRR_BS_2   (0x00000004U)

◆ GPIO_BSRR_BS_3

#define GPIO_BSRR_BS_3   (0x00000008U)

◆ GPIO_BSRR_BS_4

#define GPIO_BSRR_BS_4   (0x00000010U)

◆ GPIO_BSRR_BS_5

#define GPIO_BSRR_BS_5   (0x00000020U)

◆ GPIO_BSRR_BS_6

#define GPIO_BSRR_BS_6   (0x00000040U)

◆ GPIO_BSRR_BS_7

#define GPIO_BSRR_BS_7   (0x00000080U)

◆ GPIO_BSRR_BS_8

#define GPIO_BSRR_BS_8   (0x00000100U)

◆ GPIO_BSRR_BS_9

#define GPIO_BSRR_BS_9   (0x00000200U)

◆ GPIO_IDR_IDR_0

#define GPIO_IDR_IDR_0   (0x00000001U)

◆ GPIO_IDR_IDR_1

#define GPIO_IDR_IDR_1   (0x00000002U)

◆ GPIO_IDR_IDR_10

#define GPIO_IDR_IDR_10   (0x00000400U)

◆ GPIO_IDR_IDR_11

#define GPIO_IDR_IDR_11   (0x00000800U)

◆ GPIO_IDR_IDR_12

#define GPIO_IDR_IDR_12   (0x00001000U)

◆ GPIO_IDR_IDR_13

#define GPIO_IDR_IDR_13   (0x00002000U)

◆ GPIO_IDR_IDR_14

#define GPIO_IDR_IDR_14   (0x00004000U)

◆ GPIO_IDR_IDR_15

#define GPIO_IDR_IDR_15   (0x00008000U)

◆ GPIO_IDR_IDR_2

#define GPIO_IDR_IDR_2   (0x00000004U)

◆ GPIO_IDR_IDR_3

#define GPIO_IDR_IDR_3   (0x00000008U)

◆ GPIO_IDR_IDR_4

#define GPIO_IDR_IDR_4   (0x00000010U)

◆ GPIO_IDR_IDR_5

#define GPIO_IDR_IDR_5   (0x00000020U)

◆ GPIO_IDR_IDR_6

#define GPIO_IDR_IDR_6   (0x00000040U)

◆ GPIO_IDR_IDR_7

#define GPIO_IDR_IDR_7   (0x00000080U)

◆ GPIO_IDR_IDR_8

#define GPIO_IDR_IDR_8   (0x00000100U)

◆ GPIO_IDR_IDR_9

#define GPIO_IDR_IDR_9   (0x00000200U)

◆ GPIO_LCKR_LCK0

#define GPIO_LCKR_LCK0   GPIO_LCKR_LCK0_Msk

◆ GPIO_LCKR_LCK0_Msk

#define GPIO_LCKR_LCK0_Msk   (0x1U << GPIO_LCKR_LCK0_Pos)

0x00000001

◆ GPIO_LCKR_LCK0_Pos

#define GPIO_LCKR_LCK0_Pos   (0U)

◆ GPIO_LCKR_LCK1

#define GPIO_LCKR_LCK1   GPIO_LCKR_LCK1_Msk

◆ GPIO_LCKR_LCK10

#define GPIO_LCKR_LCK10   GPIO_LCKR_LCK10_Msk

◆ GPIO_LCKR_LCK10_Msk

#define GPIO_LCKR_LCK10_Msk   (0x1U << GPIO_LCKR_LCK10_Pos)

0x00000400

◆ GPIO_LCKR_LCK10_Pos

#define GPIO_LCKR_LCK10_Pos   (10U)

◆ GPIO_LCKR_LCK11

#define GPIO_LCKR_LCK11   GPIO_LCKR_LCK11_Msk

◆ GPIO_LCKR_LCK11_Msk

#define GPIO_LCKR_LCK11_Msk   (0x1U << GPIO_LCKR_LCK11_Pos)

0x00000800

◆ GPIO_LCKR_LCK11_Pos

#define GPIO_LCKR_LCK11_Pos   (11U)

◆ GPIO_LCKR_LCK12

#define GPIO_LCKR_LCK12   GPIO_LCKR_LCK12_Msk

◆ GPIO_LCKR_LCK12_Msk

#define GPIO_LCKR_LCK12_Msk   (0x1U << GPIO_LCKR_LCK12_Pos)

0x00001000

◆ GPIO_LCKR_LCK12_Pos

#define GPIO_LCKR_LCK12_Pos   (12U)

◆ GPIO_LCKR_LCK13

#define GPIO_LCKR_LCK13   GPIO_LCKR_LCK13_Msk

◆ GPIO_LCKR_LCK13_Msk

#define GPIO_LCKR_LCK13_Msk   (0x1U << GPIO_LCKR_LCK13_Pos)

0x00002000

◆ GPIO_LCKR_LCK13_Pos

#define GPIO_LCKR_LCK13_Pos   (13U)

◆ GPIO_LCKR_LCK14

#define GPIO_LCKR_LCK14   GPIO_LCKR_LCK14_Msk

◆ GPIO_LCKR_LCK14_Msk

#define GPIO_LCKR_LCK14_Msk   (0x1U << GPIO_LCKR_LCK14_Pos)

0x00004000

◆ GPIO_LCKR_LCK14_Pos

#define GPIO_LCKR_LCK14_Pos   (14U)

◆ GPIO_LCKR_LCK15

#define GPIO_LCKR_LCK15   GPIO_LCKR_LCK15_Msk

◆ GPIO_LCKR_LCK15_Msk

#define GPIO_LCKR_LCK15_Msk   (0x1U << GPIO_LCKR_LCK15_Pos)

0x00008000

◆ GPIO_LCKR_LCK15_Pos

#define GPIO_LCKR_LCK15_Pos   (15U)

◆ GPIO_LCKR_LCK1_Msk

#define GPIO_LCKR_LCK1_Msk   (0x1U << GPIO_LCKR_LCK1_Pos)

0x00000002

◆ GPIO_LCKR_LCK1_Pos

#define GPIO_LCKR_LCK1_Pos   (1U)

◆ GPIO_LCKR_LCK2

#define GPIO_LCKR_LCK2   GPIO_LCKR_LCK2_Msk

◆ GPIO_LCKR_LCK2_Msk

#define GPIO_LCKR_LCK2_Msk   (0x1U << GPIO_LCKR_LCK2_Pos)

0x00000004

◆ GPIO_LCKR_LCK2_Pos

#define GPIO_LCKR_LCK2_Pos   (2U)

◆ GPIO_LCKR_LCK3

#define GPIO_LCKR_LCK3   GPIO_LCKR_LCK3_Msk

◆ GPIO_LCKR_LCK3_Msk

#define GPIO_LCKR_LCK3_Msk   (0x1U << GPIO_LCKR_LCK3_Pos)

0x00000008

◆ GPIO_LCKR_LCK3_Pos

#define GPIO_LCKR_LCK3_Pos   (3U)

◆ GPIO_LCKR_LCK4

#define GPIO_LCKR_LCK4   GPIO_LCKR_LCK4_Msk

◆ GPIO_LCKR_LCK4_Msk

#define GPIO_LCKR_LCK4_Msk   (0x1U << GPIO_LCKR_LCK4_Pos)

0x00000010

◆ GPIO_LCKR_LCK4_Pos

#define GPIO_LCKR_LCK4_Pos   (4U)

◆ GPIO_LCKR_LCK5

#define GPIO_LCKR_LCK5   GPIO_LCKR_LCK5_Msk

◆ GPIO_LCKR_LCK5_Msk

#define GPIO_LCKR_LCK5_Msk   (0x1U << GPIO_LCKR_LCK5_Pos)

0x00000020

◆ GPIO_LCKR_LCK5_Pos

#define GPIO_LCKR_LCK5_Pos   (5U)

◆ GPIO_LCKR_LCK6

#define GPIO_LCKR_LCK6   GPIO_LCKR_LCK6_Msk

◆ GPIO_LCKR_LCK6_Msk

#define GPIO_LCKR_LCK6_Msk   (0x1U << GPIO_LCKR_LCK6_Pos)

0x00000040

◆ GPIO_LCKR_LCK6_Pos

#define GPIO_LCKR_LCK6_Pos   (6U)

◆ GPIO_LCKR_LCK7

#define GPIO_LCKR_LCK7   GPIO_LCKR_LCK7_Msk

◆ GPIO_LCKR_LCK7_Msk

#define GPIO_LCKR_LCK7_Msk   (0x1U << GPIO_LCKR_LCK7_Pos)

0x00000080

◆ GPIO_LCKR_LCK7_Pos

#define GPIO_LCKR_LCK7_Pos   (7U)

◆ GPIO_LCKR_LCK8

#define GPIO_LCKR_LCK8   GPIO_LCKR_LCK8_Msk

◆ GPIO_LCKR_LCK8_Msk

#define GPIO_LCKR_LCK8_Msk   (0x1U << GPIO_LCKR_LCK8_Pos)

0x00000100

◆ GPIO_LCKR_LCK8_Pos

#define GPIO_LCKR_LCK8_Pos   (8U)

◆ GPIO_LCKR_LCK9

#define GPIO_LCKR_LCK9   GPIO_LCKR_LCK9_Msk

◆ GPIO_LCKR_LCK9_Msk

#define GPIO_LCKR_LCK9_Msk   (0x1U << GPIO_LCKR_LCK9_Pos)

0x00000200

◆ GPIO_LCKR_LCK9_Pos

#define GPIO_LCKR_LCK9_Pos   (9U)

◆ GPIO_LCKR_LCKK

#define GPIO_LCKR_LCKK   GPIO_LCKR_LCKK_Msk

◆ GPIO_LCKR_LCKK_Msk

#define GPIO_LCKR_LCKK_Msk   (0x1U << GPIO_LCKR_LCKK_Pos)

0x00010000

◆ GPIO_LCKR_LCKK_Pos

#define GPIO_LCKR_LCKK_Pos   (16U)

◆ GPIO_MODER_MODER0

#define GPIO_MODER_MODER0   GPIO_MODER_MODER0_Msk

◆ GPIO_MODER_MODER0_0

#define GPIO_MODER_MODER0_0   (0x1U << GPIO_MODER_MODER0_Pos)

0x00000001

◆ GPIO_MODER_MODER0_1

#define GPIO_MODER_MODER0_1   (0x2U << GPIO_MODER_MODER0_Pos)

0x00000002

◆ GPIO_MODER_MODER0_Msk

#define GPIO_MODER_MODER0_Msk   (0x3U << GPIO_MODER_MODER0_Pos)

0x00000003

◆ GPIO_MODER_MODER0_Pos

#define GPIO_MODER_MODER0_Pos   (0U)

◆ GPIO_MODER_MODER1

#define GPIO_MODER_MODER1   GPIO_MODER_MODER1_Msk

◆ GPIO_MODER_MODER10

#define GPIO_MODER_MODER10   GPIO_MODER_MODER10_Msk

◆ GPIO_MODER_MODER10_0

#define GPIO_MODER_MODER10_0   (0x1U << GPIO_MODER_MODER10_Pos)

0x00100000

◆ GPIO_MODER_MODER10_1

#define GPIO_MODER_MODER10_1   (0x2U << GPIO_MODER_MODER10_Pos)

0x00200000

◆ GPIO_MODER_MODER10_Msk

#define GPIO_MODER_MODER10_Msk   (0x3U << GPIO_MODER_MODER10_Pos)

0x00300000

◆ GPIO_MODER_MODER10_Pos

#define GPIO_MODER_MODER10_Pos   (20U)

◆ GPIO_MODER_MODER11

#define GPIO_MODER_MODER11   GPIO_MODER_MODER11_Msk

◆ GPIO_MODER_MODER11_0

#define GPIO_MODER_MODER11_0   (0x1U << GPIO_MODER_MODER11_Pos)

0x00400000

◆ GPIO_MODER_MODER11_1

#define GPIO_MODER_MODER11_1   (0x2U << GPIO_MODER_MODER11_Pos)

0x00800000

◆ GPIO_MODER_MODER11_Msk

#define GPIO_MODER_MODER11_Msk   (0x3U << GPIO_MODER_MODER11_Pos)

0x00C00000

◆ GPIO_MODER_MODER11_Pos

#define GPIO_MODER_MODER11_Pos   (22U)

◆ GPIO_MODER_MODER12

#define GPIO_MODER_MODER12   GPIO_MODER_MODER12_Msk

◆ GPIO_MODER_MODER12_0

#define GPIO_MODER_MODER12_0   (0x1U << GPIO_MODER_MODER12_Pos)

0x01000000

◆ GPIO_MODER_MODER12_1

#define GPIO_MODER_MODER12_1   (0x2U << GPIO_MODER_MODER12_Pos)

0x02000000

◆ GPIO_MODER_MODER12_Msk

#define GPIO_MODER_MODER12_Msk   (0x3U << GPIO_MODER_MODER12_Pos)

0x03000000

◆ GPIO_MODER_MODER12_Pos

#define GPIO_MODER_MODER12_Pos   (24U)

◆ GPIO_MODER_MODER13

#define GPIO_MODER_MODER13   GPIO_MODER_MODER13_Msk

◆ GPIO_MODER_MODER13_0

#define GPIO_MODER_MODER13_0   (0x1U << GPIO_MODER_MODER13_Pos)

0x04000000

◆ GPIO_MODER_MODER13_1

#define GPIO_MODER_MODER13_1   (0x2U << GPIO_MODER_MODER13_Pos)

0x08000000

◆ GPIO_MODER_MODER13_Msk

#define GPIO_MODER_MODER13_Msk   (0x3U << GPIO_MODER_MODER13_Pos)

0x0C000000

◆ GPIO_MODER_MODER13_Pos

#define GPIO_MODER_MODER13_Pos   (26U)

◆ GPIO_MODER_MODER14

#define GPIO_MODER_MODER14   GPIO_MODER_MODER14_Msk

◆ GPIO_MODER_MODER14_0

#define GPIO_MODER_MODER14_0   (0x1U << GPIO_MODER_MODER14_Pos)

0x10000000

◆ GPIO_MODER_MODER14_1

#define GPIO_MODER_MODER14_1   (0x2U << GPIO_MODER_MODER14_Pos)

0x20000000

◆ GPIO_MODER_MODER14_Msk

#define GPIO_MODER_MODER14_Msk   (0x3U << GPIO_MODER_MODER14_Pos)

0x30000000

◆ GPIO_MODER_MODER14_Pos

#define GPIO_MODER_MODER14_Pos   (28U)

◆ GPIO_MODER_MODER15

#define GPIO_MODER_MODER15   GPIO_MODER_MODER15_Msk

◆ GPIO_MODER_MODER15_0

#define GPIO_MODER_MODER15_0   (0x1U << GPIO_MODER_MODER15_Pos)

0x40000000

◆ GPIO_MODER_MODER15_1

#define GPIO_MODER_MODER15_1   (0x2U << GPIO_MODER_MODER15_Pos)

0x80000000

◆ GPIO_MODER_MODER15_Msk

#define GPIO_MODER_MODER15_Msk   (0x3U << GPIO_MODER_MODER15_Pos)

0xC0000000

◆ GPIO_MODER_MODER15_Pos

#define GPIO_MODER_MODER15_Pos   (30U)

◆ GPIO_MODER_MODER1_0

#define GPIO_MODER_MODER1_0   (0x1U << GPIO_MODER_MODER1_Pos)

0x00000004

◆ GPIO_MODER_MODER1_1

#define GPIO_MODER_MODER1_1   (0x2U << GPIO_MODER_MODER1_Pos)

0x00000008

◆ GPIO_MODER_MODER1_Msk

#define GPIO_MODER_MODER1_Msk   (0x3U << GPIO_MODER_MODER1_Pos)

0x0000000C

◆ GPIO_MODER_MODER1_Pos

#define GPIO_MODER_MODER1_Pos   (2U)

◆ GPIO_MODER_MODER2

#define GPIO_MODER_MODER2   GPIO_MODER_MODER2_Msk

◆ GPIO_MODER_MODER2_0

#define GPIO_MODER_MODER2_0   (0x1U << GPIO_MODER_MODER2_Pos)

0x00000010

◆ GPIO_MODER_MODER2_1

#define GPIO_MODER_MODER2_1   (0x2U << GPIO_MODER_MODER2_Pos)

0x00000020

◆ GPIO_MODER_MODER2_Msk

#define GPIO_MODER_MODER2_Msk   (0x3U << GPIO_MODER_MODER2_Pos)

0x00000030

◆ GPIO_MODER_MODER2_Pos

#define GPIO_MODER_MODER2_Pos   (4U)

◆ GPIO_MODER_MODER3

#define GPIO_MODER_MODER3   GPIO_MODER_MODER3_Msk

◆ GPIO_MODER_MODER3_0

#define GPIO_MODER_MODER3_0   (0x1U << GPIO_MODER_MODER3_Pos)

0x00000040

◆ GPIO_MODER_MODER3_1

#define GPIO_MODER_MODER3_1   (0x2U << GPIO_MODER_MODER3_Pos)

0x00000080

◆ GPIO_MODER_MODER3_Msk

#define GPIO_MODER_MODER3_Msk   (0x3U << GPIO_MODER_MODER3_Pos)

0x000000C0

◆ GPIO_MODER_MODER3_Pos

#define GPIO_MODER_MODER3_Pos   (6U)

◆ GPIO_MODER_MODER4

#define GPIO_MODER_MODER4   GPIO_MODER_MODER4_Msk

◆ GPIO_MODER_MODER4_0

#define GPIO_MODER_MODER4_0   (0x1U << GPIO_MODER_MODER4_Pos)

0x00000100

◆ GPIO_MODER_MODER4_1

#define GPIO_MODER_MODER4_1   (0x2U << GPIO_MODER_MODER4_Pos)

0x00000200

◆ GPIO_MODER_MODER4_Msk

#define GPIO_MODER_MODER4_Msk   (0x3U << GPIO_MODER_MODER4_Pos)

0x00000300

◆ GPIO_MODER_MODER4_Pos

#define GPIO_MODER_MODER4_Pos   (8U)

◆ GPIO_MODER_MODER5

#define GPIO_MODER_MODER5   GPIO_MODER_MODER5_Msk

◆ GPIO_MODER_MODER5_0

#define GPIO_MODER_MODER5_0   (0x1U << GPIO_MODER_MODER5_Pos)

0x00000400

◆ GPIO_MODER_MODER5_1

#define GPIO_MODER_MODER5_1   (0x2U << GPIO_MODER_MODER5_Pos)

0x00000800

◆ GPIO_MODER_MODER5_Msk

#define GPIO_MODER_MODER5_Msk   (0x3U << GPIO_MODER_MODER5_Pos)

0x00000C00

◆ GPIO_MODER_MODER5_Pos

#define GPIO_MODER_MODER5_Pos   (10U)

◆ GPIO_MODER_MODER6

#define GPIO_MODER_MODER6   GPIO_MODER_MODER6_Msk

◆ GPIO_MODER_MODER6_0

#define GPIO_MODER_MODER6_0   (0x1U << GPIO_MODER_MODER6_Pos)

0x00001000

◆ GPIO_MODER_MODER6_1

#define GPIO_MODER_MODER6_1   (0x2U << GPIO_MODER_MODER6_Pos)

0x00002000

◆ GPIO_MODER_MODER6_Msk

#define GPIO_MODER_MODER6_Msk   (0x3U << GPIO_MODER_MODER6_Pos)

0x00003000

◆ GPIO_MODER_MODER6_Pos

#define GPIO_MODER_MODER6_Pos   (12U)

◆ GPIO_MODER_MODER7

#define GPIO_MODER_MODER7   GPIO_MODER_MODER7_Msk

◆ GPIO_MODER_MODER7_0

#define GPIO_MODER_MODER7_0   (0x1U << GPIO_MODER_MODER7_Pos)

0x00004000

◆ GPIO_MODER_MODER7_1

#define GPIO_MODER_MODER7_1   (0x2U << GPIO_MODER_MODER7_Pos)

0x00008000

◆ GPIO_MODER_MODER7_Msk

#define GPIO_MODER_MODER7_Msk   (0x3U << GPIO_MODER_MODER7_Pos)

0x0000C000

◆ GPIO_MODER_MODER7_Pos

#define GPIO_MODER_MODER7_Pos   (14U)

◆ GPIO_MODER_MODER8

#define GPIO_MODER_MODER8   GPIO_MODER_MODER8_Msk

◆ GPIO_MODER_MODER8_0

#define GPIO_MODER_MODER8_0   (0x1U << GPIO_MODER_MODER8_Pos)

0x00010000

◆ GPIO_MODER_MODER8_1

#define GPIO_MODER_MODER8_1   (0x2U << GPIO_MODER_MODER8_Pos)

0x00020000

◆ GPIO_MODER_MODER8_Msk

#define GPIO_MODER_MODER8_Msk   (0x3U << GPIO_MODER_MODER8_Pos)

0x00030000

◆ GPIO_MODER_MODER8_Pos

#define GPIO_MODER_MODER8_Pos   (16U)

◆ GPIO_MODER_MODER9

#define GPIO_MODER_MODER9   GPIO_MODER_MODER9_Msk

◆ GPIO_MODER_MODER9_0

#define GPIO_MODER_MODER9_0   (0x1U << GPIO_MODER_MODER9_Pos)

0x00040000

◆ GPIO_MODER_MODER9_1

#define GPIO_MODER_MODER9_1   (0x2U << GPIO_MODER_MODER9_Pos)

0x00080000

◆ GPIO_MODER_MODER9_Msk

#define GPIO_MODER_MODER9_Msk   (0x3U << GPIO_MODER_MODER9_Pos)

0x000C0000

◆ GPIO_MODER_MODER9_Pos

#define GPIO_MODER_MODER9_Pos   (18U)

◆ GPIO_ODR_ODR_0

#define GPIO_ODR_ODR_0   (0x00000001U)

◆ GPIO_ODR_ODR_1

#define GPIO_ODR_ODR_1   (0x00000002U)

◆ GPIO_ODR_ODR_10

#define GPIO_ODR_ODR_10   (0x00000400U)

◆ GPIO_ODR_ODR_11

#define GPIO_ODR_ODR_11   (0x00000800U)

◆ GPIO_ODR_ODR_12

#define GPIO_ODR_ODR_12   (0x00001000U)

◆ GPIO_ODR_ODR_13

#define GPIO_ODR_ODR_13   (0x00002000U)

◆ GPIO_ODR_ODR_14

#define GPIO_ODR_ODR_14   (0x00004000U)

◆ GPIO_ODR_ODR_15

#define GPIO_ODR_ODR_15   (0x00008000U)

◆ GPIO_ODR_ODR_2

#define GPIO_ODR_ODR_2   (0x00000004U)

◆ GPIO_ODR_ODR_3

#define GPIO_ODR_ODR_3   (0x00000008U)

◆ GPIO_ODR_ODR_4

#define GPIO_ODR_ODR_4   (0x00000010U)

◆ GPIO_ODR_ODR_5

#define GPIO_ODR_ODR_5   (0x00000020U)

◆ GPIO_ODR_ODR_6

#define GPIO_ODR_ODR_6   (0x00000040U)

◆ GPIO_ODR_ODR_7

#define GPIO_ODR_ODR_7   (0x00000080U)

◆ GPIO_ODR_ODR_8

#define GPIO_ODR_ODR_8   (0x00000100U)

◆ GPIO_ODR_ODR_9

#define GPIO_ODR_ODR_9   (0x00000200U)

◆ GPIO_OSPEEDER_OSPEEDR0

#define GPIO_OSPEEDER_OSPEEDR0   GPIO_OSPEEDER_OSPEEDR0_Msk

◆ GPIO_OSPEEDER_OSPEEDR0_0

#define GPIO_OSPEEDER_OSPEEDR0_0   (0x1U << GPIO_OSPEEDER_OSPEEDR0_Pos)

0x00000001

◆ GPIO_OSPEEDER_OSPEEDR0_1

#define GPIO_OSPEEDER_OSPEEDR0_1   (0x2U << GPIO_OSPEEDER_OSPEEDR0_Pos)

0x00000002

◆ GPIO_OSPEEDER_OSPEEDR0_Msk

#define GPIO_OSPEEDER_OSPEEDR0_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR0_Pos)

0x00000003

◆ GPIO_OSPEEDER_OSPEEDR0_Pos

#define GPIO_OSPEEDER_OSPEEDR0_Pos   (0U)

◆ GPIO_OSPEEDER_OSPEEDR1

#define GPIO_OSPEEDER_OSPEEDR1   GPIO_OSPEEDER_OSPEEDR1_Msk

◆ GPIO_OSPEEDER_OSPEEDR10

#define GPIO_OSPEEDER_OSPEEDR10   GPIO_OSPEEDER_OSPEEDR10_Msk

◆ GPIO_OSPEEDER_OSPEEDR10_0

#define GPIO_OSPEEDER_OSPEEDR10_0   (0x1U << GPIO_OSPEEDER_OSPEEDR10_Pos)

0x00100000

◆ GPIO_OSPEEDER_OSPEEDR10_1

#define GPIO_OSPEEDER_OSPEEDR10_1   (0x2U << GPIO_OSPEEDER_OSPEEDR10_Pos)

0x00200000

◆ GPIO_OSPEEDER_OSPEEDR10_Msk

#define GPIO_OSPEEDER_OSPEEDR10_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR10_Pos)

0x00300000

◆ GPIO_OSPEEDER_OSPEEDR10_Pos

#define GPIO_OSPEEDER_OSPEEDR10_Pos   (20U)

◆ GPIO_OSPEEDER_OSPEEDR11

#define GPIO_OSPEEDER_OSPEEDR11   GPIO_OSPEEDER_OSPEEDR11_Msk

◆ GPIO_OSPEEDER_OSPEEDR11_0

#define GPIO_OSPEEDER_OSPEEDR11_0   (0x1U << GPIO_OSPEEDER_OSPEEDR11_Pos)

0x00400000

◆ GPIO_OSPEEDER_OSPEEDR11_1

#define GPIO_OSPEEDER_OSPEEDR11_1   (0x2U << GPIO_OSPEEDER_OSPEEDR11_Pos)

0x00800000

◆ GPIO_OSPEEDER_OSPEEDR11_Msk

#define GPIO_OSPEEDER_OSPEEDR11_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR11_Pos)

0x00C00000

◆ GPIO_OSPEEDER_OSPEEDR11_Pos

#define GPIO_OSPEEDER_OSPEEDR11_Pos   (22U)

◆ GPIO_OSPEEDER_OSPEEDR12

#define GPIO_OSPEEDER_OSPEEDR12   GPIO_OSPEEDER_OSPEEDR12_Msk

◆ GPIO_OSPEEDER_OSPEEDR12_0

#define GPIO_OSPEEDER_OSPEEDR12_0   (0x1U << GPIO_OSPEEDER_OSPEEDR12_Pos)

0x01000000

◆ GPIO_OSPEEDER_OSPEEDR12_1

#define GPIO_OSPEEDER_OSPEEDR12_1   (0x2U << GPIO_OSPEEDER_OSPEEDR12_Pos)

0x02000000

◆ GPIO_OSPEEDER_OSPEEDR12_Msk

#define GPIO_OSPEEDER_OSPEEDR12_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR12_Pos)

0x03000000

◆ GPIO_OSPEEDER_OSPEEDR12_Pos

#define GPIO_OSPEEDER_OSPEEDR12_Pos   (24U)

◆ GPIO_OSPEEDER_OSPEEDR13

#define GPIO_OSPEEDER_OSPEEDR13   GPIO_OSPEEDER_OSPEEDR13_Msk

◆ GPIO_OSPEEDER_OSPEEDR13_0

#define GPIO_OSPEEDER_OSPEEDR13_0   (0x1U << GPIO_OSPEEDER_OSPEEDR13_Pos)

0x04000000

◆ GPIO_OSPEEDER_OSPEEDR13_1

#define GPIO_OSPEEDER_OSPEEDR13_1   (0x2U << GPIO_OSPEEDER_OSPEEDR13_Pos)

0x08000000

◆ GPIO_OSPEEDER_OSPEEDR13_Msk

#define GPIO_OSPEEDER_OSPEEDR13_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR13_Pos)

0x0C000000

◆ GPIO_OSPEEDER_OSPEEDR13_Pos

#define GPIO_OSPEEDER_OSPEEDR13_Pos   (26U)

◆ GPIO_OSPEEDER_OSPEEDR14

#define GPIO_OSPEEDER_OSPEEDR14   GPIO_OSPEEDER_OSPEEDR14_Msk

◆ GPIO_OSPEEDER_OSPEEDR14_0

#define GPIO_OSPEEDER_OSPEEDR14_0   (0x1U << GPIO_OSPEEDER_OSPEEDR14_Pos)

0x10000000

◆ GPIO_OSPEEDER_OSPEEDR14_1

#define GPIO_OSPEEDER_OSPEEDR14_1   (0x2U << GPIO_OSPEEDER_OSPEEDR14_Pos)

0x20000000

◆ GPIO_OSPEEDER_OSPEEDR14_Msk

#define GPIO_OSPEEDER_OSPEEDR14_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR14_Pos)

0x30000000

◆ GPIO_OSPEEDER_OSPEEDR14_Pos

#define GPIO_OSPEEDER_OSPEEDR14_Pos   (28U)

◆ GPIO_OSPEEDER_OSPEEDR15

#define GPIO_OSPEEDER_OSPEEDR15   GPIO_OSPEEDER_OSPEEDR15_Msk

◆ GPIO_OSPEEDER_OSPEEDR15_0

#define GPIO_OSPEEDER_OSPEEDR15_0   (0x1U << GPIO_OSPEEDER_OSPEEDR15_Pos)

0x40000000

◆ GPIO_OSPEEDER_OSPEEDR15_1

#define GPIO_OSPEEDER_OSPEEDR15_1   (0x2U << GPIO_OSPEEDER_OSPEEDR15_Pos)

0x80000000

◆ GPIO_OSPEEDER_OSPEEDR15_Msk

#define GPIO_OSPEEDER_OSPEEDR15_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR15_Pos)

0xC0000000

◆ GPIO_OSPEEDER_OSPEEDR15_Pos

#define GPIO_OSPEEDER_OSPEEDR15_Pos   (30U)

◆ GPIO_OSPEEDER_OSPEEDR1_0

#define GPIO_OSPEEDER_OSPEEDR1_0   (0x1U << GPIO_OSPEEDER_OSPEEDR1_Pos)

0x00000004

◆ GPIO_OSPEEDER_OSPEEDR1_1

#define GPIO_OSPEEDER_OSPEEDR1_1   (0x2U << GPIO_OSPEEDER_OSPEEDR1_Pos)

0x00000008

◆ GPIO_OSPEEDER_OSPEEDR1_Msk

#define GPIO_OSPEEDER_OSPEEDR1_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR1_Pos)

0x0000000C

◆ GPIO_OSPEEDER_OSPEEDR1_Pos

#define GPIO_OSPEEDER_OSPEEDR1_Pos   (2U)

◆ GPIO_OSPEEDER_OSPEEDR2

#define GPIO_OSPEEDER_OSPEEDR2   GPIO_OSPEEDER_OSPEEDR2_Msk

◆ GPIO_OSPEEDER_OSPEEDR2_0

#define GPIO_OSPEEDER_OSPEEDR2_0   (0x1U << GPIO_OSPEEDER_OSPEEDR2_Pos)

0x00000010

◆ GPIO_OSPEEDER_OSPEEDR2_1

#define GPIO_OSPEEDER_OSPEEDR2_1   (0x2U << GPIO_OSPEEDER_OSPEEDR2_Pos)

0x00000020

◆ GPIO_OSPEEDER_OSPEEDR2_Msk

#define GPIO_OSPEEDER_OSPEEDR2_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR2_Pos)

0x00000030

◆ GPIO_OSPEEDER_OSPEEDR2_Pos

#define GPIO_OSPEEDER_OSPEEDR2_Pos   (4U)

◆ GPIO_OSPEEDER_OSPEEDR3

#define GPIO_OSPEEDER_OSPEEDR3   GPIO_OSPEEDER_OSPEEDR3_Msk

◆ GPIO_OSPEEDER_OSPEEDR3_0

#define GPIO_OSPEEDER_OSPEEDR3_0   (0x1U << GPIO_OSPEEDER_OSPEEDR3_Pos)

0x00000040

◆ GPIO_OSPEEDER_OSPEEDR3_1

#define GPIO_OSPEEDER_OSPEEDR3_1   (0x2U << GPIO_OSPEEDER_OSPEEDR3_Pos)

0x00000080

◆ GPIO_OSPEEDER_OSPEEDR3_Msk

#define GPIO_OSPEEDER_OSPEEDR3_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR3_Pos)

0x000000C0

◆ GPIO_OSPEEDER_OSPEEDR3_Pos

#define GPIO_OSPEEDER_OSPEEDR3_Pos   (6U)

◆ GPIO_OSPEEDER_OSPEEDR4

#define GPIO_OSPEEDER_OSPEEDR4   GPIO_OSPEEDER_OSPEEDR4_Msk

◆ GPIO_OSPEEDER_OSPEEDR4_0

#define GPIO_OSPEEDER_OSPEEDR4_0   (0x1U << GPIO_OSPEEDER_OSPEEDR4_Pos)

0x00000100

◆ GPIO_OSPEEDER_OSPEEDR4_1

#define GPIO_OSPEEDER_OSPEEDR4_1   (0x2U << GPIO_OSPEEDER_OSPEEDR4_Pos)

0x00000200

◆ GPIO_OSPEEDER_OSPEEDR4_Msk

#define GPIO_OSPEEDER_OSPEEDR4_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR4_Pos)

0x00000300

◆ GPIO_OSPEEDER_OSPEEDR4_Pos

#define GPIO_OSPEEDER_OSPEEDR4_Pos   (8U)

◆ GPIO_OSPEEDER_OSPEEDR5

#define GPIO_OSPEEDER_OSPEEDR5   GPIO_OSPEEDER_OSPEEDR5_Msk

◆ GPIO_OSPEEDER_OSPEEDR5_0

#define GPIO_OSPEEDER_OSPEEDR5_0   (0x1U << GPIO_OSPEEDER_OSPEEDR5_Pos)

0x00000400

◆ GPIO_OSPEEDER_OSPEEDR5_1

#define GPIO_OSPEEDER_OSPEEDR5_1   (0x2U << GPIO_OSPEEDER_OSPEEDR5_Pos)

0x00000800

◆ GPIO_OSPEEDER_OSPEEDR5_Msk

#define GPIO_OSPEEDER_OSPEEDR5_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR5_Pos)

0x00000C00

◆ GPIO_OSPEEDER_OSPEEDR5_Pos

#define GPIO_OSPEEDER_OSPEEDR5_Pos   (10U)

◆ GPIO_OSPEEDER_OSPEEDR6

#define GPIO_OSPEEDER_OSPEEDR6   GPIO_OSPEEDER_OSPEEDR6_Msk

◆ GPIO_OSPEEDER_OSPEEDR6_0

#define GPIO_OSPEEDER_OSPEEDR6_0   (0x1U << GPIO_OSPEEDER_OSPEEDR6_Pos)

0x00001000

◆ GPIO_OSPEEDER_OSPEEDR6_1

#define GPIO_OSPEEDER_OSPEEDR6_1   (0x2U << GPIO_OSPEEDER_OSPEEDR6_Pos)

0x00002000

◆ GPIO_OSPEEDER_OSPEEDR6_Msk

#define GPIO_OSPEEDER_OSPEEDR6_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR6_Pos)

0x00003000

◆ GPIO_OSPEEDER_OSPEEDR6_Pos

#define GPIO_OSPEEDER_OSPEEDR6_Pos   (12U)

◆ GPIO_OSPEEDER_OSPEEDR7

#define GPIO_OSPEEDER_OSPEEDR7   GPIO_OSPEEDER_OSPEEDR7_Msk

◆ GPIO_OSPEEDER_OSPEEDR7_0

#define GPIO_OSPEEDER_OSPEEDR7_0   (0x1U << GPIO_OSPEEDER_OSPEEDR7_Pos)

0x00004000

◆ GPIO_OSPEEDER_OSPEEDR7_1

#define GPIO_OSPEEDER_OSPEEDR7_1   (0x2U << GPIO_OSPEEDER_OSPEEDR7_Pos)

0x00008000

◆ GPIO_OSPEEDER_OSPEEDR7_Msk

#define GPIO_OSPEEDER_OSPEEDR7_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR7_Pos)

0x0000C000

◆ GPIO_OSPEEDER_OSPEEDR7_Pos

#define GPIO_OSPEEDER_OSPEEDR7_Pos   (14U)

◆ GPIO_OSPEEDER_OSPEEDR8

#define GPIO_OSPEEDER_OSPEEDR8   GPIO_OSPEEDER_OSPEEDR8_Msk

◆ GPIO_OSPEEDER_OSPEEDR8_0

#define GPIO_OSPEEDER_OSPEEDR8_0   (0x1U << GPIO_OSPEEDER_OSPEEDR8_Pos)

0x00010000

◆ GPIO_OSPEEDER_OSPEEDR8_1

#define GPIO_OSPEEDER_OSPEEDR8_1   (0x2U << GPIO_OSPEEDER_OSPEEDR8_Pos)

0x00020000

◆ GPIO_OSPEEDER_OSPEEDR8_Msk

#define GPIO_OSPEEDER_OSPEEDR8_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR8_Pos)

0x00030000

◆ GPIO_OSPEEDER_OSPEEDR8_Pos

#define GPIO_OSPEEDER_OSPEEDR8_Pos   (16U)

◆ GPIO_OSPEEDER_OSPEEDR9

#define GPIO_OSPEEDER_OSPEEDR9   GPIO_OSPEEDER_OSPEEDR9_Msk

◆ GPIO_OSPEEDER_OSPEEDR9_0

#define GPIO_OSPEEDER_OSPEEDR9_0   (0x1U << GPIO_OSPEEDER_OSPEEDR9_Pos)

0x00040000

◆ GPIO_OSPEEDER_OSPEEDR9_1

#define GPIO_OSPEEDER_OSPEEDR9_1   (0x2U << GPIO_OSPEEDER_OSPEEDR9_Pos)

0x00080000

◆ GPIO_OSPEEDER_OSPEEDR9_Msk

#define GPIO_OSPEEDER_OSPEEDR9_Msk   (0x3U << GPIO_OSPEEDER_OSPEEDR9_Pos)

0x000C0000

◆ GPIO_OSPEEDER_OSPEEDR9_Pos

#define GPIO_OSPEEDER_OSPEEDR9_Pos   (18U)

◆ GPIO_OTYPER_OT_0

#define GPIO_OTYPER_OT_0   (0x00000001U)

◆ GPIO_OTYPER_OT_1

#define GPIO_OTYPER_OT_1   (0x00000002U)

◆ GPIO_OTYPER_OT_10

#define GPIO_OTYPER_OT_10   (0x00000400U)

◆ GPIO_OTYPER_OT_11

#define GPIO_OTYPER_OT_11   (0x00000800U)

◆ GPIO_OTYPER_OT_12

#define GPIO_OTYPER_OT_12   (0x00001000U)

◆ GPIO_OTYPER_OT_13

#define GPIO_OTYPER_OT_13   (0x00002000U)

◆ GPIO_OTYPER_OT_14

#define GPIO_OTYPER_OT_14   (0x00004000U)

◆ GPIO_OTYPER_OT_15

#define GPIO_OTYPER_OT_15   (0x00008000U)

◆ GPIO_OTYPER_OT_2

#define GPIO_OTYPER_OT_2   (0x00000004U)

◆ GPIO_OTYPER_OT_3

#define GPIO_OTYPER_OT_3   (0x00000008U)

◆ GPIO_OTYPER_OT_4

#define GPIO_OTYPER_OT_4   (0x00000010U)

◆ GPIO_OTYPER_OT_5

#define GPIO_OTYPER_OT_5   (0x00000020U)

◆ GPIO_OTYPER_OT_6

#define GPIO_OTYPER_OT_6   (0x00000040U)

◆ GPIO_OTYPER_OT_7

#define GPIO_OTYPER_OT_7   (0x00000080U)

◆ GPIO_OTYPER_OT_8

#define GPIO_OTYPER_OT_8   (0x00000100U)

◆ GPIO_OTYPER_OT_9

#define GPIO_OTYPER_OT_9   (0x00000200U)

◆ GPIO_PUPDR_PUPDR0

#define GPIO_PUPDR_PUPDR0   GPIO_PUPDR_PUPDR0_Msk

◆ GPIO_PUPDR_PUPDR0_0

#define GPIO_PUPDR_PUPDR0_0   (0x1U << GPIO_PUPDR_PUPDR0_Pos)

0x00000001

◆ GPIO_PUPDR_PUPDR0_1

#define GPIO_PUPDR_PUPDR0_1   (0x2U << GPIO_PUPDR_PUPDR0_Pos)

0x00000002

◆ GPIO_PUPDR_PUPDR0_Msk

#define GPIO_PUPDR_PUPDR0_Msk   (0x3U << GPIO_PUPDR_PUPDR0_Pos)

0x00000003

◆ GPIO_PUPDR_PUPDR0_Pos

#define GPIO_PUPDR_PUPDR0_Pos   (0U)

◆ GPIO_PUPDR_PUPDR1

#define GPIO_PUPDR_PUPDR1   GPIO_PUPDR_PUPDR1_Msk

◆ GPIO_PUPDR_PUPDR10

#define GPIO_PUPDR_PUPDR10   GPIO_PUPDR_PUPDR10_Msk

◆ GPIO_PUPDR_PUPDR10_0

#define GPIO_PUPDR_PUPDR10_0   (0x1U << GPIO_PUPDR_PUPDR10_Pos)

0x00100000

◆ GPIO_PUPDR_PUPDR10_1

#define GPIO_PUPDR_PUPDR10_1   (0x2U << GPIO_PUPDR_PUPDR10_Pos)

0x00200000

◆ GPIO_PUPDR_PUPDR10_Msk

#define GPIO_PUPDR_PUPDR10_Msk   (0x3U << GPIO_PUPDR_PUPDR10_Pos)

0x00300000

◆ GPIO_PUPDR_PUPDR10_Pos

#define GPIO_PUPDR_PUPDR10_Pos   (20U)

◆ GPIO_PUPDR_PUPDR11

#define GPIO_PUPDR_PUPDR11   GPIO_PUPDR_PUPDR11_Msk

◆ GPIO_PUPDR_PUPDR11_0

#define GPIO_PUPDR_PUPDR11_0   (0x1U << GPIO_PUPDR_PUPDR11_Pos)

0x00400000

◆ GPIO_PUPDR_PUPDR11_1

#define GPIO_PUPDR_PUPDR11_1   (0x2U << GPIO_PUPDR_PUPDR11_Pos)

0x00800000

◆ GPIO_PUPDR_PUPDR11_Msk

#define GPIO_PUPDR_PUPDR11_Msk   (0x3U << GPIO_PUPDR_PUPDR11_Pos)

0x00C00000

◆ GPIO_PUPDR_PUPDR11_Pos

#define GPIO_PUPDR_PUPDR11_Pos   (22U)

◆ GPIO_PUPDR_PUPDR12

#define GPIO_PUPDR_PUPDR12   GPIO_PUPDR_PUPDR12_Msk

◆ GPIO_PUPDR_PUPDR12_0

#define GPIO_PUPDR_PUPDR12_0   (0x1U << GPIO_PUPDR_PUPDR12_Pos)

0x01000000

◆ GPIO_PUPDR_PUPDR12_1

#define GPIO_PUPDR_PUPDR12_1   (0x2U << GPIO_PUPDR_PUPDR12_Pos)

0x02000000

◆ GPIO_PUPDR_PUPDR12_Msk

#define GPIO_PUPDR_PUPDR12_Msk   (0x3U << GPIO_PUPDR_PUPDR12_Pos)

0x03000000

◆ GPIO_PUPDR_PUPDR12_Pos

#define GPIO_PUPDR_PUPDR12_Pos   (24U)

◆ GPIO_PUPDR_PUPDR13

#define GPIO_PUPDR_PUPDR13   GPIO_PUPDR_PUPDR13_Msk

◆ GPIO_PUPDR_PUPDR13_0

#define GPIO_PUPDR_PUPDR13_0   (0x1U << GPIO_PUPDR_PUPDR13_Pos)

0x04000000

◆ GPIO_PUPDR_PUPDR13_1

#define GPIO_PUPDR_PUPDR13_1   (0x2U << GPIO_PUPDR_PUPDR13_Pos)

0x08000000

◆ GPIO_PUPDR_PUPDR13_Msk

#define GPIO_PUPDR_PUPDR13_Msk   (0x3U << GPIO_PUPDR_PUPDR13_Pos)

0x0C000000

◆ GPIO_PUPDR_PUPDR13_Pos

#define GPIO_PUPDR_PUPDR13_Pos   (26U)

◆ GPIO_PUPDR_PUPDR14

#define GPIO_PUPDR_PUPDR14   GPIO_PUPDR_PUPDR14_Msk

◆ GPIO_PUPDR_PUPDR14_0

#define GPIO_PUPDR_PUPDR14_0   (0x1U << GPIO_PUPDR_PUPDR14_Pos)

0x10000000

◆ GPIO_PUPDR_PUPDR14_1

#define GPIO_PUPDR_PUPDR14_1   (0x2U << GPIO_PUPDR_PUPDR14_Pos)

0x20000000

◆ GPIO_PUPDR_PUPDR14_Msk

#define GPIO_PUPDR_PUPDR14_Msk   (0x3U << GPIO_PUPDR_PUPDR14_Pos)

0x30000000

◆ GPIO_PUPDR_PUPDR14_Pos

#define GPIO_PUPDR_PUPDR14_Pos   (28U)

◆ GPIO_PUPDR_PUPDR15

#define GPIO_PUPDR_PUPDR15   GPIO_PUPDR_PUPDR15_Msk

◆ GPIO_PUPDR_PUPDR15_0

#define GPIO_PUPDR_PUPDR15_0   (0x1U << GPIO_PUPDR_PUPDR15_Pos)

0x40000000

◆ GPIO_PUPDR_PUPDR15_1

#define GPIO_PUPDR_PUPDR15_1   (0x2U << GPIO_PUPDR_PUPDR15_Pos)

0x80000000

◆ GPIO_PUPDR_PUPDR15_Msk

#define GPIO_PUPDR_PUPDR15_Msk   (0x3U << GPIO_PUPDR_PUPDR15_Pos)

0xC0000000

◆ GPIO_PUPDR_PUPDR15_Pos

#define GPIO_PUPDR_PUPDR15_Pos   (30U)

◆ GPIO_PUPDR_PUPDR1_0

#define GPIO_PUPDR_PUPDR1_0   (0x1U << GPIO_PUPDR_PUPDR1_Pos)

0x00000004

◆ GPIO_PUPDR_PUPDR1_1

#define GPIO_PUPDR_PUPDR1_1   (0x2U << GPIO_PUPDR_PUPDR1_Pos)

0x00000008

◆ GPIO_PUPDR_PUPDR1_Msk

#define GPIO_PUPDR_PUPDR1_Msk   (0x3U << GPIO_PUPDR_PUPDR1_Pos)

0x0000000C

◆ GPIO_PUPDR_PUPDR1_Pos

#define GPIO_PUPDR_PUPDR1_Pos   (2U)

◆ GPIO_PUPDR_PUPDR2

#define GPIO_PUPDR_PUPDR2   GPIO_PUPDR_PUPDR2_Msk

◆ GPIO_PUPDR_PUPDR2_0

#define GPIO_PUPDR_PUPDR2_0   (0x1U << GPIO_PUPDR_PUPDR2_Pos)

0x00000010

◆ GPIO_PUPDR_PUPDR2_1

#define GPIO_PUPDR_PUPDR2_1   (0x2U << GPIO_PUPDR_PUPDR2_Pos)

0x00000020

◆ GPIO_PUPDR_PUPDR2_Msk

#define GPIO_PUPDR_PUPDR2_Msk   (0x3U << GPIO_PUPDR_PUPDR2_Pos)

0x00000030

◆ GPIO_PUPDR_PUPDR2_Pos

#define GPIO_PUPDR_PUPDR2_Pos   (4U)

◆ GPIO_PUPDR_PUPDR3

#define GPIO_PUPDR_PUPDR3   GPIO_PUPDR_PUPDR3_Msk

◆ GPIO_PUPDR_PUPDR3_0

#define GPIO_PUPDR_PUPDR3_0   (0x1U << GPIO_PUPDR_PUPDR3_Pos)

0x00000040

◆ GPIO_PUPDR_PUPDR3_1

#define GPIO_PUPDR_PUPDR3_1   (0x2U << GPIO_PUPDR_PUPDR3_Pos)

0x00000080

◆ GPIO_PUPDR_PUPDR3_Msk

#define GPIO_PUPDR_PUPDR3_Msk   (0x3U << GPIO_PUPDR_PUPDR3_Pos)

0x000000C0

◆ GPIO_PUPDR_PUPDR3_Pos

#define GPIO_PUPDR_PUPDR3_Pos   (6U)

◆ GPIO_PUPDR_PUPDR4

#define GPIO_PUPDR_PUPDR4   GPIO_PUPDR_PUPDR4_Msk

◆ GPIO_PUPDR_PUPDR4_0

#define GPIO_PUPDR_PUPDR4_0   (0x1U << GPIO_PUPDR_PUPDR4_Pos)

0x00000100

◆ GPIO_PUPDR_PUPDR4_1

#define GPIO_PUPDR_PUPDR4_1   (0x2U << GPIO_PUPDR_PUPDR4_Pos)

0x00000200

◆ GPIO_PUPDR_PUPDR4_Msk

#define GPIO_PUPDR_PUPDR4_Msk   (0x3U << GPIO_PUPDR_PUPDR4_Pos)

0x00000300

◆ GPIO_PUPDR_PUPDR4_Pos

#define GPIO_PUPDR_PUPDR4_Pos   (8U)

◆ GPIO_PUPDR_PUPDR5

#define GPIO_PUPDR_PUPDR5   GPIO_PUPDR_PUPDR5_Msk

◆ GPIO_PUPDR_PUPDR5_0

#define GPIO_PUPDR_PUPDR5_0   (0x1U << GPIO_PUPDR_PUPDR5_Pos)

0x00000400

◆ GPIO_PUPDR_PUPDR5_1

#define GPIO_PUPDR_PUPDR5_1   (0x2U << GPIO_PUPDR_PUPDR5_Pos)

0x00000800

◆ GPIO_PUPDR_PUPDR5_Msk

#define GPIO_PUPDR_PUPDR5_Msk   (0x3U << GPIO_PUPDR_PUPDR5_Pos)

0x00000C00

◆ GPIO_PUPDR_PUPDR5_Pos

#define GPIO_PUPDR_PUPDR5_Pos   (10U)

◆ GPIO_PUPDR_PUPDR6

#define GPIO_PUPDR_PUPDR6   GPIO_PUPDR_PUPDR6_Msk

◆ GPIO_PUPDR_PUPDR6_0

#define GPIO_PUPDR_PUPDR6_0   (0x1U << GPIO_PUPDR_PUPDR6_Pos)

0x00001000

◆ GPIO_PUPDR_PUPDR6_1

#define GPIO_PUPDR_PUPDR6_1   (0x2U << GPIO_PUPDR_PUPDR6_Pos)

0x00002000

◆ GPIO_PUPDR_PUPDR6_Msk

#define GPIO_PUPDR_PUPDR6_Msk   (0x3U << GPIO_PUPDR_PUPDR6_Pos)

0x00003000

◆ GPIO_PUPDR_PUPDR6_Pos

#define GPIO_PUPDR_PUPDR6_Pos   (12U)

◆ GPIO_PUPDR_PUPDR7

#define GPIO_PUPDR_PUPDR7   GPIO_PUPDR_PUPDR7_Msk

◆ GPIO_PUPDR_PUPDR7_0

#define GPIO_PUPDR_PUPDR7_0   (0x1U << GPIO_PUPDR_PUPDR7_Pos)

0x00004000

◆ GPIO_PUPDR_PUPDR7_1

#define GPIO_PUPDR_PUPDR7_1   (0x2U << GPIO_PUPDR_PUPDR7_Pos)

0x00008000

◆ GPIO_PUPDR_PUPDR7_Msk

#define GPIO_PUPDR_PUPDR7_Msk   (0x3U << GPIO_PUPDR_PUPDR7_Pos)

0x0000C000

◆ GPIO_PUPDR_PUPDR7_Pos

#define GPIO_PUPDR_PUPDR7_Pos   (14U)

◆ GPIO_PUPDR_PUPDR8

#define GPIO_PUPDR_PUPDR8   GPIO_PUPDR_PUPDR8_Msk

◆ GPIO_PUPDR_PUPDR8_0

#define GPIO_PUPDR_PUPDR8_0   (0x1U << GPIO_PUPDR_PUPDR8_Pos)

0x00010000

◆ GPIO_PUPDR_PUPDR8_1

#define GPIO_PUPDR_PUPDR8_1   (0x2U << GPIO_PUPDR_PUPDR8_Pos)

0x00020000

◆ GPIO_PUPDR_PUPDR8_Msk

#define GPIO_PUPDR_PUPDR8_Msk   (0x3U << GPIO_PUPDR_PUPDR8_Pos)

0x00030000

◆ GPIO_PUPDR_PUPDR8_Pos

#define GPIO_PUPDR_PUPDR8_Pos   (16U)

◆ GPIO_PUPDR_PUPDR9

#define GPIO_PUPDR_PUPDR9   GPIO_PUPDR_PUPDR9_Msk

◆ GPIO_PUPDR_PUPDR9_0

#define GPIO_PUPDR_PUPDR9_0   (0x1U << GPIO_PUPDR_PUPDR9_Pos)

0x00040000

◆ GPIO_PUPDR_PUPDR9_1

#define GPIO_PUPDR_PUPDR9_1   (0x2U << GPIO_PUPDR_PUPDR9_Pos)

0x00080000

◆ GPIO_PUPDR_PUPDR9_Msk

#define GPIO_PUPDR_PUPDR9_Msk   (0x3U << GPIO_PUPDR_PUPDR9_Pos)

0x000C0000

◆ GPIO_PUPDR_PUPDR9_Pos

#define GPIO_PUPDR_PUPDR9_Pos   (18U)

◆ I2C_CCR_CCR

#define I2C_CCR_CCR   I2C_CCR_CCR_Msk

Clock Control Register in Fast/Standard mode (Master mode)

◆ I2C_CCR_CCR_Msk

#define I2C_CCR_CCR_Msk   (0xFFFU << I2C_CCR_CCR_Pos)

0x00000FFF

◆ I2C_CCR_CCR_Pos

#define I2C_CCR_CCR_Pos   (0U)

◆ I2C_CCR_DUTY

#define I2C_CCR_DUTY   I2C_CCR_DUTY_Msk

Fast Mode Duty Cycle

◆ I2C_CCR_DUTY_Msk

#define I2C_CCR_DUTY_Msk   (0x1U << I2C_CCR_DUTY_Pos)

0x00004000

◆ I2C_CCR_DUTY_Pos

#define I2C_CCR_DUTY_Pos   (14U)

◆ I2C_CCR_FS

#define I2C_CCR_FS   I2C_CCR_FS_Msk

I2C Master Mode Selection

◆ I2C_CCR_FS_Msk

#define I2C_CCR_FS_Msk   (0x1U << I2C_CCR_FS_Pos)

0x00008000

◆ I2C_CCR_FS_Pos

#define I2C_CCR_FS_Pos   (15U)

◆ I2C_CR1_ACK

#define I2C_CR1_ACK   I2C_CR1_ACK_Msk

Acknowledge Enable

◆ I2C_CR1_ACK_Msk

#define I2C_CR1_ACK_Msk   (0x1U << I2C_CR1_ACK_Pos)

0x00000400

◆ I2C_CR1_ACK_Pos

#define I2C_CR1_ACK_Pos   (10U)

◆ I2C_CR1_ALERT

#define I2C_CR1_ALERT   I2C_CR1_ALERT_Msk

SMBus Alert

◆ I2C_CR1_ALERT_Msk

#define I2C_CR1_ALERT_Msk   (0x1U << I2C_CR1_ALERT_Pos)

0x00002000

◆ I2C_CR1_ALERT_Pos

#define I2C_CR1_ALERT_Pos   (13U)

◆ I2C_CR1_ENARP

#define I2C_CR1_ENARP   I2C_CR1_ENARP_Msk

ARP Enable

◆ I2C_CR1_ENARP_Msk

#define I2C_CR1_ENARP_Msk   (0x1U << I2C_CR1_ENARP_Pos)

0x00000010

◆ I2C_CR1_ENARP_Pos

#define I2C_CR1_ENARP_Pos   (4U)

◆ I2C_CR1_ENGC

#define I2C_CR1_ENGC   I2C_CR1_ENGC_Msk

General Call Enable

◆ I2C_CR1_ENGC_Msk

#define I2C_CR1_ENGC_Msk   (0x1U << I2C_CR1_ENGC_Pos)

0x00000040

◆ I2C_CR1_ENGC_Pos

#define I2C_CR1_ENGC_Pos   (6U)

◆ I2C_CR1_ENPEC

#define I2C_CR1_ENPEC   I2C_CR1_ENPEC_Msk

PEC Enable

◆ I2C_CR1_ENPEC_Msk

#define I2C_CR1_ENPEC_Msk   (0x1U << I2C_CR1_ENPEC_Pos)

0x00000020

◆ I2C_CR1_ENPEC_Pos

#define I2C_CR1_ENPEC_Pos   (5U)

◆ I2C_CR1_NOSTRETCH

#define I2C_CR1_NOSTRETCH   I2C_CR1_NOSTRETCH_Msk

Clock Stretching Disable (Slave mode)

◆ I2C_CR1_NOSTRETCH_Msk

#define I2C_CR1_NOSTRETCH_Msk   (0x1U << I2C_CR1_NOSTRETCH_Pos)

0x00000080

◆ I2C_CR1_NOSTRETCH_Pos

#define I2C_CR1_NOSTRETCH_Pos   (7U)

◆ I2C_CR1_PE

#define I2C_CR1_PE   I2C_CR1_PE_Msk

Peripheral Enable

◆ I2C_CR1_PE_Msk

#define I2C_CR1_PE_Msk   (0x1U << I2C_CR1_PE_Pos)

0x00000001

◆ I2C_CR1_PE_Pos

#define I2C_CR1_PE_Pos   (0U)

◆ I2C_CR1_PEC

#define I2C_CR1_PEC   I2C_CR1_PEC_Msk

Packet Error Checking

◆ I2C_CR1_PEC_Msk

#define I2C_CR1_PEC_Msk   (0x1U << I2C_CR1_PEC_Pos)

0x00001000

◆ I2C_CR1_PEC_Pos

#define I2C_CR1_PEC_Pos   (12U)

◆ I2C_CR1_POS

#define I2C_CR1_POS   I2C_CR1_POS_Msk

Acknowledge/PEC Position (for data reception)

◆ I2C_CR1_POS_Msk

#define I2C_CR1_POS_Msk   (0x1U << I2C_CR1_POS_Pos)

0x00000800

◆ I2C_CR1_POS_Pos

#define I2C_CR1_POS_Pos   (11U)

◆ I2C_CR1_SMBTYPE

#define I2C_CR1_SMBTYPE   I2C_CR1_SMBTYPE_Msk

SMBus Type

◆ I2C_CR1_SMBTYPE_Msk

#define I2C_CR1_SMBTYPE_Msk   (0x1U << I2C_CR1_SMBTYPE_Pos)

0x00000008

◆ I2C_CR1_SMBTYPE_Pos

#define I2C_CR1_SMBTYPE_Pos   (3U)

◆ I2C_CR1_SMBUS

#define I2C_CR1_SMBUS   I2C_CR1_SMBUS_Msk

SMBus Mode

◆ I2C_CR1_SMBUS_Msk

#define I2C_CR1_SMBUS_Msk   (0x1U << I2C_CR1_SMBUS_Pos)

0x00000002

◆ I2C_CR1_SMBUS_Pos

#define I2C_CR1_SMBUS_Pos   (1U)

◆ I2C_CR1_START

#define I2C_CR1_START   I2C_CR1_START_Msk

Start Generation

◆ I2C_CR1_START_Msk

#define I2C_CR1_START_Msk   (0x1U << I2C_CR1_START_Pos)

0x00000100

◆ I2C_CR1_START_Pos

#define I2C_CR1_START_Pos   (8U)

◆ I2C_CR1_STOP

#define I2C_CR1_STOP   I2C_CR1_STOP_Msk

Stop Generation

◆ I2C_CR1_STOP_Msk

#define I2C_CR1_STOP_Msk   (0x1U << I2C_CR1_STOP_Pos)

0x00000200

◆ I2C_CR1_STOP_Pos

#define I2C_CR1_STOP_Pos   (9U)

◆ I2C_CR1_SWRST

#define I2C_CR1_SWRST   I2C_CR1_SWRST_Msk

Software Reset

◆ I2C_CR1_SWRST_Msk

#define I2C_CR1_SWRST_Msk   (0x1U << I2C_CR1_SWRST_Pos)

0x00008000

◆ I2C_CR1_SWRST_Pos

#define I2C_CR1_SWRST_Pos   (15U)

◆ I2C_CR2_DMAEN

#define I2C_CR2_DMAEN   I2C_CR2_DMAEN_Msk

DMA Requests Enable

◆ I2C_CR2_DMAEN_Msk

#define I2C_CR2_DMAEN_Msk   (0x1U << I2C_CR2_DMAEN_Pos)

0x00000800

◆ I2C_CR2_DMAEN_Pos

#define I2C_CR2_DMAEN_Pos   (11U)

◆ I2C_CR2_FREQ

#define I2C_CR2_FREQ   I2C_CR2_FREQ_Msk

FREQ[5:0] bits (Peripheral Clock Frequency)

◆ I2C_CR2_FREQ_0

#define I2C_CR2_FREQ_0   (0x01U << I2C_CR2_FREQ_Pos)

0x00000001

◆ I2C_CR2_FREQ_1

#define I2C_CR2_FREQ_1   (0x02U << I2C_CR2_FREQ_Pos)

0x00000002

◆ I2C_CR2_FREQ_2

#define I2C_CR2_FREQ_2   (0x04U << I2C_CR2_FREQ_Pos)

0x00000004

◆ I2C_CR2_FREQ_3

#define I2C_CR2_FREQ_3   (0x08U << I2C_CR2_FREQ_Pos)

0x00000008

◆ I2C_CR2_FREQ_4

#define I2C_CR2_FREQ_4   (0x10U << I2C_CR2_FREQ_Pos)

0x00000010

◆ I2C_CR2_FREQ_5

#define I2C_CR2_FREQ_5   (0x20U << I2C_CR2_FREQ_Pos)

0x00000020

◆ I2C_CR2_FREQ_Msk

#define I2C_CR2_FREQ_Msk   (0x3FU << I2C_CR2_FREQ_Pos)

0x0000003F

◆ I2C_CR2_FREQ_Pos

#define I2C_CR2_FREQ_Pos   (0U)

◆ I2C_CR2_ITBUFEN

#define I2C_CR2_ITBUFEN   I2C_CR2_ITBUFEN_Msk

Buffer Interrupt Enable

◆ I2C_CR2_ITBUFEN_Msk

#define I2C_CR2_ITBUFEN_Msk   (0x1U << I2C_CR2_ITBUFEN_Pos)

0x00000400

◆ I2C_CR2_ITBUFEN_Pos

#define I2C_CR2_ITBUFEN_Pos   (10U)

◆ I2C_CR2_ITERREN

#define I2C_CR2_ITERREN   I2C_CR2_ITERREN_Msk

Error Interrupt Enable

◆ I2C_CR2_ITERREN_Msk

#define I2C_CR2_ITERREN_Msk   (0x1U << I2C_CR2_ITERREN_Pos)

0x00000100

◆ I2C_CR2_ITERREN_Pos

#define I2C_CR2_ITERREN_Pos   (8U)

◆ I2C_CR2_ITEVTEN

#define I2C_CR2_ITEVTEN   I2C_CR2_ITEVTEN_Msk

Event Interrupt Enable

◆ I2C_CR2_ITEVTEN_Msk

#define I2C_CR2_ITEVTEN_Msk   (0x1U << I2C_CR2_ITEVTEN_Pos)

0x00000200

◆ I2C_CR2_ITEVTEN_Pos

#define I2C_CR2_ITEVTEN_Pos   (9U)

◆ I2C_CR2_LAST

#define I2C_CR2_LAST   I2C_CR2_LAST_Msk

DMA Last Transfer

◆ I2C_CR2_LAST_Msk

#define I2C_CR2_LAST_Msk   (0x1U << I2C_CR2_LAST_Pos)

0x00001000

◆ I2C_CR2_LAST_Pos

#define I2C_CR2_LAST_Pos   (12U)

◆ I2C_DR_DR

#define I2C_DR_DR   I2C_DR_DR_Msk

8-bit Data Register

◆ I2C_DR_DR_Msk

#define I2C_DR_DR_Msk   (0xFFU << I2C_DR_DR_Pos)

0x000000FF

◆ I2C_DR_DR_Pos

#define I2C_DR_DR_Pos   (0U)

◆ I2C_OAR1_ADD0

#define I2C_OAR1_ADD0   I2C_OAR1_ADD0_Msk

Bit 0

◆ I2C_OAR1_ADD0_Msk

#define I2C_OAR1_ADD0_Msk   (0x1U << I2C_OAR1_ADD0_Pos)

0x00000001

◆ I2C_OAR1_ADD0_Pos

#define I2C_OAR1_ADD0_Pos   (0U)

◆ I2C_OAR1_ADD1

#define I2C_OAR1_ADD1   I2C_OAR1_ADD1_Msk

Bit 1

◆ I2C_OAR1_ADD1_7

#define I2C_OAR1_ADD1_7   (0x000000FEU)

Interface Address

◆ I2C_OAR1_ADD1_Msk

#define I2C_OAR1_ADD1_Msk   (0x1U << I2C_OAR1_ADD1_Pos)

0x00000002

◆ I2C_OAR1_ADD1_Pos

#define I2C_OAR1_ADD1_Pos   (1U)

◆ I2C_OAR1_ADD2

#define I2C_OAR1_ADD2   I2C_OAR1_ADD2_Msk

Bit 2

◆ I2C_OAR1_ADD2_Msk

#define I2C_OAR1_ADD2_Msk   (0x1U << I2C_OAR1_ADD2_Pos)

0x00000004

◆ I2C_OAR1_ADD2_Pos

#define I2C_OAR1_ADD2_Pos   (2U)

◆ I2C_OAR1_ADD3

#define I2C_OAR1_ADD3   I2C_OAR1_ADD3_Msk

Bit 3

◆ I2C_OAR1_ADD3_Msk

#define I2C_OAR1_ADD3_Msk   (0x1U << I2C_OAR1_ADD3_Pos)

0x00000008

◆ I2C_OAR1_ADD3_Pos

#define I2C_OAR1_ADD3_Pos   (3U)

◆ I2C_OAR1_ADD4

#define I2C_OAR1_ADD4   I2C_OAR1_ADD4_Msk

Bit 4

◆ I2C_OAR1_ADD4_Msk

#define I2C_OAR1_ADD4_Msk   (0x1U << I2C_OAR1_ADD4_Pos)

0x00000010

◆ I2C_OAR1_ADD4_Pos

#define I2C_OAR1_ADD4_Pos   (4U)

◆ I2C_OAR1_ADD5

#define I2C_OAR1_ADD5   I2C_OAR1_ADD5_Msk

Bit 5

◆ I2C_OAR1_ADD5_Msk

#define I2C_OAR1_ADD5_Msk   (0x1U << I2C_OAR1_ADD5_Pos)

0x00000020

◆ I2C_OAR1_ADD5_Pos

#define I2C_OAR1_ADD5_Pos   (5U)

◆ I2C_OAR1_ADD6

#define I2C_OAR1_ADD6   I2C_OAR1_ADD6_Msk

Bit 6

◆ I2C_OAR1_ADD6_Msk

#define I2C_OAR1_ADD6_Msk   (0x1U << I2C_OAR1_ADD6_Pos)

0x00000040

◆ I2C_OAR1_ADD6_Pos

#define I2C_OAR1_ADD6_Pos   (6U)

◆ I2C_OAR1_ADD7

#define I2C_OAR1_ADD7   I2C_OAR1_ADD7_Msk

Bit 7

◆ I2C_OAR1_ADD7_Msk

#define I2C_OAR1_ADD7_Msk   (0x1U << I2C_OAR1_ADD7_Pos)

0x00000080

◆ I2C_OAR1_ADD7_Pos

#define I2C_OAR1_ADD7_Pos   (7U)

◆ I2C_OAR1_ADD8

#define I2C_OAR1_ADD8   I2C_OAR1_ADD8_Msk

Bit 8

◆ I2C_OAR1_ADD8_9

#define I2C_OAR1_ADD8_9   (0x00000300U)

Interface Address

◆ I2C_OAR1_ADD8_Msk

#define I2C_OAR1_ADD8_Msk   (0x1U << I2C_OAR1_ADD8_Pos)

0x00000100

◆ I2C_OAR1_ADD8_Pos

#define I2C_OAR1_ADD8_Pos   (8U)

◆ I2C_OAR1_ADD9

#define I2C_OAR1_ADD9   I2C_OAR1_ADD9_Msk

Bit 9

◆ I2C_OAR1_ADD9_Msk

#define I2C_OAR1_ADD9_Msk   (0x1U << I2C_OAR1_ADD9_Pos)

0x00000200

◆ I2C_OAR1_ADD9_Pos

#define I2C_OAR1_ADD9_Pos   (9U)

◆ I2C_OAR1_ADDMODE

#define I2C_OAR1_ADDMODE   I2C_OAR1_ADDMODE_Msk

Addressing Mode (Slave mode)

◆ I2C_OAR1_ADDMODE_Msk

#define I2C_OAR1_ADDMODE_Msk   (0x1U << I2C_OAR1_ADDMODE_Pos)

0x00008000

◆ I2C_OAR1_ADDMODE_Pos

#define I2C_OAR1_ADDMODE_Pos   (15U)

◆ I2C_OAR2_ADD2

#define I2C_OAR2_ADD2   I2C_OAR2_ADD2_Msk

Interface address

◆ I2C_OAR2_ADD2_Msk

#define I2C_OAR2_ADD2_Msk   (0x7FU << I2C_OAR2_ADD2_Pos)

0x000000FE

◆ I2C_OAR2_ADD2_Pos

#define I2C_OAR2_ADD2_Pos   (1U)

◆ I2C_OAR2_ENDUAL

#define I2C_OAR2_ENDUAL   I2C_OAR2_ENDUAL_Msk

Dual addressing mode enable

◆ I2C_OAR2_ENDUAL_Msk

#define I2C_OAR2_ENDUAL_Msk   (0x1U << I2C_OAR2_ENDUAL_Pos)

0x00000001

◆ I2C_OAR2_ENDUAL_Pos

#define I2C_OAR2_ENDUAL_Pos   (0U)

◆ I2C_SR1_ADD10

#define I2C_SR1_ADD10   I2C_SR1_ADD10_Msk

10-bit header sent (Master mode)

◆ I2C_SR1_ADD10_Msk

#define I2C_SR1_ADD10_Msk   (0x1U << I2C_SR1_ADD10_Pos)

0x00000008

◆ I2C_SR1_ADD10_Pos

#define I2C_SR1_ADD10_Pos   (3U)

◆ I2C_SR1_ADDR

#define I2C_SR1_ADDR   I2C_SR1_ADDR_Msk

Address sent (master mode)/matched (slave mode)

◆ I2C_SR1_ADDR_Msk

#define I2C_SR1_ADDR_Msk   (0x1U << I2C_SR1_ADDR_Pos)

0x00000002

◆ I2C_SR1_ADDR_Pos

#define I2C_SR1_ADDR_Pos   (1U)

◆ I2C_SR1_AF

#define I2C_SR1_AF   I2C_SR1_AF_Msk

Acknowledge Failure

◆ I2C_SR1_AF_Msk

#define I2C_SR1_AF_Msk   (0x1U << I2C_SR1_AF_Pos)

0x00000400

◆ I2C_SR1_AF_Pos

#define I2C_SR1_AF_Pos   (10U)

◆ I2C_SR1_ARLO

#define I2C_SR1_ARLO   I2C_SR1_ARLO_Msk

Arbitration Lost (master mode)

◆ I2C_SR1_ARLO_Msk

#define I2C_SR1_ARLO_Msk   (0x1U << I2C_SR1_ARLO_Pos)

0x00000200

◆ I2C_SR1_ARLO_Pos

#define I2C_SR1_ARLO_Pos   (9U)

◆ I2C_SR1_BERR

#define I2C_SR1_BERR   I2C_SR1_BERR_Msk

Bus Error

◆ I2C_SR1_BERR_Msk

#define I2C_SR1_BERR_Msk   (0x1U << I2C_SR1_BERR_Pos)

0x00000100

◆ I2C_SR1_BERR_Pos

#define I2C_SR1_BERR_Pos   (8U)

◆ I2C_SR1_BTF

#define I2C_SR1_BTF   I2C_SR1_BTF_Msk

Byte Transfer Finished

◆ I2C_SR1_BTF_Msk

#define I2C_SR1_BTF_Msk   (0x1U << I2C_SR1_BTF_Pos)

0x00000004

◆ I2C_SR1_BTF_Pos

#define I2C_SR1_BTF_Pos   (2U)

◆ I2C_SR1_OVR

#define I2C_SR1_OVR   I2C_SR1_OVR_Msk

Overrun/Underrun

◆ I2C_SR1_OVR_Msk

#define I2C_SR1_OVR_Msk   (0x1U << I2C_SR1_OVR_Pos)

0x00000800

◆ I2C_SR1_OVR_Pos

#define I2C_SR1_OVR_Pos   (11U)

◆ I2C_SR1_PECERR

#define I2C_SR1_PECERR   I2C_SR1_PECERR_Msk

PEC Error in reception

◆ I2C_SR1_PECERR_Msk

#define I2C_SR1_PECERR_Msk   (0x1U << I2C_SR1_PECERR_Pos)

0x00001000

◆ I2C_SR1_PECERR_Pos

#define I2C_SR1_PECERR_Pos   (12U)

◆ I2C_SR1_RXNE

#define I2C_SR1_RXNE   I2C_SR1_RXNE_Msk

Data Register not Empty (receivers)

◆ I2C_SR1_RXNE_Msk

#define I2C_SR1_RXNE_Msk   (0x1U << I2C_SR1_RXNE_Pos)

0x00000040

◆ I2C_SR1_RXNE_Pos

#define I2C_SR1_RXNE_Pos   (6U)

◆ I2C_SR1_SB

#define I2C_SR1_SB   I2C_SR1_SB_Msk

Start Bit (Master mode)

◆ I2C_SR1_SB_Msk

#define I2C_SR1_SB_Msk   (0x1U << I2C_SR1_SB_Pos)

0x00000001

◆ I2C_SR1_SB_Pos

#define I2C_SR1_SB_Pos   (0U)

◆ I2C_SR1_SMBALERT

#define I2C_SR1_SMBALERT   I2C_SR1_SMBALERT_Msk

SMBus Alert

◆ I2C_SR1_SMBALERT_Msk

#define I2C_SR1_SMBALERT_Msk   (0x1U << I2C_SR1_SMBALERT_Pos)

0x00008000

◆ I2C_SR1_SMBALERT_Pos

#define I2C_SR1_SMBALERT_Pos   (15U)

◆ I2C_SR1_STOPF

#define I2C_SR1_STOPF   I2C_SR1_STOPF_Msk

Stop detection (Slave mode)

◆ I2C_SR1_STOPF_Msk

#define I2C_SR1_STOPF_Msk   (0x1U << I2C_SR1_STOPF_Pos)

0x00000010

◆ I2C_SR1_STOPF_Pos

#define I2C_SR1_STOPF_Pos   (4U)

◆ I2C_SR1_TIMEOUT

#define I2C_SR1_TIMEOUT   I2C_SR1_TIMEOUT_Msk

Timeout or Tlow Error

◆ I2C_SR1_TIMEOUT_Msk

#define I2C_SR1_TIMEOUT_Msk   (0x1U << I2C_SR1_TIMEOUT_Pos)

0x00004000

◆ I2C_SR1_TIMEOUT_Pos

#define I2C_SR1_TIMEOUT_Pos   (14U)

◆ I2C_SR1_TXE

#define I2C_SR1_TXE   I2C_SR1_TXE_Msk

Data Register Empty (transmitters)

◆ I2C_SR1_TXE_Msk

#define I2C_SR1_TXE_Msk   (0x1U << I2C_SR1_TXE_Pos)

0x00000080

◆ I2C_SR1_TXE_Pos

#define I2C_SR1_TXE_Pos   (7U)

◆ I2C_SR2_BUSY

#define I2C_SR2_BUSY   I2C_SR2_BUSY_Msk

Bus Busy

◆ I2C_SR2_BUSY_Msk

#define I2C_SR2_BUSY_Msk   (0x1U << I2C_SR2_BUSY_Pos)

0x00000002

◆ I2C_SR2_BUSY_Pos

#define I2C_SR2_BUSY_Pos   (1U)

◆ I2C_SR2_DUALF

#define I2C_SR2_DUALF   I2C_SR2_DUALF_Msk

Dual Flag (Slave mode)

◆ I2C_SR2_DUALF_Msk

#define I2C_SR2_DUALF_Msk   (0x1U << I2C_SR2_DUALF_Pos)

0x00000080

◆ I2C_SR2_DUALF_Pos

#define I2C_SR2_DUALF_Pos   (7U)

◆ I2C_SR2_GENCALL

#define I2C_SR2_GENCALL   I2C_SR2_GENCALL_Msk

General Call Address (Slave mode)

◆ I2C_SR2_GENCALL_Msk

#define I2C_SR2_GENCALL_Msk   (0x1U << I2C_SR2_GENCALL_Pos)

0x00000010

◆ I2C_SR2_GENCALL_Pos

#define I2C_SR2_GENCALL_Pos   (4U)

◆ I2C_SR2_MSL

#define I2C_SR2_MSL   I2C_SR2_MSL_Msk

Master/Slave

◆ I2C_SR2_MSL_Msk

#define I2C_SR2_MSL_Msk   (0x1U << I2C_SR2_MSL_Pos)

0x00000001

◆ I2C_SR2_MSL_Pos

#define I2C_SR2_MSL_Pos   (0U)

◆ I2C_SR2_PEC

#define I2C_SR2_PEC   I2C_SR2_PEC_Msk

Packet Error Checking Register

◆ I2C_SR2_PEC_Msk

#define I2C_SR2_PEC_Msk   (0xFFU << I2C_SR2_PEC_Pos)

0x0000FF00

◆ I2C_SR2_PEC_Pos

#define I2C_SR2_PEC_Pos   (8U)

◆ I2C_SR2_SMBDEFAULT

#define I2C_SR2_SMBDEFAULT   I2C_SR2_SMBDEFAULT_Msk

SMBus Device Default Address (Slave mode)

◆ I2C_SR2_SMBDEFAULT_Msk

#define I2C_SR2_SMBDEFAULT_Msk   (0x1U << I2C_SR2_SMBDEFAULT_Pos)

0x00000020

◆ I2C_SR2_SMBDEFAULT_Pos

#define I2C_SR2_SMBDEFAULT_Pos   (5U)

◆ I2C_SR2_SMBHOST

#define I2C_SR2_SMBHOST   I2C_SR2_SMBHOST_Msk

SMBus Host Header (Slave mode)

◆ I2C_SR2_SMBHOST_Msk

#define I2C_SR2_SMBHOST_Msk   (0x1U << I2C_SR2_SMBHOST_Pos)

0x00000040

◆ I2C_SR2_SMBHOST_Pos

#define I2C_SR2_SMBHOST_Pos   (6U)

◆ I2C_SR2_TRA

#define I2C_SR2_TRA   I2C_SR2_TRA_Msk

Transmitter/Receiver

◆ I2C_SR2_TRA_Msk

#define I2C_SR2_TRA_Msk   (0x1U << I2C_SR2_TRA_Pos)

0x00000004

◆ I2C_SR2_TRA_Pos

#define I2C_SR2_TRA_Pos   (2U)

◆ I2C_TRISE_TRISE

#define I2C_TRISE_TRISE   I2C_TRISE_TRISE_Msk

Maximum Rise Time in Fast/Standard mode (Master mode)

◆ I2C_TRISE_TRISE_Msk

#define I2C_TRISE_TRISE_Msk   (0x3FU << I2C_TRISE_TRISE_Pos)

0x0000003F

◆ I2C_TRISE_TRISE_Pos

#define I2C_TRISE_TRISE_Pos   (0U)

◆ IWDG_KR_KEY

#define IWDG_KR_KEY   IWDG_KR_KEY_Msk

Key value (write only, read 0000h)

◆ IWDG_KR_KEY_Msk

#define IWDG_KR_KEY_Msk   (0xFFFFU << IWDG_KR_KEY_Pos)

0x0000FFFF

◆ IWDG_KR_KEY_Pos

#define IWDG_KR_KEY_Pos   (0U)

◆ IWDG_PR_PR

#define IWDG_PR_PR   IWDG_PR_PR_Msk

PR[2:0] (Prescaler divider)

◆ IWDG_PR_PR_0

#define IWDG_PR_PR_0   (0x1U << IWDG_PR_PR_Pos)

0x00000001

◆ IWDG_PR_PR_1

#define IWDG_PR_PR_1   (0x2U << IWDG_PR_PR_Pos)

0x00000002

◆ IWDG_PR_PR_2

#define IWDG_PR_PR_2   (0x4U << IWDG_PR_PR_Pos)

0x00000004

◆ IWDG_PR_PR_Msk

#define IWDG_PR_PR_Msk   (0x7U << IWDG_PR_PR_Pos)

0x00000007

◆ IWDG_PR_PR_Pos

#define IWDG_PR_PR_Pos   (0U)

◆ IWDG_RLR_RL

#define IWDG_RLR_RL   IWDG_RLR_RL_Msk

Watchdog counter reload value

◆ IWDG_RLR_RL_Msk

#define IWDG_RLR_RL_Msk   (0xFFFU << IWDG_RLR_RL_Pos)

0x00000FFF

◆ IWDG_RLR_RL_Pos

#define IWDG_RLR_RL_Pos   (0U)

◆ IWDG_SR_PVU

#define IWDG_SR_PVU   IWDG_SR_PVU_Msk

Watchdog prescaler value update

◆ IWDG_SR_PVU_Msk

#define IWDG_SR_PVU_Msk   (0x1U << IWDG_SR_PVU_Pos)

0x00000001

◆ IWDG_SR_PVU_Pos

#define IWDG_SR_PVU_Pos   (0U)

◆ IWDG_SR_RVU

#define IWDG_SR_RVU   IWDG_SR_RVU_Msk

Watchdog counter reload value update

◆ IWDG_SR_RVU_Msk

#define IWDG_SR_RVU_Msk   (0x1U << IWDG_SR_RVU_Pos)

0x00000002

◆ IWDG_SR_RVU_Pos

#define IWDG_SR_RVU_Pos   (1U)

◆ LCD_CLR_SOFC

#define LCD_CLR_SOFC   LCD_CLR_SOFC_Msk

Start Of Frame Flag Clear Bit

◆ LCD_CLR_SOFC_Msk

#define LCD_CLR_SOFC_Msk   (0x1U << LCD_CLR_SOFC_Pos)

0x00000002

◆ LCD_CLR_SOFC_Pos

#define LCD_CLR_SOFC_Pos   (1U)

◆ LCD_CLR_UDDC

#define LCD_CLR_UDDC   LCD_CLR_UDDC_Msk

Update Display Done Flag Clear Bit

◆ LCD_CLR_UDDC_Msk

#define LCD_CLR_UDDC_Msk   (0x1U << LCD_CLR_UDDC_Pos)

0x00000008

◆ LCD_CLR_UDDC_Pos

#define LCD_CLR_UDDC_Pos   (3U)

◆ LCD_CR_BIAS

#define LCD_CR_BIAS   LCD_CR_BIAS_Msk

BIAS[1:0] bits (Bias selector)

◆ LCD_CR_BIAS_0

#define LCD_CR_BIAS_0   (0x1U << LCD_CR_BIAS_Pos)

0x00000020

◆ LCD_CR_BIAS_1

#define LCD_CR_BIAS_1   (0x2U << LCD_CR_BIAS_Pos)

0x00000040

◆ LCD_CR_BIAS_Msk

#define LCD_CR_BIAS_Msk   (0x3U << LCD_CR_BIAS_Pos)

0x00000060

◆ LCD_CR_BIAS_Pos

#define LCD_CR_BIAS_Pos   (5U)

◆ LCD_CR_DUTY

#define LCD_CR_DUTY   LCD_CR_DUTY_Msk

DUTY[2:0] bits (Duty selector)

◆ LCD_CR_DUTY_0

#define LCD_CR_DUTY_0   (0x1U << LCD_CR_DUTY_Pos)

0x00000004

◆ LCD_CR_DUTY_1

#define LCD_CR_DUTY_1   (0x2U << LCD_CR_DUTY_Pos)

0x00000008

◆ LCD_CR_DUTY_2

#define LCD_CR_DUTY_2   (0x4U << LCD_CR_DUTY_Pos)

0x00000010

◆ LCD_CR_DUTY_Msk

#define LCD_CR_DUTY_Msk   (0x7U << LCD_CR_DUTY_Pos)

0x0000001C

◆ LCD_CR_DUTY_Pos

#define LCD_CR_DUTY_Pos   (2U)

◆ LCD_CR_LCDEN

#define LCD_CR_LCDEN   LCD_CR_LCDEN_Msk

LCD Enable Bit

◆ LCD_CR_LCDEN_Msk

#define LCD_CR_LCDEN_Msk   (0x1U << LCD_CR_LCDEN_Pos)

0x00000001

◆ LCD_CR_LCDEN_Pos

#define LCD_CR_LCDEN_Pos   (0U)

◆ LCD_CR_MUX_SEG

#define LCD_CR_MUX_SEG   LCD_CR_MUX_SEG_Msk

Mux Segment Enable Bit

◆ LCD_CR_MUX_SEG_Msk

#define LCD_CR_MUX_SEG_Msk   (0x1U << LCD_CR_MUX_SEG_Pos)

0x00000080

◆ LCD_CR_MUX_SEG_Pos

#define LCD_CR_MUX_SEG_Pos   (7U)

◆ LCD_CR_VSEL

#define LCD_CR_VSEL   LCD_CR_VSEL_Msk

Voltage source selector Bit

◆ LCD_CR_VSEL_Msk

#define LCD_CR_VSEL_Msk   (0x1U << LCD_CR_VSEL_Pos)

0x00000002

◆ LCD_CR_VSEL_Pos

#define LCD_CR_VSEL_Pos   (1U)

◆ LCD_FCR_BLINK

#define LCD_FCR_BLINK   LCD_FCR_BLINK_Msk

BLINK[1:0] bits (Blink Enable)

◆ LCD_FCR_BLINK_0

#define LCD_FCR_BLINK_0   (0x1U << LCD_FCR_BLINK_Pos)

0x00010000

◆ LCD_FCR_BLINK_1

#define LCD_FCR_BLINK_1   (0x2U << LCD_FCR_BLINK_Pos)

0x00020000

◆ LCD_FCR_BLINK_Msk

#define LCD_FCR_BLINK_Msk   (0x3U << LCD_FCR_BLINK_Pos)

0x00030000

◆ LCD_FCR_BLINK_Pos

#define LCD_FCR_BLINK_Pos   (16U)

◆ LCD_FCR_BLINKF

#define LCD_FCR_BLINKF   LCD_FCR_BLINKF_Msk

BLINKF[2:0] bits (Blink Frequency)

◆ LCD_FCR_BLINKF_0

#define LCD_FCR_BLINKF_0   (0x1U << LCD_FCR_BLINKF_Pos)

0x00002000

◆ LCD_FCR_BLINKF_1

#define LCD_FCR_BLINKF_1   (0x2U << LCD_FCR_BLINKF_Pos)

0x00004000

◆ LCD_FCR_BLINKF_2

#define LCD_FCR_BLINKF_2   (0x4U << LCD_FCR_BLINKF_Pos)

0x00008000

◆ LCD_FCR_BLINKF_Msk

#define LCD_FCR_BLINKF_Msk   (0x7U << LCD_FCR_BLINKF_Pos)

0x0000E000

◆ LCD_FCR_BLINKF_Pos

#define LCD_FCR_BLINKF_Pos   (13U)

◆ LCD_FCR_CC

#define LCD_FCR_CC   LCD_FCR_CC_Msk

CC[2:0] bits (Contrast Control)

◆ LCD_FCR_CC_0

#define LCD_FCR_CC_0   (0x1U << LCD_FCR_CC_Pos)

0x00000400

◆ LCD_FCR_CC_1

#define LCD_FCR_CC_1   (0x2U << LCD_FCR_CC_Pos)

0x00000800

◆ LCD_FCR_CC_2

#define LCD_FCR_CC_2   (0x4U << LCD_FCR_CC_Pos)

0x00001000

◆ LCD_FCR_CC_Msk

#define LCD_FCR_CC_Msk   (0x7U << LCD_FCR_CC_Pos)

0x00001C00

◆ LCD_FCR_CC_Pos

#define LCD_FCR_CC_Pos   (10U)

◆ LCD_FCR_DEAD

#define LCD_FCR_DEAD   LCD_FCR_DEAD_Msk

DEAD[2:0] bits (DEAD Time)

◆ LCD_FCR_DEAD_0

#define LCD_FCR_DEAD_0   (0x1U << LCD_FCR_DEAD_Pos)

0x00000080

◆ LCD_FCR_DEAD_1

#define LCD_FCR_DEAD_1   (0x2U << LCD_FCR_DEAD_Pos)

0x00000100

◆ LCD_FCR_DEAD_2

#define LCD_FCR_DEAD_2   (0x4U << LCD_FCR_DEAD_Pos)

0x00000200

◆ LCD_FCR_DEAD_Msk

#define LCD_FCR_DEAD_Msk   (0x7U << LCD_FCR_DEAD_Pos)

0x00000380

◆ LCD_FCR_DEAD_Pos

#define LCD_FCR_DEAD_Pos   (7U)

◆ LCD_FCR_DIV

#define LCD_FCR_DIV   LCD_FCR_DIV_Msk

DIV[3:0] bits (Divider)

◆ LCD_FCR_DIV_Msk

#define LCD_FCR_DIV_Msk   (0xFU << LCD_FCR_DIV_Pos)

0x003C0000

◆ LCD_FCR_DIV_Pos

#define LCD_FCR_DIV_Pos   (18U)

◆ LCD_FCR_HD

#define LCD_FCR_HD   LCD_FCR_HD_Msk

High Drive Enable Bit

◆ LCD_FCR_HD_Msk

#define LCD_FCR_HD_Msk   (0x1U << LCD_FCR_HD_Pos)

0x00000001

◆ LCD_FCR_HD_Pos

#define LCD_FCR_HD_Pos   (0U)

◆ LCD_FCR_PON

#define LCD_FCR_PON   LCD_FCR_PON_Msk

PON[2:0] bits (Puls ON Duration)

◆ LCD_FCR_PON_0

#define LCD_FCR_PON_0   (0x1U << LCD_FCR_PON_Pos)

0x00000010

◆ LCD_FCR_PON_1

#define LCD_FCR_PON_1   (0x2U << LCD_FCR_PON_Pos)

0x00000020

◆ LCD_FCR_PON_2

#define LCD_FCR_PON_2   (0x4U << LCD_FCR_PON_Pos)

0x00000040

◆ LCD_FCR_PON_Msk

#define LCD_FCR_PON_Msk   (0x7U << LCD_FCR_PON_Pos)

0x00000070

◆ LCD_FCR_PON_Pos

#define LCD_FCR_PON_Pos   (4U)

◆ LCD_FCR_PS

#define LCD_FCR_PS   LCD_FCR_PS_Msk

PS[3:0] bits (Prescaler)

◆ LCD_FCR_PS_Msk

#define LCD_FCR_PS_Msk   (0xFU << LCD_FCR_PS_Pos)

0x03C00000

◆ LCD_FCR_PS_Pos

#define LCD_FCR_PS_Pos   (22U)

◆ LCD_FCR_SOFIE

#define LCD_FCR_SOFIE   LCD_FCR_SOFIE_Msk

Start of Frame Interrupt Enable Bit

◆ LCD_FCR_SOFIE_Msk

#define LCD_FCR_SOFIE_Msk   (0x1U << LCD_FCR_SOFIE_Pos)

0x00000002

◆ LCD_FCR_SOFIE_Pos

#define LCD_FCR_SOFIE_Pos   (1U)

◆ LCD_FCR_UDDIE

#define LCD_FCR_UDDIE   LCD_FCR_UDDIE_Msk

Update Display Done Interrupt Enable Bit

◆ LCD_FCR_UDDIE_Msk

#define LCD_FCR_UDDIE_Msk   (0x1U << LCD_FCR_UDDIE_Pos)

0x00000008

◆ LCD_FCR_UDDIE_Pos

#define LCD_FCR_UDDIE_Pos   (3U)

◆ LCD_RAM_SEGMENT_DATA

#define LCD_RAM_SEGMENT_DATA   LCD_RAM_SEGMENT_DATA_Msk

Segment Data Bits

◆ LCD_RAM_SEGMENT_DATA_Msk

#define LCD_RAM_SEGMENT_DATA_Msk   (0xFFFFFFFFU << LCD_RAM_SEGMENT_DATA_Pos)

0xFFFFFFFF

◆ LCD_RAM_SEGMENT_DATA_Pos

#define LCD_RAM_SEGMENT_DATA_Pos   (0U)

◆ LCD_SR_ENS

#define LCD_SR_ENS   LCD_SR_ENS_Msk

LCD Enabled Bit

◆ LCD_SR_ENS_Msk

#define LCD_SR_ENS_Msk   (0x1U << LCD_SR_ENS_Pos)

0x00000001

◆ LCD_SR_ENS_Pos

#define LCD_SR_ENS_Pos   (0U)

◆ LCD_SR_FCRSR

#define LCD_SR_FCRSR   LCD_SR_FCRSR_Msk

LCD FCR Register Synchronization Flag Bit

◆ LCD_SR_FCRSR_Msk

#define LCD_SR_FCRSR_Msk   (0x1U << LCD_SR_FCRSR_Pos)

0x00000020

◆ LCD_SR_FCRSR_Pos

#define LCD_SR_FCRSR_Pos   (5U)

◆ LCD_SR_RDY

#define LCD_SR_RDY   LCD_SR_RDY_Msk

Ready Flag Bit

◆ LCD_SR_RDY_Msk

#define LCD_SR_RDY_Msk   (0x1U << LCD_SR_RDY_Pos)

0x00000010

◆ LCD_SR_RDY_Pos

#define LCD_SR_RDY_Pos   (4U)

◆ LCD_SR_SOF

#define LCD_SR_SOF   LCD_SR_SOF_Msk

Start Of Frame Flag Bit

◆ LCD_SR_SOF_Msk

#define LCD_SR_SOF_Msk   (0x1U << LCD_SR_SOF_Pos)

0x00000002

◆ LCD_SR_SOF_Pos

#define LCD_SR_SOF_Pos   (1U)

◆ LCD_SR_UDD

#define LCD_SR_UDD   LCD_SR_UDD_Msk

Update Display Done Flag Bit

◆ LCD_SR_UDD_Msk

#define LCD_SR_UDD_Msk   (0x1U << LCD_SR_UDD_Pos)

0x00000008

◆ LCD_SR_UDD_Pos

#define LCD_SR_UDD_Pos   (3U)

◆ LCD_SR_UDR

#define LCD_SR_UDR   LCD_SR_UDR_Msk

Update Display Request Bit

◆ LCD_SR_UDR_Msk

#define LCD_SR_UDR_Msk   (0x1U << LCD_SR_UDR_Pos)

0x00000004

◆ LCD_SR_UDR_Pos

#define LCD_SR_UDR_Pos   (2U)

◆ NVIC_IABR_ACTIVE

#define NVIC_IABR_ACTIVE   NVIC_IABR_ACTIVE_Msk

Interrupt active flags

◆ NVIC_IABR_ACTIVE_0

#define NVIC_IABR_ACTIVE_0   (0x00000001U << NVIC_IABR_ACTIVE_Pos)

0x00000001

◆ NVIC_IABR_ACTIVE_1

#define NVIC_IABR_ACTIVE_1   (0x00000002U << NVIC_IABR_ACTIVE_Pos)

0x00000002

◆ NVIC_IABR_ACTIVE_10

#define NVIC_IABR_ACTIVE_10   (0x00000400U << NVIC_IABR_ACTIVE_Pos)

0x00000400

◆ NVIC_IABR_ACTIVE_11

#define NVIC_IABR_ACTIVE_11   (0x00000800U << NVIC_IABR_ACTIVE_Pos)

0x00000800

◆ NVIC_IABR_ACTIVE_12

#define NVIC_IABR_ACTIVE_12   (0x00001000U << NVIC_IABR_ACTIVE_Pos)

0x00001000

◆ NVIC_IABR_ACTIVE_13

#define NVIC_IABR_ACTIVE_13   (0x00002000U << NVIC_IABR_ACTIVE_Pos)

0x00002000

◆ NVIC_IABR_ACTIVE_14

#define NVIC_IABR_ACTIVE_14   (0x00004000U << NVIC_IABR_ACTIVE_Pos)

0x00004000

◆ NVIC_IABR_ACTIVE_15

#define NVIC_IABR_ACTIVE_15   (0x00008000U << NVIC_IABR_ACTIVE_Pos)

0x00008000

◆ NVIC_IABR_ACTIVE_16

#define NVIC_IABR_ACTIVE_16   (0x00010000U << NVIC_IABR_ACTIVE_Pos)

0x00010000

◆ NVIC_IABR_ACTIVE_17

#define NVIC_IABR_ACTIVE_17   (0x00020000U << NVIC_IABR_ACTIVE_Pos)

0x00020000

◆ NVIC_IABR_ACTIVE_18

#define NVIC_IABR_ACTIVE_18   (0x00040000U << NVIC_IABR_ACTIVE_Pos)

0x00040000

◆ NVIC_IABR_ACTIVE_19

#define NVIC_IABR_ACTIVE_19   (0x00080000U << NVIC_IABR_ACTIVE_Pos)

0x00080000

◆ NVIC_IABR_ACTIVE_2

#define NVIC_IABR_ACTIVE_2   (0x00000004U << NVIC_IABR_ACTIVE_Pos)

0x00000004

◆ NVIC_IABR_ACTIVE_20

#define NVIC_IABR_ACTIVE_20   (0x00100000U << NVIC_IABR_ACTIVE_Pos)

0x00100000

◆ NVIC_IABR_ACTIVE_21

#define NVIC_IABR_ACTIVE_21   (0x00200000U << NVIC_IABR_ACTIVE_Pos)

0x00200000

◆ NVIC_IABR_ACTIVE_22

#define NVIC_IABR_ACTIVE_22   (0x00400000U << NVIC_IABR_ACTIVE_Pos)

0x00400000

◆ NVIC_IABR_ACTIVE_23

#define NVIC_IABR_ACTIVE_23   (0x00800000U << NVIC_IABR_ACTIVE_Pos)

0x00800000

◆ NVIC_IABR_ACTIVE_24

#define NVIC_IABR_ACTIVE_24   (0x01000000U << NVIC_IABR_ACTIVE_Pos)

0x01000000

◆ NVIC_IABR_ACTIVE_25

#define NVIC_IABR_ACTIVE_25   (0x02000000U << NVIC_IABR_ACTIVE_Pos)

0x02000000

◆ NVIC_IABR_ACTIVE_26

#define NVIC_IABR_ACTIVE_26   (0x04000000U << NVIC_IABR_ACTIVE_Pos)

0x04000000

◆ NVIC_IABR_ACTIVE_27

#define NVIC_IABR_ACTIVE_27   (0x08000000U << NVIC_IABR_ACTIVE_Pos)

0x08000000

◆ NVIC_IABR_ACTIVE_28

#define NVIC_IABR_ACTIVE_28   (0x10000000U << NVIC_IABR_ACTIVE_Pos)

0x10000000

◆ NVIC_IABR_ACTIVE_29

#define NVIC_IABR_ACTIVE_29   (0x20000000U << NVIC_IABR_ACTIVE_Pos)

0x20000000

◆ NVIC_IABR_ACTIVE_3

#define NVIC_IABR_ACTIVE_3   (0x00000008U << NVIC_IABR_ACTIVE_Pos)

0x00000008

◆ NVIC_IABR_ACTIVE_30

#define NVIC_IABR_ACTIVE_30   (0x40000000U << NVIC_IABR_ACTIVE_Pos)

0x40000000

◆ NVIC_IABR_ACTIVE_31

#define NVIC_IABR_ACTIVE_31   (0x80000000U << NVIC_IABR_ACTIVE_Pos)

0x80000000

◆ NVIC_IABR_ACTIVE_4

#define NVIC_IABR_ACTIVE_4   (0x00000010U << NVIC_IABR_ACTIVE_Pos)

0x00000010

◆ NVIC_IABR_ACTIVE_5

#define NVIC_IABR_ACTIVE_5   (0x00000020U << NVIC_IABR_ACTIVE_Pos)

0x00000020

◆ NVIC_IABR_ACTIVE_6

#define NVIC_IABR_ACTIVE_6   (0x00000040U << NVIC_IABR_ACTIVE_Pos)

0x00000040

◆ NVIC_IABR_ACTIVE_7

#define NVIC_IABR_ACTIVE_7   (0x00000080U << NVIC_IABR_ACTIVE_Pos)

0x00000080

◆ NVIC_IABR_ACTIVE_8

#define NVIC_IABR_ACTIVE_8   (0x00000100U << NVIC_IABR_ACTIVE_Pos)

0x00000100

◆ NVIC_IABR_ACTIVE_9

#define NVIC_IABR_ACTIVE_9   (0x00000200U << NVIC_IABR_ACTIVE_Pos)

0x00000200

◆ NVIC_IABR_ACTIVE_Msk

#define NVIC_IABR_ACTIVE_Msk   (0xFFFFFFFFU << NVIC_IABR_ACTIVE_Pos)

0xFFFFFFFF

◆ NVIC_IABR_ACTIVE_Pos

#define NVIC_IABR_ACTIVE_Pos   (0U)

◆ NVIC_ICER_CLRENA

#define NVIC_ICER_CLRENA   NVIC_ICER_CLRENA_Msk

Interrupt clear-enable bits

◆ NVIC_ICER_CLRENA_0

#define NVIC_ICER_CLRENA_0   (0x00000001U << NVIC_ICER_CLRENA_Pos)

0x00000001

◆ NVIC_ICER_CLRENA_1

#define NVIC_ICER_CLRENA_1   (0x00000002U << NVIC_ICER_CLRENA_Pos)

0x00000002

◆ NVIC_ICER_CLRENA_10

#define NVIC_ICER_CLRENA_10   (0x00000400U << NVIC_ICER_CLRENA_Pos)

0x00000400

◆ NVIC_ICER_CLRENA_11

#define NVIC_ICER_CLRENA_11   (0x00000800U << NVIC_ICER_CLRENA_Pos)

0x00000800

◆ NVIC_ICER_CLRENA_12

#define NVIC_ICER_CLRENA_12   (0x00001000U << NVIC_ICER_CLRENA_Pos)

0x00001000

◆ NVIC_ICER_CLRENA_13

#define NVIC_ICER_CLRENA_13   (0x00002000U << NVIC_ICER_CLRENA_Pos)

0x00002000

◆ NVIC_ICER_CLRENA_14

#define NVIC_ICER_CLRENA_14   (0x00004000U << NVIC_ICER_CLRENA_Pos)

0x00004000

◆ NVIC_ICER_CLRENA_15

#define NVIC_ICER_CLRENA_15   (0x00008000U << NVIC_ICER_CLRENA_Pos)

0x00008000

◆ NVIC_ICER_CLRENA_16

#define NVIC_ICER_CLRENA_16   (0x00010000U << NVIC_ICER_CLRENA_Pos)

0x00010000

◆ NVIC_ICER_CLRENA_17

#define NVIC_ICER_CLRENA_17   (0x00020000U << NVIC_ICER_CLRENA_Pos)

0x00020000

◆ NVIC_ICER_CLRENA_18

#define NVIC_ICER_CLRENA_18   (0x00040000U << NVIC_ICER_CLRENA_Pos)

0x00040000

◆ NVIC_ICER_CLRENA_19

#define NVIC_ICER_CLRENA_19   (0x00080000U << NVIC_ICER_CLRENA_Pos)

0x00080000

◆ NVIC_ICER_CLRENA_2

#define NVIC_ICER_CLRENA_2   (0x00000004U << NVIC_ICER_CLRENA_Pos)

0x00000004

◆ NVIC_ICER_CLRENA_20

#define NVIC_ICER_CLRENA_20   (0x00100000U << NVIC_ICER_CLRENA_Pos)

0x00100000

◆ NVIC_ICER_CLRENA_21

#define NVIC_ICER_CLRENA_21   (0x00200000U << NVIC_ICER_CLRENA_Pos)

0x00200000

◆ NVIC_ICER_CLRENA_22

#define NVIC_ICER_CLRENA_22   (0x00400000U << NVIC_ICER_CLRENA_Pos)

0x00400000

◆ NVIC_ICER_CLRENA_23

#define NVIC_ICER_CLRENA_23   (0x00800000U << NVIC_ICER_CLRENA_Pos)

0x00800000

◆ NVIC_ICER_CLRENA_24

#define NVIC_ICER_CLRENA_24   (0x01000000U << NVIC_ICER_CLRENA_Pos)

0x01000000

◆ NVIC_ICER_CLRENA_25

#define NVIC_ICER_CLRENA_25   (0x02000000U << NVIC_ICER_CLRENA_Pos)

0x02000000

◆ NVIC_ICER_CLRENA_26

#define NVIC_ICER_CLRENA_26   (0x04000000U << NVIC_ICER_CLRENA_Pos)

0x04000000

◆ NVIC_ICER_CLRENA_27

#define NVIC_ICER_CLRENA_27   (0x08000000U << NVIC_ICER_CLRENA_Pos)

0x08000000

◆ NVIC_ICER_CLRENA_28

#define NVIC_ICER_CLRENA_28   (0x10000000U << NVIC_ICER_CLRENA_Pos)

0x10000000

◆ NVIC_ICER_CLRENA_29

#define NVIC_ICER_CLRENA_29   (0x20000000U << NVIC_ICER_CLRENA_Pos)

0x20000000

◆ NVIC_ICER_CLRENA_3

#define NVIC_ICER_CLRENA_3   (0x00000008U << NVIC_ICER_CLRENA_Pos)

0x00000008

◆ NVIC_ICER_CLRENA_30

#define NVIC_ICER_CLRENA_30   (0x40000000U << NVIC_ICER_CLRENA_Pos)

0x40000000

◆ NVIC_ICER_CLRENA_31

#define NVIC_ICER_CLRENA_31   (0x80000000U << NVIC_ICER_CLRENA_Pos)

0x80000000

◆ NVIC_ICER_CLRENA_4

#define NVIC_ICER_CLRENA_4   (0x00000010U << NVIC_ICER_CLRENA_Pos)

0x00000010

◆ NVIC_ICER_CLRENA_5

#define NVIC_ICER_CLRENA_5   (0x00000020U << NVIC_ICER_CLRENA_Pos)

0x00000020

◆ NVIC_ICER_CLRENA_6

#define NVIC_ICER_CLRENA_6   (0x00000040U << NVIC_ICER_CLRENA_Pos)

0x00000040

◆ NVIC_ICER_CLRENA_7

#define NVIC_ICER_CLRENA_7   (0x00000080U << NVIC_ICER_CLRENA_Pos)

0x00000080

◆ NVIC_ICER_CLRENA_8

#define NVIC_ICER_CLRENA_8   (0x00000100U << NVIC_ICER_CLRENA_Pos)

0x00000100

◆ NVIC_ICER_CLRENA_9

#define NVIC_ICER_CLRENA_9   (0x00000200U << NVIC_ICER_CLRENA_Pos)

0x00000200

◆ NVIC_ICER_CLRENA_Msk

#define NVIC_ICER_CLRENA_Msk   (0xFFFFFFFFU << NVIC_ICER_CLRENA_Pos)

0xFFFFFFFF

◆ NVIC_ICER_CLRENA_Pos

#define NVIC_ICER_CLRENA_Pos   (0U)

◆ NVIC_ICPR_CLRPEND

#define NVIC_ICPR_CLRPEND   NVIC_ICPR_CLRPEND_Msk

Interrupt clear-pending bits

◆ NVIC_ICPR_CLRPEND_0

#define NVIC_ICPR_CLRPEND_0   (0x00000001U << NVIC_ICPR_CLRPEND_Pos)

0x00000001

◆ NVIC_ICPR_CLRPEND_1

#define NVIC_ICPR_CLRPEND_1   (0x00000002U << NVIC_ICPR_CLRPEND_Pos)

0x00000002

◆ NVIC_ICPR_CLRPEND_10

#define NVIC_ICPR_CLRPEND_10   (0x00000400U << NVIC_ICPR_CLRPEND_Pos)

0x00000400

◆ NVIC_ICPR_CLRPEND_11

#define NVIC_ICPR_CLRPEND_11   (0x00000800U << NVIC_ICPR_CLRPEND_Pos)

0x00000800

◆ NVIC_ICPR_CLRPEND_12

#define NVIC_ICPR_CLRPEND_12   (0x00001000U << NVIC_ICPR_CLRPEND_Pos)

0x00001000

◆ NVIC_ICPR_CLRPEND_13

#define NVIC_ICPR_CLRPEND_13   (0x00002000U << NVIC_ICPR_CLRPEND_Pos)

0x00002000

◆ NVIC_ICPR_CLRPEND_14

#define NVIC_ICPR_CLRPEND_14   (0x00004000U << NVIC_ICPR_CLRPEND_Pos)

0x00004000

◆ NVIC_ICPR_CLRPEND_15

#define NVIC_ICPR_CLRPEND_15   (0x00008000U << NVIC_ICPR_CLRPEND_Pos)

0x00008000

◆ NVIC_ICPR_CLRPEND_16

#define NVIC_ICPR_CLRPEND_16   (0x00010000U << NVIC_ICPR_CLRPEND_Pos)

0x00010000

◆ NVIC_ICPR_CLRPEND_17

#define NVIC_ICPR_CLRPEND_17   (0x00020000U << NVIC_ICPR_CLRPEND_Pos)

0x00020000

◆ NVIC_ICPR_CLRPEND_18

#define NVIC_ICPR_CLRPEND_18   (0x00040000U << NVIC_ICPR_CLRPEND_Pos)

0x00040000

◆ NVIC_ICPR_CLRPEND_19

#define NVIC_ICPR_CLRPEND_19   (0x00080000U << NVIC_ICPR_CLRPEND_Pos)

0x00080000

◆ NVIC_ICPR_CLRPEND_2

#define NVIC_ICPR_CLRPEND_2   (0x00000004U << NVIC_ICPR_CLRPEND_Pos)

0x00000004

◆ NVIC_ICPR_CLRPEND_20

#define NVIC_ICPR_CLRPEND_20   (0x00100000U << NVIC_ICPR_CLRPEND_Pos)

0x00100000

◆ NVIC_ICPR_CLRPEND_21

#define NVIC_ICPR_CLRPEND_21   (0x00200000U << NVIC_ICPR_CLRPEND_Pos)

0x00200000

◆ NVIC_ICPR_CLRPEND_22

#define NVIC_ICPR_CLRPEND_22   (0x00400000U << NVIC_ICPR_CLRPEND_Pos)

0x00400000

◆ NVIC_ICPR_CLRPEND_23

#define NVIC_ICPR_CLRPEND_23   (0x00800000U << NVIC_ICPR_CLRPEND_Pos)

0x00800000

◆ NVIC_ICPR_CLRPEND_24

#define NVIC_ICPR_CLRPEND_24   (0x01000000U << NVIC_ICPR_CLRPEND_Pos)

0x01000000

◆ NVIC_ICPR_CLRPEND_25

#define NVIC_ICPR_CLRPEND_25   (0x02000000U << NVIC_ICPR_CLRPEND_Pos)

0x02000000

◆ NVIC_ICPR_CLRPEND_26

#define NVIC_ICPR_CLRPEND_26   (0x04000000U << NVIC_ICPR_CLRPEND_Pos)

0x04000000

◆ NVIC_ICPR_CLRPEND_27

#define NVIC_ICPR_CLRPEND_27   (0x08000000U << NVIC_ICPR_CLRPEND_Pos)

0x08000000

◆ NVIC_ICPR_CLRPEND_28

#define NVIC_ICPR_CLRPEND_28   (0x10000000U << NVIC_ICPR_CLRPEND_Pos)

0x10000000

◆ NVIC_ICPR_CLRPEND_29

#define NVIC_ICPR_CLRPEND_29   (0x20000000U << NVIC_ICPR_CLRPEND_Pos)

0x20000000

◆ NVIC_ICPR_CLRPEND_3

#define NVIC_ICPR_CLRPEND_3   (0x00000008U << NVIC_ICPR_CLRPEND_Pos)

0x00000008

◆ NVIC_ICPR_CLRPEND_30

#define NVIC_ICPR_CLRPEND_30   (0x40000000U << NVIC_ICPR_CLRPEND_Pos)

0x40000000

◆ NVIC_ICPR_CLRPEND_31

#define NVIC_ICPR_CLRPEND_31   (0x80000000U << NVIC_ICPR_CLRPEND_Pos)

0x80000000

◆ NVIC_ICPR_CLRPEND_4

#define NVIC_ICPR_CLRPEND_4   (0x00000010U << NVIC_ICPR_CLRPEND_Pos)

0x00000010

◆ NVIC_ICPR_CLRPEND_5

#define NVIC_ICPR_CLRPEND_5   (0x00000020U << NVIC_ICPR_CLRPEND_Pos)

0x00000020

◆ NVIC_ICPR_CLRPEND_6

#define NVIC_ICPR_CLRPEND_6   (0x00000040U << NVIC_ICPR_CLRPEND_Pos)

0x00000040

◆ NVIC_ICPR_CLRPEND_7

#define NVIC_ICPR_CLRPEND_7   (0x00000080U << NVIC_ICPR_CLRPEND_Pos)

0x00000080

◆ NVIC_ICPR_CLRPEND_8

#define NVIC_ICPR_CLRPEND_8   (0x00000100U << NVIC_ICPR_CLRPEND_Pos)

0x00000100

◆ NVIC_ICPR_CLRPEND_9

#define NVIC_ICPR_CLRPEND_9   (0x00000200U << NVIC_ICPR_CLRPEND_Pos)

0x00000200

◆ NVIC_ICPR_CLRPEND_Msk

#define NVIC_ICPR_CLRPEND_Msk   (0xFFFFFFFFU << NVIC_ICPR_CLRPEND_Pos)

0xFFFFFFFF

◆ NVIC_ICPR_CLRPEND_Pos

#define NVIC_ICPR_CLRPEND_Pos   (0U)

◆ NVIC_IPR0_PRI_0

#define NVIC_IPR0_PRI_0   (0x000000FFU)

Priority of interrupt 0

◆ NVIC_IPR0_PRI_1

#define NVIC_IPR0_PRI_1   (0x0000FF00U)

Priority of interrupt 1

◆ NVIC_IPR0_PRI_2

#define NVIC_IPR0_PRI_2   (0x00FF0000U)

Priority of interrupt 2

◆ NVIC_IPR0_PRI_3

#define NVIC_IPR0_PRI_3   (0xFF000000U)

Priority of interrupt 3

◆ NVIC_IPR1_PRI_4

#define NVIC_IPR1_PRI_4   (0x000000FFU)

Priority of interrupt 4

◆ NVIC_IPR1_PRI_5

#define NVIC_IPR1_PRI_5   (0x0000FF00U)

Priority of interrupt 5

◆ NVIC_IPR1_PRI_6

#define NVIC_IPR1_PRI_6   (0x00FF0000U)

Priority of interrupt 6

◆ NVIC_IPR1_PRI_7

#define NVIC_IPR1_PRI_7   (0xFF000000U)

Priority of interrupt 7

◆ NVIC_IPR2_PRI_10

#define NVIC_IPR2_PRI_10   (0x00FF0000U)

Priority of interrupt 10

◆ NVIC_IPR2_PRI_11

#define NVIC_IPR2_PRI_11   (0xFF000000U)

Priority of interrupt 11

◆ NVIC_IPR2_PRI_8

#define NVIC_IPR2_PRI_8   (0x000000FFU)

Priority of interrupt 8

◆ NVIC_IPR2_PRI_9

#define NVIC_IPR2_PRI_9   (0x0000FF00U)

Priority of interrupt 9

◆ NVIC_IPR3_PRI_12

#define NVIC_IPR3_PRI_12   (0x000000FFU)

Priority of interrupt 12

◆ NVIC_IPR3_PRI_13

#define NVIC_IPR3_PRI_13   (0x0000FF00U)

Priority of interrupt 13

◆ NVIC_IPR3_PRI_14

#define NVIC_IPR3_PRI_14   (0x00FF0000U)

Priority of interrupt 14

◆ NVIC_IPR3_PRI_15

#define NVIC_IPR3_PRI_15   (0xFF000000U)

Priority of interrupt 15

◆ NVIC_IPR4_PRI_16

#define NVIC_IPR4_PRI_16   (0x000000FFU)

Priority of interrupt 16

◆ NVIC_IPR4_PRI_17

#define NVIC_IPR4_PRI_17   (0x0000FF00U)

Priority of interrupt 17

◆ NVIC_IPR4_PRI_18

#define NVIC_IPR4_PRI_18   (0x00FF0000U)

Priority of interrupt 18

◆ NVIC_IPR4_PRI_19

#define NVIC_IPR4_PRI_19   (0xFF000000U)

Priority of interrupt 19

◆ NVIC_IPR5_PRI_20

#define NVIC_IPR5_PRI_20   (0x000000FFU)

Priority of interrupt 20

◆ NVIC_IPR5_PRI_21

#define NVIC_IPR5_PRI_21   (0x0000FF00U)

Priority of interrupt 21

◆ NVIC_IPR5_PRI_22

#define NVIC_IPR5_PRI_22   (0x00FF0000U)

Priority of interrupt 22

◆ NVIC_IPR5_PRI_23

#define NVIC_IPR5_PRI_23   (0xFF000000U)

Priority of interrupt 23

◆ NVIC_IPR6_PRI_24

#define NVIC_IPR6_PRI_24   (0x000000FFU)

Priority of interrupt 24

◆ NVIC_IPR6_PRI_25

#define NVIC_IPR6_PRI_25   (0x0000FF00U)

Priority of interrupt 25

◆ NVIC_IPR6_PRI_26

#define NVIC_IPR6_PRI_26   (0x00FF0000U)

Priority of interrupt 26

◆ NVIC_IPR6_PRI_27

#define NVIC_IPR6_PRI_27   (0xFF000000U)

Priority of interrupt 27

◆ NVIC_IPR7_PRI_28

#define NVIC_IPR7_PRI_28   (0x000000FFU)

Priority of interrupt 28

◆ NVIC_IPR7_PRI_29

#define NVIC_IPR7_PRI_29   (0x0000FF00U)

Priority of interrupt 29

◆ NVIC_IPR7_PRI_30

#define NVIC_IPR7_PRI_30   (0x00FF0000U)

Priority of interrupt 30

◆ NVIC_IPR7_PRI_31

#define NVIC_IPR7_PRI_31   (0xFF000000U)

Priority of interrupt 31

◆ NVIC_ISER_SETENA

#define NVIC_ISER_SETENA   NVIC_ISER_SETENA_Msk

Interrupt set enable bits

◆ NVIC_ISER_SETENA_0

#define NVIC_ISER_SETENA_0   (0x00000001U << NVIC_ISER_SETENA_Pos)

0x00000001

◆ NVIC_ISER_SETENA_1

#define NVIC_ISER_SETENA_1   (0x00000002U << NVIC_ISER_SETENA_Pos)

0x00000002

◆ NVIC_ISER_SETENA_10

#define NVIC_ISER_SETENA_10   (0x00000400U << NVIC_ISER_SETENA_Pos)

0x00000400

◆ NVIC_ISER_SETENA_11

#define NVIC_ISER_SETENA_11   (0x00000800U << NVIC_ISER_SETENA_Pos)

0x00000800

◆ NVIC_ISER_SETENA_12

#define NVIC_ISER_SETENA_12   (0x00001000U << NVIC_ISER_SETENA_Pos)

0x00001000

◆ NVIC_ISER_SETENA_13

#define NVIC_ISER_SETENA_13   (0x00002000U << NVIC_ISER_SETENA_Pos)

0x00002000

◆ NVIC_ISER_SETENA_14

#define NVIC_ISER_SETENA_14   (0x00004000U << NVIC_ISER_SETENA_Pos)

0x00004000

◆ NVIC_ISER_SETENA_15

#define NVIC_ISER_SETENA_15   (0x00008000U << NVIC_ISER_SETENA_Pos)

0x00008000

◆ NVIC_ISER_SETENA_16

#define NVIC_ISER_SETENA_16   (0x00010000U << NVIC_ISER_SETENA_Pos)

0x00010000

◆ NVIC_ISER_SETENA_17

#define NVIC_ISER_SETENA_17   (0x00020000U << NVIC_ISER_SETENA_Pos)

0x00020000

◆ NVIC_ISER_SETENA_18

#define NVIC_ISER_SETENA_18   (0x00040000U << NVIC_ISER_SETENA_Pos)

0x00040000

◆ NVIC_ISER_SETENA_19

#define NVIC_ISER_SETENA_19   (0x00080000U << NVIC_ISER_SETENA_Pos)

0x00080000

◆ NVIC_ISER_SETENA_2

#define NVIC_ISER_SETENA_2   (0x00000004U << NVIC_ISER_SETENA_Pos)

0x00000004

◆ NVIC_ISER_SETENA_20

#define NVIC_ISER_SETENA_20   (0x00100000U << NVIC_ISER_SETENA_Pos)

0x00100000

◆ NVIC_ISER_SETENA_21

#define NVIC_ISER_SETENA_21   (0x00200000U << NVIC_ISER_SETENA_Pos)

0x00200000

◆ NVIC_ISER_SETENA_22

#define NVIC_ISER_SETENA_22   (0x00400000U << NVIC_ISER_SETENA_Pos)

0x00400000

◆ NVIC_ISER_SETENA_23

#define NVIC_ISER_SETENA_23   (0x00800000U << NVIC_ISER_SETENA_Pos)

0x00800000

◆ NVIC_ISER_SETENA_24

#define NVIC_ISER_SETENA_24   (0x01000000U << NVIC_ISER_SETENA_Pos)

0x01000000

◆ NVIC_ISER_SETENA_25

#define NVIC_ISER_SETENA_25   (0x02000000U << NVIC_ISER_SETENA_Pos)

0x02000000

◆ NVIC_ISER_SETENA_26

#define NVIC_ISER_SETENA_26   (0x04000000U << NVIC_ISER_SETENA_Pos)

0x04000000

◆ NVIC_ISER_SETENA_27

#define NVIC_ISER_SETENA_27   (0x08000000U << NVIC_ISER_SETENA_Pos)

0x08000000

◆ NVIC_ISER_SETENA_28

#define NVIC_ISER_SETENA_28   (0x10000000U << NVIC_ISER_SETENA_Pos)

0x10000000

◆ NVIC_ISER_SETENA_29

#define NVIC_ISER_SETENA_29   (0x20000000U << NVIC_ISER_SETENA_Pos)

0x20000000

◆ NVIC_ISER_SETENA_3

#define NVIC_ISER_SETENA_3   (0x00000008U << NVIC_ISER_SETENA_Pos)

0x00000008

◆ NVIC_ISER_SETENA_30

#define NVIC_ISER_SETENA_30   (0x40000000U << NVIC_ISER_SETENA_Pos)

0x40000000

◆ NVIC_ISER_SETENA_31

#define NVIC_ISER_SETENA_31   (0x80000000U << NVIC_ISER_SETENA_Pos)

0x80000000

◆ NVIC_ISER_SETENA_4

#define NVIC_ISER_SETENA_4   (0x00000010U << NVIC_ISER_SETENA_Pos)

0x00000010

◆ NVIC_ISER_SETENA_5

#define NVIC_ISER_SETENA_5   (0x00000020U << NVIC_ISER_SETENA_Pos)

0x00000020

◆ NVIC_ISER_SETENA_6

#define NVIC_ISER_SETENA_6   (0x00000040U << NVIC_ISER_SETENA_Pos)

0x00000040

◆ NVIC_ISER_SETENA_7

#define NVIC_ISER_SETENA_7   (0x00000080U << NVIC_ISER_SETENA_Pos)

0x00000080

◆ NVIC_ISER_SETENA_8

#define NVIC_ISER_SETENA_8   (0x00000100U << NVIC_ISER_SETENA_Pos)

0x00000100

◆ NVIC_ISER_SETENA_9

#define NVIC_ISER_SETENA_9   (0x00000200U << NVIC_ISER_SETENA_Pos)

0x00000200

◆ NVIC_ISER_SETENA_Msk

#define NVIC_ISER_SETENA_Msk   (0xFFFFFFFFU << NVIC_ISER_SETENA_Pos)

0xFFFFFFFF

◆ NVIC_ISER_SETENA_Pos

#define NVIC_ISER_SETENA_Pos   (0U)

◆ NVIC_ISPR_SETPEND

#define NVIC_ISPR_SETPEND   NVIC_ISPR_SETPEND_Msk

Interrupt set-pending bits

◆ NVIC_ISPR_SETPEND_0

#define NVIC_ISPR_SETPEND_0   (0x00000001U << NVIC_ISPR_SETPEND_Pos)

0x00000001

◆ NVIC_ISPR_SETPEND_1

#define NVIC_ISPR_SETPEND_1   (0x00000002U << NVIC_ISPR_SETPEND_Pos)

0x00000002

◆ NVIC_ISPR_SETPEND_10

#define NVIC_ISPR_SETPEND_10   (0x00000400U << NVIC_ISPR_SETPEND_Pos)

0x00000400

◆ NVIC_ISPR_SETPEND_11

#define NVIC_ISPR_SETPEND_11   (0x00000800U << NVIC_ISPR_SETPEND_Pos)

0x00000800

◆ NVIC_ISPR_SETPEND_12

#define NVIC_ISPR_SETPEND_12   (0x00001000U << NVIC_ISPR_SETPEND_Pos)

0x00001000

◆ NVIC_ISPR_SETPEND_13

#define NVIC_ISPR_SETPEND_13   (0x00002000U << NVIC_ISPR_SETPEND_Pos)

0x00002000

◆ NVIC_ISPR_SETPEND_14

#define NVIC_ISPR_SETPEND_14   (0x00004000U << NVIC_ISPR_SETPEND_Pos)

0x00004000

◆ NVIC_ISPR_SETPEND_15

#define NVIC_ISPR_SETPEND_15   (0x00008000U << NVIC_ISPR_SETPEND_Pos)

0x00008000

◆ NVIC_ISPR_SETPEND_16

#define NVIC_ISPR_SETPEND_16   (0x00010000U << NVIC_ISPR_SETPEND_Pos)

0x00010000

◆ NVIC_ISPR_SETPEND_17

#define NVIC_ISPR_SETPEND_17   (0x00020000U << NVIC_ISPR_SETPEND_Pos)

0x00020000

◆ NVIC_ISPR_SETPEND_18

#define NVIC_ISPR_SETPEND_18   (0x00040000U << NVIC_ISPR_SETPEND_Pos)

0x00040000

◆ NVIC_ISPR_SETPEND_19

#define NVIC_ISPR_SETPEND_19   (0x00080000U << NVIC_ISPR_SETPEND_Pos)

0x00080000

◆ NVIC_ISPR_SETPEND_2

#define NVIC_ISPR_SETPEND_2   (0x00000004U << NVIC_ISPR_SETPEND_Pos)

0x00000004

◆ NVIC_ISPR_SETPEND_20

#define NVIC_ISPR_SETPEND_20   (0x00100000U << NVIC_ISPR_SETPEND_Pos)

0x00100000

◆ NVIC_ISPR_SETPEND_21

#define NVIC_ISPR_SETPEND_21   (0x00200000U << NVIC_ISPR_SETPEND_Pos)

0x00200000

◆ NVIC_ISPR_SETPEND_22

#define NVIC_ISPR_SETPEND_22   (0x00400000U << NVIC_ISPR_SETPEND_Pos)

0x00400000

◆ NVIC_ISPR_SETPEND_23

#define NVIC_ISPR_SETPEND_23   (0x00800000U << NVIC_ISPR_SETPEND_Pos)

0x00800000

◆ NVIC_ISPR_SETPEND_24

#define NVIC_ISPR_SETPEND_24   (0x01000000U << NVIC_ISPR_SETPEND_Pos)

0x01000000

◆ NVIC_ISPR_SETPEND_25

#define NVIC_ISPR_SETPEND_25   (0x02000000U << NVIC_ISPR_SETPEND_Pos)

0x02000000

◆ NVIC_ISPR_SETPEND_26

#define NVIC_ISPR_SETPEND_26   (0x04000000U << NVIC_ISPR_SETPEND_Pos)

0x04000000

◆ NVIC_ISPR_SETPEND_27

#define NVIC_ISPR_SETPEND_27   (0x08000000U << NVIC_ISPR_SETPEND_Pos)

0x08000000

◆ NVIC_ISPR_SETPEND_28

#define NVIC_ISPR_SETPEND_28   (0x10000000U << NVIC_ISPR_SETPEND_Pos)

0x10000000

◆ NVIC_ISPR_SETPEND_29

#define NVIC_ISPR_SETPEND_29   (0x20000000U << NVIC_ISPR_SETPEND_Pos)

0x20000000

◆ NVIC_ISPR_SETPEND_3

#define NVIC_ISPR_SETPEND_3   (0x00000008U << NVIC_ISPR_SETPEND_Pos)

0x00000008

◆ NVIC_ISPR_SETPEND_30

#define NVIC_ISPR_SETPEND_30   (0x40000000U << NVIC_ISPR_SETPEND_Pos)

0x40000000

◆ NVIC_ISPR_SETPEND_31

#define NVIC_ISPR_SETPEND_31   (0x80000000U << NVIC_ISPR_SETPEND_Pos)

0x80000000

◆ NVIC_ISPR_SETPEND_4

#define NVIC_ISPR_SETPEND_4   (0x00000010U << NVIC_ISPR_SETPEND_Pos)

0x00000010

◆ NVIC_ISPR_SETPEND_5

#define NVIC_ISPR_SETPEND_5   (0x00000020U << NVIC_ISPR_SETPEND_Pos)

0x00000020

◆ NVIC_ISPR_SETPEND_6

#define NVIC_ISPR_SETPEND_6   (0x00000040U << NVIC_ISPR_SETPEND_Pos)

0x00000040

◆ NVIC_ISPR_SETPEND_7

#define NVIC_ISPR_SETPEND_7   (0x00000080U << NVIC_ISPR_SETPEND_Pos)

0x00000080

◆ NVIC_ISPR_SETPEND_8

#define NVIC_ISPR_SETPEND_8   (0x00000100U << NVIC_ISPR_SETPEND_Pos)

0x00000100

◆ NVIC_ISPR_SETPEND_9

#define NVIC_ISPR_SETPEND_9   (0x00000200U << NVIC_ISPR_SETPEND_Pos)

0x00000200

◆ NVIC_ISPR_SETPEND_Msk

#define NVIC_ISPR_SETPEND_Msk   (0xFFFFFFFFU << NVIC_ISPR_SETPEND_Pos)

0xFFFFFFFF

◆ NVIC_ISPR_SETPEND_Pos

#define NVIC_ISPR_SETPEND_Pos   (0U)

◆ OPAMP_CSR_ANAWSEL1

#define OPAMP_CSR_ANAWSEL1   OPAMP_CSR_ANAWSEL1_Msk

Switch ANA Enable for OPAMP1

◆ OPAMP_CSR_ANAWSEL1_Msk

#define OPAMP_CSR_ANAWSEL1_Msk   (0x1U << OPAMP_CSR_ANAWSEL1_Pos)

0x01000000

◆ OPAMP_CSR_ANAWSEL1_Pos

#define OPAMP_CSR_ANAWSEL1_Pos   (24U)

◆ OPAMP_CSR_ANAWSEL2

#define OPAMP_CSR_ANAWSEL2   OPAMP_CSR_ANAWSEL2_Msk

Switch ANA Enable for OPAMP2

◆ OPAMP_CSR_ANAWSEL2_Msk

#define OPAMP_CSR_ANAWSEL2_Msk   (0x1U << OPAMP_CSR_ANAWSEL2_Pos)

0x02000000

◆ OPAMP_CSR_ANAWSEL2_Pos

#define OPAMP_CSR_ANAWSEL2_Pos   (25U)

◆ OPAMP_CSR_AOP_RANGE

#define OPAMP_CSR_AOP_RANGE   OPAMP_CSR_AOP_RANGE_Msk

Common to several OPAMP instances: Operational amplifier voltage supply range. Bit intended to be used with OPAMP common instance (OPAMP_Common_TypeDef)

◆ OPAMP_CSR_AOP_RANGE_Msk

#define OPAMP_CSR_AOP_RANGE_Msk   (0x1U << OPAMP_CSR_AOP_RANGE_Pos)

0x10000000

◆ OPAMP_CSR_AOP_RANGE_Pos

#define OPAMP_CSR_AOP_RANGE_Pos   (28U)

◆ OPAMP_CSR_OPA1CAL_H

#define OPAMP_CSR_OPA1CAL_H   OPAMP_CSR_OPA1CAL_H_Msk

OPAMP1 Offset calibration for N differential pair

◆ OPAMP_CSR_OPA1CAL_H_Msk

#define OPAMP_CSR_OPA1CAL_H_Msk   (0x1U << OPAMP_CSR_OPA1CAL_H_Pos)

0x00000040

◆ OPAMP_CSR_OPA1CAL_H_Pos

#define OPAMP_CSR_OPA1CAL_H_Pos   (6U)

◆ OPAMP_CSR_OPA1CAL_L

#define OPAMP_CSR_OPA1CAL_L   OPAMP_CSR_OPA1CAL_L_Msk

OPAMP1 Offset calibration for P differential pair

◆ OPAMP_CSR_OPA1CAL_L_Msk

#define OPAMP_CSR_OPA1CAL_L_Msk   (0x1U << OPAMP_CSR_OPA1CAL_L_Pos)

0x00000020

◆ OPAMP_CSR_OPA1CAL_L_Pos

#define OPAMP_CSR_OPA1CAL_L_Pos   (5U)

◆ OPAMP_CSR_OPA1CALOUT

#define OPAMP_CSR_OPA1CALOUT   OPAMP_CSR_OPA1CALOUT_Msk

OPAMP1 calibration output

◆ OPAMP_CSR_OPA1CALOUT_Msk

#define OPAMP_CSR_OPA1CALOUT_Msk   (0x1U << OPAMP_CSR_OPA1CALOUT_Pos)

0x20000000

◆ OPAMP_CSR_OPA1CALOUT_Pos

#define OPAMP_CSR_OPA1CALOUT_Pos   (29U)

◆ OPAMP_CSR_OPA1LPM

#define OPAMP_CSR_OPA1LPM   OPAMP_CSR_OPA1LPM_Msk

OPAMP1 Low power enable

◆ OPAMP_CSR_OPA1LPM_Msk

#define OPAMP_CSR_OPA1LPM_Msk   (0x1U << OPAMP_CSR_OPA1LPM_Pos)

0x00000080

◆ OPAMP_CSR_OPA1LPM_Pos

#define OPAMP_CSR_OPA1LPM_Pos   (7U)

◆ OPAMP_CSR_OPA1PD

#define OPAMP_CSR_OPA1PD   OPAMP_CSR_OPA1PD_Msk

OPAMP1 disable

◆ OPAMP_CSR_OPA1PD_Msk

#define OPAMP_CSR_OPA1PD_Msk   (0x1U << OPAMP_CSR_OPA1PD_Pos)

0x00000001

◆ OPAMP_CSR_OPA1PD_Pos

#define OPAMP_CSR_OPA1PD_Pos   (0U)

◆ OPAMP_CSR_OPA2CAL_H

#define OPAMP_CSR_OPA2CAL_H   OPAMP_CSR_OPA2CAL_H_Msk

OPAMP2 Offset calibration for N differential pair

◆ OPAMP_CSR_OPA2CAL_H_Msk

#define OPAMP_CSR_OPA2CAL_H_Msk   (0x1U << OPAMP_CSR_OPA2CAL_H_Pos)

0x00004000

◆ OPAMP_CSR_OPA2CAL_H_Pos

#define OPAMP_CSR_OPA2CAL_H_Pos   (14U)

◆ OPAMP_CSR_OPA2CAL_L

#define OPAMP_CSR_OPA2CAL_L   OPAMP_CSR_OPA2CAL_L_Msk

OPAMP2 Offset calibration for P differential pair

◆ OPAMP_CSR_OPA2CAL_L_Msk

#define OPAMP_CSR_OPA2CAL_L_Msk   (0x1U << OPAMP_CSR_OPA2CAL_L_Pos)

0x00002000

◆ OPAMP_CSR_OPA2CAL_L_Pos

#define OPAMP_CSR_OPA2CAL_L_Pos   (13U)

◆ OPAMP_CSR_OPA2CALOUT

#define OPAMP_CSR_OPA2CALOUT   OPAMP_CSR_OPA2CALOUT_Msk

OPAMP2 calibration output

◆ OPAMP_CSR_OPA2CALOUT_Msk

#define OPAMP_CSR_OPA2CALOUT_Msk   (0x1U << OPAMP_CSR_OPA2CALOUT_Pos)

0x40000000

◆ OPAMP_CSR_OPA2CALOUT_Pos

#define OPAMP_CSR_OPA2CALOUT_Pos   (30U)

◆ OPAMP_CSR_OPA2LPM

#define OPAMP_CSR_OPA2LPM   OPAMP_CSR_OPA2LPM_Msk

OPAMP2 Low power enable

◆ OPAMP_CSR_OPA2LPM_Msk

#define OPAMP_CSR_OPA2LPM_Msk   (0x1U << OPAMP_CSR_OPA2LPM_Pos)

0x00008000

◆ OPAMP_CSR_OPA2LPM_Pos

#define OPAMP_CSR_OPA2LPM_Pos   (15U)

◆ OPAMP_CSR_OPA2PD

#define OPAMP_CSR_OPA2PD   OPAMP_CSR_OPA2PD_Msk

OPAMP2 disable

◆ OPAMP_CSR_OPA2PD_Msk

#define OPAMP_CSR_OPA2PD_Msk   (0x1U << OPAMP_CSR_OPA2PD_Pos)

0x00000100

◆ OPAMP_CSR_OPA2PD_Pos

#define OPAMP_CSR_OPA2PD_Pos   (8U)

◆ OPAMP_CSR_S3SEL1

#define OPAMP_CSR_S3SEL1   OPAMP_CSR_S3SEL1_Msk

Switch 3 for OPAMP1 Enable

◆ OPAMP_CSR_S3SEL1_Msk

#define OPAMP_CSR_S3SEL1_Msk   (0x1U << OPAMP_CSR_S3SEL1_Pos)

0x00000002

◆ OPAMP_CSR_S3SEL1_Pos

#define OPAMP_CSR_S3SEL1_Pos   (1U)

◆ OPAMP_CSR_S3SEL2

#define OPAMP_CSR_S3SEL2   OPAMP_CSR_S3SEL2_Msk

Switch 3 for OPAMP2 Enable

◆ OPAMP_CSR_S3SEL2_Msk

#define OPAMP_CSR_S3SEL2_Msk   (0x1U << OPAMP_CSR_S3SEL2_Pos)

0x00000200

◆ OPAMP_CSR_S3SEL2_Pos

#define OPAMP_CSR_S3SEL2_Pos   (9U)

◆ OPAMP_CSR_S4SEL1

#define OPAMP_CSR_S4SEL1   OPAMP_CSR_S4SEL1_Msk

Switch 4 for OPAMP1 Enable

◆ OPAMP_CSR_S4SEL1_Msk

#define OPAMP_CSR_S4SEL1_Msk   (0x1U << OPAMP_CSR_S4SEL1_Pos)

0x00000004

◆ OPAMP_CSR_S4SEL1_Pos

#define OPAMP_CSR_S4SEL1_Pos   (2U)

◆ OPAMP_CSR_S4SEL2

#define OPAMP_CSR_S4SEL2   OPAMP_CSR_S4SEL2_Msk

Switch 4 for OPAMP2 Enable

◆ OPAMP_CSR_S4SEL2_Msk

#define OPAMP_CSR_S4SEL2_Msk   (0x1U << OPAMP_CSR_S4SEL2_Pos)

0x00000400

◆ OPAMP_CSR_S4SEL2_Pos

#define OPAMP_CSR_S4SEL2_Pos   (10U)

◆ OPAMP_CSR_S5SEL1

#define OPAMP_CSR_S5SEL1   OPAMP_CSR_S5SEL1_Msk

Switch 5 for OPAMP1 Enable

◆ OPAMP_CSR_S5SEL1_Msk

#define OPAMP_CSR_S5SEL1_Msk   (0x1U << OPAMP_CSR_S5SEL1_Pos)

0x00000008

◆ OPAMP_CSR_S5SEL1_Pos

#define OPAMP_CSR_S5SEL1_Pos   (3U)

◆ OPAMP_CSR_S5SEL2

#define OPAMP_CSR_S5SEL2   OPAMP_CSR_S5SEL2_Msk

Switch 5 for OPAMP2 Enable

◆ OPAMP_CSR_S5SEL2_Msk

#define OPAMP_CSR_S5SEL2_Msk   (0x1U << OPAMP_CSR_S5SEL2_Pos)

0x00000800

◆ OPAMP_CSR_S5SEL2_Pos

#define OPAMP_CSR_S5SEL2_Pos   (11U)

◆ OPAMP_CSR_S6SEL1

#define OPAMP_CSR_S6SEL1   OPAMP_CSR_S6SEL1_Msk

Switch 6 for OPAMP1 Enable

◆ OPAMP_CSR_S6SEL1_Msk

#define OPAMP_CSR_S6SEL1_Msk   (0x1U << OPAMP_CSR_S6SEL1_Pos)

0x00000010

◆ OPAMP_CSR_S6SEL1_Pos

#define OPAMP_CSR_S6SEL1_Pos   (4U)

◆ OPAMP_CSR_S6SEL2

#define OPAMP_CSR_S6SEL2   OPAMP_CSR_S6SEL2_Msk

Switch 6 for OPAMP2 Enable

◆ OPAMP_CSR_S6SEL2_Msk

#define OPAMP_CSR_S6SEL2_Msk   (0x1U << OPAMP_CSR_S6SEL2_Pos)

0x00001000

◆ OPAMP_CSR_S6SEL2_Pos

#define OPAMP_CSR_S6SEL2_Pos   (12U)

◆ OPAMP_CSR_S7SEL2

#define OPAMP_CSR_S7SEL2   OPAMP_CSR_S7SEL2_Msk

Switch 7 for OPAMP2 Enable

◆ OPAMP_CSR_S7SEL2_Msk

#define OPAMP_CSR_S7SEL2_Msk   (0x1U << OPAMP_CSR_S7SEL2_Pos)

0x08000000

◆ OPAMP_CSR_S7SEL2_Pos

#define OPAMP_CSR_S7SEL2_Pos   (27U)

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk

Offset trim for transistors differential pair NMOS of OPAMP1

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Msk   (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos)

0x000003E0

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH_Pos   (5U)

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk

Offset trim for transistors differential pair PMOS of OPAMP1

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Msk   (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos)

0x0000001F

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW_Pos   (0U)

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk

Offset trim for transistors differential pair NMOS of OPAMP1

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Msk   (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos)

0x000003E0

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH_Pos   (5U)

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk

Offset trim for transistors differential pair PMOS of OPAMP1

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Msk   (0x1FU << OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos)

0x0000001F

◆ OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos

#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW_Pos   (0U)

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH   OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk

Offset trim for transistors differential pair NMOS of OPAMP2

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Msk   (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos)

0x000F8000

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH_Pos   (15U)

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW   OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk

Offset trim for transistors differential pair PMOS of OPAMP2

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Msk   (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos)

0x00007C00

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW_Pos   (10U)

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH   OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk

Offset trim for transistors differential pair NMOS of OPAMP2

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Msk   (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos)

0x000F8000

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH_Pos   (15U)

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW   OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk

Offset trim for transistors differential pair PMOS of OPAMP2

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Msk   (0x1FU << OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos)

0x00007C00

◆ OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos

#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW_Pos   (10U)

◆ OPAMP_OTR_OT_USER

#define OPAMP_OTR_OT_USER   OPAMP_OTR_OT_USER_Msk

Switch to OPAMP offset user trimmed values

◆ OPAMP_OTR_OT_USER_Msk

#define OPAMP_OTR_OT_USER_Msk   (0x1U << OPAMP_OTR_OT_USER_Pos)

0x80000000

◆ OPAMP_OTR_OT_USER_Pos

#define OPAMP_OTR_OT_USER_Pos   (31U)

◆ PWR_CR_CSBF

#define PWR_CR_CSBF   PWR_CR_CSBF_Msk

Clear Standby Flag

◆ PWR_CR_CSBF_Msk

#define PWR_CR_CSBF_Msk   (0x1U << PWR_CR_CSBF_Pos)

0x00000008

◆ PWR_CR_CSBF_Pos

#define PWR_CR_CSBF_Pos   (3U)

◆ PWR_CR_CWUF

#define PWR_CR_CWUF   PWR_CR_CWUF_Msk

Clear Wakeup Flag

◆ PWR_CR_CWUF_Msk

#define PWR_CR_CWUF_Msk   (0x1U << PWR_CR_CWUF_Pos)

0x00000004

◆ PWR_CR_CWUF_Pos

#define PWR_CR_CWUF_Pos   (2U)

◆ PWR_CR_DBP

#define PWR_CR_DBP   PWR_CR_DBP_Msk

Disable Backup Domain write protection

◆ PWR_CR_DBP_Msk

#define PWR_CR_DBP_Msk   (0x1U << PWR_CR_DBP_Pos)

0x00000100

◆ PWR_CR_DBP_Pos

#define PWR_CR_DBP_Pos   (8U)

◆ PWR_CR_FWU

#define PWR_CR_FWU   PWR_CR_FWU_Msk

Fast wakeup

◆ PWR_CR_FWU_Msk

#define PWR_CR_FWU_Msk   (0x1U << PWR_CR_FWU_Pos)

0x00000400

◆ PWR_CR_FWU_Pos

#define PWR_CR_FWU_Pos   (10U)

◆ PWR_CR_LPRUN

#define PWR_CR_LPRUN   PWR_CR_LPRUN_Msk

Low power run mode

◆ PWR_CR_LPRUN_Msk

#define PWR_CR_LPRUN_Msk   (0x1U << PWR_CR_LPRUN_Pos)

0x00004000

◆ PWR_CR_LPRUN_Pos

#define PWR_CR_LPRUN_Pos   (14U)

◆ PWR_CR_LPSDSR

#define PWR_CR_LPSDSR   PWR_CR_LPSDSR_Msk

Low-power deepsleep/sleep/low power run

◆ PWR_CR_LPSDSR_Msk

#define PWR_CR_LPSDSR_Msk   (0x1U << PWR_CR_LPSDSR_Pos)

0x00000001

◆ PWR_CR_LPSDSR_Pos

#define PWR_CR_LPSDSR_Pos   (0U)

◆ PWR_CR_PDDS

#define PWR_CR_PDDS   PWR_CR_PDDS_Msk

Power Down Deepsleep

◆ PWR_CR_PDDS_Msk

#define PWR_CR_PDDS_Msk   (0x1U << PWR_CR_PDDS_Pos)

0x00000002

◆ PWR_CR_PDDS_Pos

#define PWR_CR_PDDS_Pos   (1U)

◆ PWR_CR_PLS

#define PWR_CR_PLS   PWR_CR_PLS_Msk

PLS[2:0] bits (PVD Level Selection)

◆ PWR_CR_PLS_0

#define PWR_CR_PLS_0   (0x1U << PWR_CR_PLS_Pos)

0x00000020

◆ PWR_CR_PLS_1

#define PWR_CR_PLS_1   (0x2U << PWR_CR_PLS_Pos)

0x00000040

◆ PWR_CR_PLS_2

#define PWR_CR_PLS_2   (0x4U << PWR_CR_PLS_Pos)

0x00000080 PVD level configuration

◆ PWR_CR_PLS_LEV0

#define PWR_CR_PLS_LEV0   (0x00000000U)

PVD level 0

◆ PWR_CR_PLS_LEV1

#define PWR_CR_PLS_LEV1   (0x00000020U)

PVD level 1

◆ PWR_CR_PLS_LEV2

#define PWR_CR_PLS_LEV2   (0x00000040U)

PVD level 2

◆ PWR_CR_PLS_LEV3

#define PWR_CR_PLS_LEV3   (0x00000060U)

PVD level 3

◆ PWR_CR_PLS_LEV4

#define PWR_CR_PLS_LEV4   (0x00000080U)

PVD level 4

◆ PWR_CR_PLS_LEV5

#define PWR_CR_PLS_LEV5   (0x000000A0U)

PVD level 5

◆ PWR_CR_PLS_LEV6

#define PWR_CR_PLS_LEV6   (0x000000C0U)

PVD level 6

◆ PWR_CR_PLS_LEV7

#define PWR_CR_PLS_LEV7   (0x000000E0U)

PVD level 7

◆ PWR_CR_PLS_Msk

#define PWR_CR_PLS_Msk   (0x7U << PWR_CR_PLS_Pos)

0x000000E0

◆ PWR_CR_PLS_Pos

#define PWR_CR_PLS_Pos   (5U)

◆ PWR_CR_PVDE

#define PWR_CR_PVDE   PWR_CR_PVDE_Msk

Power Voltage Detector Enable

◆ PWR_CR_PVDE_Msk

#define PWR_CR_PVDE_Msk   (0x1U << PWR_CR_PVDE_Pos)

0x00000010

◆ PWR_CR_PVDE_Pos

#define PWR_CR_PVDE_Pos   (4U)

◆ PWR_CR_ULP

#define PWR_CR_ULP   PWR_CR_ULP_Msk

Ultra Low Power mode

◆ PWR_CR_ULP_Msk

#define PWR_CR_ULP_Msk   (0x1U << PWR_CR_ULP_Pos)

0x00000200

◆ PWR_CR_ULP_Pos

#define PWR_CR_ULP_Pos   (9U)

◆ PWR_CR_VOS

#define PWR_CR_VOS   PWR_CR_VOS_Msk

VOS[1:0] bits (Voltage scaling range selection)

◆ PWR_CR_VOS_0

#define PWR_CR_VOS_0   (0x1U << PWR_CR_VOS_Pos)

0x00000800

◆ PWR_CR_VOS_1

#define PWR_CR_VOS_1   (0x2U << PWR_CR_VOS_Pos)

0x00001000

◆ PWR_CR_VOS_Msk

#define PWR_CR_VOS_Msk   (0x3U << PWR_CR_VOS_Pos)

0x00001800

◆ PWR_CR_VOS_Pos

#define PWR_CR_VOS_Pos   (11U)

◆ PWR_CSR_EWUP1

#define PWR_CSR_EWUP1   PWR_CSR_EWUP1_Msk

Enable WKUP pin 1

◆ PWR_CSR_EWUP1_Msk

#define PWR_CSR_EWUP1_Msk   (0x1U << PWR_CSR_EWUP1_Pos)

0x00000100

◆ PWR_CSR_EWUP1_Pos

#define PWR_CSR_EWUP1_Pos   (8U)

◆ PWR_CSR_EWUP2

#define PWR_CSR_EWUP2   PWR_CSR_EWUP2_Msk

Enable WKUP pin 2

◆ PWR_CSR_EWUP2_Msk

#define PWR_CSR_EWUP2_Msk   (0x1U << PWR_CSR_EWUP2_Pos)

0x00000200

◆ PWR_CSR_EWUP2_Pos

#define PWR_CSR_EWUP2_Pos   (9U)

◆ PWR_CSR_EWUP3

#define PWR_CSR_EWUP3   PWR_CSR_EWUP3_Msk

Enable WKUP pin 3

◆ PWR_CSR_EWUP3_Msk

#define PWR_CSR_EWUP3_Msk   (0x1U << PWR_CSR_EWUP3_Pos)

0x00000400

◆ PWR_CSR_EWUP3_Pos

#define PWR_CSR_EWUP3_Pos   (10U)

◆ PWR_CSR_PVDO

#define PWR_CSR_PVDO   PWR_CSR_PVDO_Msk

PVD Output

◆ PWR_CSR_PVDO_Msk

#define PWR_CSR_PVDO_Msk   (0x1U << PWR_CSR_PVDO_Pos)

0x00000004

◆ PWR_CSR_PVDO_Pos

#define PWR_CSR_PVDO_Pos   (2U)

◆ PWR_CSR_REGLPF

#define PWR_CSR_REGLPF   PWR_CSR_REGLPF_Msk

Regulator LP flag

◆ PWR_CSR_REGLPF_Msk

#define PWR_CSR_REGLPF_Msk   (0x1U << PWR_CSR_REGLPF_Pos)

0x00000020

◆ PWR_CSR_REGLPF_Pos

#define PWR_CSR_REGLPF_Pos   (5U)

◆ PWR_CSR_SBF

#define PWR_CSR_SBF   PWR_CSR_SBF_Msk

Standby Flag

◆ PWR_CSR_SBF_Msk

#define PWR_CSR_SBF_Msk   (0x1U << PWR_CSR_SBF_Pos)

0x00000002

◆ PWR_CSR_SBF_Pos

#define PWR_CSR_SBF_Pos   (1U)

◆ PWR_CSR_VOSF

#define PWR_CSR_VOSF   PWR_CSR_VOSF_Msk

Voltage Scaling select flag

◆ PWR_CSR_VOSF_Msk

#define PWR_CSR_VOSF_Msk   (0x1U << PWR_CSR_VOSF_Pos)

0x00000010

◆ PWR_CSR_VOSF_Pos

#define PWR_CSR_VOSF_Pos   (4U)

◆ PWR_CSR_VREFINTRDYF

#define PWR_CSR_VREFINTRDYF   PWR_CSR_VREFINTRDYF_Msk

Internal voltage reference (VREFINT) ready flag

◆ PWR_CSR_VREFINTRDYF_Msk

#define PWR_CSR_VREFINTRDYF_Msk   (0x1U << PWR_CSR_VREFINTRDYF_Pos)

0x00000008

◆ PWR_CSR_VREFINTRDYF_Pos

#define PWR_CSR_VREFINTRDYF_Pos   (3U)

◆ PWR_CSR_WUF

#define PWR_CSR_WUF   PWR_CSR_WUF_Msk

Wakeup Flag

◆ PWR_CSR_WUF_Msk

#define PWR_CSR_WUF_Msk   (0x1U << PWR_CSR_WUF_Pos)

0x00000001

◆ PWR_CSR_WUF_Pos

#define PWR_CSR_WUF_Pos   (0U)

◆ PWR_PVD_SUPPORT

#define PWR_PVD_SUPPORT

PWR feature available only on specific devices: Power Voltage Detection feature

◆ RCC_AHBENR_CRCEN

#define RCC_AHBENR_CRCEN   RCC_AHBENR_CRCEN_Msk

CRC clock enable

◆ RCC_AHBENR_CRCEN_Msk

#define RCC_AHBENR_CRCEN_Msk   (0x1U << RCC_AHBENR_CRCEN_Pos)

0x00001000

◆ RCC_AHBENR_CRCEN_Pos

#define RCC_AHBENR_CRCEN_Pos   (12U)

◆ RCC_AHBENR_DMA1EN

#define RCC_AHBENR_DMA1EN   RCC_AHBENR_DMA1EN_Msk

DMA1 clock enable

◆ RCC_AHBENR_DMA1EN_Msk

#define RCC_AHBENR_DMA1EN_Msk   (0x1U << RCC_AHBENR_DMA1EN_Pos)

0x01000000

◆ RCC_AHBENR_DMA1EN_Pos

#define RCC_AHBENR_DMA1EN_Pos   (24U)

◆ RCC_AHBENR_DMA2EN

#define RCC_AHBENR_DMA2EN   RCC_AHBENR_DMA2EN_Msk

DMA2 clock enable

◆ RCC_AHBENR_DMA2EN_Msk

#define RCC_AHBENR_DMA2EN_Msk   (0x1U << RCC_AHBENR_DMA2EN_Pos)

0x02000000

◆ RCC_AHBENR_DMA2EN_Pos

#define RCC_AHBENR_DMA2EN_Pos   (25U)

◆ RCC_AHBENR_FLITFEN

#define RCC_AHBENR_FLITFEN   RCC_AHBENR_FLITFEN_Msk

FLITF clock enable (has effect only when the Flash memory is in power down mode)

◆ RCC_AHBENR_FLITFEN_Msk

#define RCC_AHBENR_FLITFEN_Msk   (0x1U << RCC_AHBENR_FLITFEN_Pos)

0x00008000

◆ RCC_AHBENR_FLITFEN_Pos

#define RCC_AHBENR_FLITFEN_Pos   (15U)

◆ RCC_AHBENR_GPIOAEN

#define RCC_AHBENR_GPIOAEN   RCC_AHBENR_GPIOAEN_Msk

GPIO port A clock enable

◆ RCC_AHBENR_GPIOAEN_Msk

#define RCC_AHBENR_GPIOAEN_Msk   (0x1U << RCC_AHBENR_GPIOAEN_Pos)

0x00000001

◆ RCC_AHBENR_GPIOAEN_Pos

#define RCC_AHBENR_GPIOAEN_Pos   (0U)

◆ RCC_AHBENR_GPIOBEN

#define RCC_AHBENR_GPIOBEN   RCC_AHBENR_GPIOBEN_Msk

GPIO port B clock enable

◆ RCC_AHBENR_GPIOBEN_Msk

#define RCC_AHBENR_GPIOBEN_Msk   (0x1U << RCC_AHBENR_GPIOBEN_Pos)

0x00000002

◆ RCC_AHBENR_GPIOBEN_Pos

#define RCC_AHBENR_GPIOBEN_Pos   (1U)

◆ RCC_AHBENR_GPIOCEN

#define RCC_AHBENR_GPIOCEN   RCC_AHBENR_GPIOCEN_Msk

GPIO port C clock enable

◆ RCC_AHBENR_GPIOCEN_Msk

#define RCC_AHBENR_GPIOCEN_Msk   (0x1U << RCC_AHBENR_GPIOCEN_Pos)

0x00000004

◆ RCC_AHBENR_GPIOCEN_Pos

#define RCC_AHBENR_GPIOCEN_Pos   (2U)

◆ RCC_AHBENR_GPIODEN

#define RCC_AHBENR_GPIODEN   RCC_AHBENR_GPIODEN_Msk

GPIO port D clock enable

◆ RCC_AHBENR_GPIODEN_Msk

#define RCC_AHBENR_GPIODEN_Msk   (0x1U << RCC_AHBENR_GPIODEN_Pos)

0x00000008

◆ RCC_AHBENR_GPIODEN_Pos

#define RCC_AHBENR_GPIODEN_Pos   (3U)

◆ RCC_AHBENR_GPIOEEN

#define RCC_AHBENR_GPIOEEN   RCC_AHBENR_GPIOEEN_Msk

GPIO port E clock enable

◆ RCC_AHBENR_GPIOEEN_Msk

#define RCC_AHBENR_GPIOEEN_Msk   (0x1U << RCC_AHBENR_GPIOEEN_Pos)

0x00000010

◆ RCC_AHBENR_GPIOEEN_Pos

#define RCC_AHBENR_GPIOEEN_Pos   (4U)

◆ RCC_AHBENR_GPIOFEN

#define RCC_AHBENR_GPIOFEN   RCC_AHBENR_GPIOFEN_Msk

GPIO port F clock enable

◆ RCC_AHBENR_GPIOFEN_Msk

#define RCC_AHBENR_GPIOFEN_Msk   (0x1U << RCC_AHBENR_GPIOFEN_Pos)

0x00000040

◆ RCC_AHBENR_GPIOFEN_Pos

#define RCC_AHBENR_GPIOFEN_Pos   (6U)

◆ RCC_AHBENR_GPIOGEN

#define RCC_AHBENR_GPIOGEN   RCC_AHBENR_GPIOGEN_Msk

GPIO port G clock enable

◆ RCC_AHBENR_GPIOGEN_Msk

#define RCC_AHBENR_GPIOGEN_Msk   (0x1U << RCC_AHBENR_GPIOGEN_Pos)

0x00000080

◆ RCC_AHBENR_GPIOGEN_Pos

#define RCC_AHBENR_GPIOGEN_Pos   (7U)

◆ RCC_AHBENR_GPIOHEN

#define RCC_AHBENR_GPIOHEN   RCC_AHBENR_GPIOHEN_Msk

GPIO port H clock enable

◆ RCC_AHBENR_GPIOHEN_Msk

#define RCC_AHBENR_GPIOHEN_Msk   (0x1U << RCC_AHBENR_GPIOHEN_Pos)

0x00000020

◆ RCC_AHBENR_GPIOHEN_Pos

#define RCC_AHBENR_GPIOHEN_Pos   (5U)

◆ RCC_AHBLPENR_CRCLPEN

#define RCC_AHBLPENR_CRCLPEN   RCC_AHBLPENR_CRCLPEN_Msk

CRC clock enabled in sleep mode

◆ RCC_AHBLPENR_CRCLPEN_Msk

#define RCC_AHBLPENR_CRCLPEN_Msk   (0x1U << RCC_AHBLPENR_CRCLPEN_Pos)

0x00001000

◆ RCC_AHBLPENR_CRCLPEN_Pos

#define RCC_AHBLPENR_CRCLPEN_Pos   (12U)

◆ RCC_AHBLPENR_DMA1LPEN

#define RCC_AHBLPENR_DMA1LPEN   RCC_AHBLPENR_DMA1LPEN_Msk

DMA1 clock enabled in sleep mode

◆ RCC_AHBLPENR_DMA1LPEN_Msk

#define RCC_AHBLPENR_DMA1LPEN_Msk   (0x1U << RCC_AHBLPENR_DMA1LPEN_Pos)

0x01000000

◆ RCC_AHBLPENR_DMA1LPEN_Pos

#define RCC_AHBLPENR_DMA1LPEN_Pos   (24U)

◆ RCC_AHBLPENR_DMA2LPEN

#define RCC_AHBLPENR_DMA2LPEN   RCC_AHBLPENR_DMA2LPEN_Msk

DMA2 clock enabled in sleep mode

◆ RCC_AHBLPENR_DMA2LPEN_Msk

#define RCC_AHBLPENR_DMA2LPEN_Msk   (0x1U << RCC_AHBLPENR_DMA2LPEN_Pos)

0x02000000

◆ RCC_AHBLPENR_DMA2LPEN_Pos

#define RCC_AHBLPENR_DMA2LPEN_Pos   (25U)

◆ RCC_AHBLPENR_FLITFLPEN

#define RCC_AHBLPENR_FLITFLPEN   RCC_AHBLPENR_FLITFLPEN_Msk

Flash Interface clock enabled in sleep mode (has effect only when the Flash memory is in power down mode)

◆ RCC_AHBLPENR_FLITFLPEN_Msk

#define RCC_AHBLPENR_FLITFLPEN_Msk   (0x1U << RCC_AHBLPENR_FLITFLPEN_Pos)

0x00008000

◆ RCC_AHBLPENR_FLITFLPEN_Pos

#define RCC_AHBLPENR_FLITFLPEN_Pos   (15U)

◆ RCC_AHBLPENR_GPIOALPEN

#define RCC_AHBLPENR_GPIOALPEN   RCC_AHBLPENR_GPIOALPEN_Msk

GPIO port A clock enabled in sleep mode

◆ RCC_AHBLPENR_GPIOALPEN_Msk

#define RCC_AHBLPENR_GPIOALPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOALPEN_Pos)

0x00000001

◆ RCC_AHBLPENR_GPIOALPEN_Pos

#define RCC_AHBLPENR_GPIOALPEN_Pos   (0U)

◆ RCC_AHBLPENR_GPIOBLPEN

#define RCC_AHBLPENR_GPIOBLPEN   RCC_AHBLPENR_GPIOBLPEN_Msk

GPIO port B clock enabled in sleep mode

◆ RCC_AHBLPENR_GPIOBLPEN_Msk

#define RCC_AHBLPENR_GPIOBLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOBLPEN_Pos)

0x00000002

◆ RCC_AHBLPENR_GPIOBLPEN_Pos

#define RCC_AHBLPENR_GPIOBLPEN_Pos   (1U)

◆ RCC_AHBLPENR_GPIOCLPEN

#define RCC_AHBLPENR_GPIOCLPEN   RCC_AHBLPENR_GPIOCLPEN_Msk

GPIO port C clock enabled in sleep mode

◆ RCC_AHBLPENR_GPIOCLPEN_Msk

#define RCC_AHBLPENR_GPIOCLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOCLPEN_Pos)

0x00000004

◆ RCC_AHBLPENR_GPIOCLPEN_Pos

#define RCC_AHBLPENR_GPIOCLPEN_Pos   (2U)

◆ RCC_AHBLPENR_GPIODLPEN

#define RCC_AHBLPENR_GPIODLPEN   RCC_AHBLPENR_GPIODLPEN_Msk

GPIO port D clock enabled in sleep mode

◆ RCC_AHBLPENR_GPIODLPEN_Msk

#define RCC_AHBLPENR_GPIODLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIODLPEN_Pos)

0x00000008

◆ RCC_AHBLPENR_GPIODLPEN_Pos

#define RCC_AHBLPENR_GPIODLPEN_Pos   (3U)

◆ RCC_AHBLPENR_GPIOELPEN

#define RCC_AHBLPENR_GPIOELPEN   RCC_AHBLPENR_GPIOELPEN_Msk

GPIO port E clock enabled in sleep mode

◆ RCC_AHBLPENR_GPIOELPEN_Msk

#define RCC_AHBLPENR_GPIOELPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOELPEN_Pos)

0x00000010

◆ RCC_AHBLPENR_GPIOELPEN_Pos

#define RCC_AHBLPENR_GPIOELPEN_Pos   (4U)

◆ RCC_AHBLPENR_GPIOFLPEN

#define RCC_AHBLPENR_GPIOFLPEN   RCC_AHBLPENR_GPIOFLPEN_Msk

GPIO port F clock enabled in sleep mode

◆ RCC_AHBLPENR_GPIOFLPEN_Msk

#define RCC_AHBLPENR_GPIOFLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOFLPEN_Pos)

0x00000040

◆ RCC_AHBLPENR_GPIOFLPEN_Pos

#define RCC_AHBLPENR_GPIOFLPEN_Pos   (6U)

◆ RCC_AHBLPENR_GPIOGLPEN

#define RCC_AHBLPENR_GPIOGLPEN   RCC_AHBLPENR_GPIOGLPEN_Msk

GPIO port G clock enabled in sleep mode

◆ RCC_AHBLPENR_GPIOGLPEN_Msk

#define RCC_AHBLPENR_GPIOGLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOGLPEN_Pos)

0x00000080

◆ RCC_AHBLPENR_GPIOGLPEN_Pos

#define RCC_AHBLPENR_GPIOGLPEN_Pos   (7U)

◆ RCC_AHBLPENR_GPIOHLPEN

#define RCC_AHBLPENR_GPIOHLPEN   RCC_AHBLPENR_GPIOHLPEN_Msk

GPIO port H clock enabled in sleep mode

◆ RCC_AHBLPENR_GPIOHLPEN_Msk

#define RCC_AHBLPENR_GPIOHLPEN_Msk   (0x1U << RCC_AHBLPENR_GPIOHLPEN_Pos)

0x00000020

◆ RCC_AHBLPENR_GPIOHLPEN_Pos

#define RCC_AHBLPENR_GPIOHLPEN_Pos   (5U)

◆ RCC_AHBLPENR_SRAMLPEN

#define RCC_AHBLPENR_SRAMLPEN   RCC_AHBLPENR_SRAMLPEN_Msk

SRAM clock enabled in sleep mode

◆ RCC_AHBLPENR_SRAMLPEN_Msk

#define RCC_AHBLPENR_SRAMLPEN_Msk   (0x1U << RCC_AHBLPENR_SRAMLPEN_Pos)

0x00010000

◆ RCC_AHBLPENR_SRAMLPEN_Pos

#define RCC_AHBLPENR_SRAMLPEN_Pos   (16U)

◆ RCC_AHBRSTR_CRCRST

#define RCC_AHBRSTR_CRCRST   RCC_AHBRSTR_CRCRST_Msk

CRC reset

◆ RCC_AHBRSTR_CRCRST_Msk

#define RCC_AHBRSTR_CRCRST_Msk   (0x1U << RCC_AHBRSTR_CRCRST_Pos)

0x00001000

◆ RCC_AHBRSTR_CRCRST_Pos

#define RCC_AHBRSTR_CRCRST_Pos   (12U)

◆ RCC_AHBRSTR_DMA1RST

#define RCC_AHBRSTR_DMA1RST   RCC_AHBRSTR_DMA1RST_Msk

DMA1 reset

◆ RCC_AHBRSTR_DMA1RST_Msk

#define RCC_AHBRSTR_DMA1RST_Msk   (0x1U << RCC_AHBRSTR_DMA1RST_Pos)

0x01000000

◆ RCC_AHBRSTR_DMA1RST_Pos

#define RCC_AHBRSTR_DMA1RST_Pos   (24U)

◆ RCC_AHBRSTR_DMA2RST

#define RCC_AHBRSTR_DMA2RST   RCC_AHBRSTR_DMA2RST_Msk

DMA2 reset

◆ RCC_AHBRSTR_DMA2RST_Msk

#define RCC_AHBRSTR_DMA2RST_Msk   (0x1U << RCC_AHBRSTR_DMA2RST_Pos)

0x02000000

◆ RCC_AHBRSTR_DMA2RST_Pos

#define RCC_AHBRSTR_DMA2RST_Pos   (25U)

◆ RCC_AHBRSTR_FLITFRST

#define RCC_AHBRSTR_FLITFRST   RCC_AHBRSTR_FLITFRST_Msk

FLITF reset

◆ RCC_AHBRSTR_FLITFRST_Msk

#define RCC_AHBRSTR_FLITFRST_Msk   (0x1U << RCC_AHBRSTR_FLITFRST_Pos)

0x00008000

◆ RCC_AHBRSTR_FLITFRST_Pos

#define RCC_AHBRSTR_FLITFRST_Pos   (15U)

◆ RCC_AHBRSTR_GPIOARST

#define RCC_AHBRSTR_GPIOARST   RCC_AHBRSTR_GPIOARST_Msk

GPIO port A reset

◆ RCC_AHBRSTR_GPIOARST_Msk

#define RCC_AHBRSTR_GPIOARST_Msk   (0x1U << RCC_AHBRSTR_GPIOARST_Pos)

0x00000001

◆ RCC_AHBRSTR_GPIOARST_Pos

#define RCC_AHBRSTR_GPIOARST_Pos   (0U)

◆ RCC_AHBRSTR_GPIOBRST

#define RCC_AHBRSTR_GPIOBRST   RCC_AHBRSTR_GPIOBRST_Msk

GPIO port B reset

◆ RCC_AHBRSTR_GPIOBRST_Msk

#define RCC_AHBRSTR_GPIOBRST_Msk   (0x1U << RCC_AHBRSTR_GPIOBRST_Pos)

0x00000002

◆ RCC_AHBRSTR_GPIOBRST_Pos

#define RCC_AHBRSTR_GPIOBRST_Pos   (1U)

◆ RCC_AHBRSTR_GPIOCRST

#define RCC_AHBRSTR_GPIOCRST   RCC_AHBRSTR_GPIOCRST_Msk

GPIO port C reset

◆ RCC_AHBRSTR_GPIOCRST_Msk

#define RCC_AHBRSTR_GPIOCRST_Msk   (0x1U << RCC_AHBRSTR_GPIOCRST_Pos)

0x00000004

◆ RCC_AHBRSTR_GPIOCRST_Pos

#define RCC_AHBRSTR_GPIOCRST_Pos   (2U)

◆ RCC_AHBRSTR_GPIODRST

#define RCC_AHBRSTR_GPIODRST   RCC_AHBRSTR_GPIODRST_Msk

GPIO port D reset

◆ RCC_AHBRSTR_GPIODRST_Msk

#define RCC_AHBRSTR_GPIODRST_Msk   (0x1U << RCC_AHBRSTR_GPIODRST_Pos)

0x00000008

◆ RCC_AHBRSTR_GPIODRST_Pos

#define RCC_AHBRSTR_GPIODRST_Pos   (3U)

◆ RCC_AHBRSTR_GPIOERST

#define RCC_AHBRSTR_GPIOERST   RCC_AHBRSTR_GPIOERST_Msk

GPIO port E reset

◆ RCC_AHBRSTR_GPIOERST_Msk

#define RCC_AHBRSTR_GPIOERST_Msk   (0x1U << RCC_AHBRSTR_GPIOERST_Pos)

0x00000010

◆ RCC_AHBRSTR_GPIOERST_Pos

#define RCC_AHBRSTR_GPIOERST_Pos   (4U)

◆ RCC_AHBRSTR_GPIOFRST

#define RCC_AHBRSTR_GPIOFRST   RCC_AHBRSTR_GPIOFRST_Msk

GPIO port F reset

◆ RCC_AHBRSTR_GPIOFRST_Msk

#define RCC_AHBRSTR_GPIOFRST_Msk   (0x1U << RCC_AHBRSTR_GPIOFRST_Pos)

0x00000040

◆ RCC_AHBRSTR_GPIOFRST_Pos

#define RCC_AHBRSTR_GPIOFRST_Pos   (6U)

◆ RCC_AHBRSTR_GPIOGRST

#define RCC_AHBRSTR_GPIOGRST   RCC_AHBRSTR_GPIOGRST_Msk

GPIO port G reset

◆ RCC_AHBRSTR_GPIOGRST_Msk

#define RCC_AHBRSTR_GPIOGRST_Msk   (0x1U << RCC_AHBRSTR_GPIOGRST_Pos)

0x00000080

◆ RCC_AHBRSTR_GPIOGRST_Pos

#define RCC_AHBRSTR_GPIOGRST_Pos   (7U)

◆ RCC_AHBRSTR_GPIOHRST

#define RCC_AHBRSTR_GPIOHRST   RCC_AHBRSTR_GPIOHRST_Msk

GPIO port H reset

◆ RCC_AHBRSTR_GPIOHRST_Msk

#define RCC_AHBRSTR_GPIOHRST_Msk   (0x1U << RCC_AHBRSTR_GPIOHRST_Pos)

0x00000020

◆ RCC_AHBRSTR_GPIOHRST_Pos

#define RCC_AHBRSTR_GPIOHRST_Pos   (5U)

◆ RCC_APB1ENR_COMPEN

#define RCC_APB1ENR_COMPEN   RCC_APB1ENR_COMPEN_Msk

Comparator interface clock enable

◆ RCC_APB1ENR_COMPEN_Msk

#define RCC_APB1ENR_COMPEN_Msk   (0x1U << RCC_APB1ENR_COMPEN_Pos)

0x80000000

◆ RCC_APB1ENR_COMPEN_Pos

#define RCC_APB1ENR_COMPEN_Pos   (31U)

◆ RCC_APB1ENR_DACEN

#define RCC_APB1ENR_DACEN   RCC_APB1ENR_DACEN_Msk

DAC interface clock enable

◆ RCC_APB1ENR_DACEN_Msk

#define RCC_APB1ENR_DACEN_Msk   (0x1U << RCC_APB1ENR_DACEN_Pos)

0x20000000

◆ RCC_APB1ENR_DACEN_Pos

#define RCC_APB1ENR_DACEN_Pos   (29U)

◆ RCC_APB1ENR_I2C1EN

#define RCC_APB1ENR_I2C1EN   RCC_APB1ENR_I2C1EN_Msk

I2C 1 clock enable

◆ RCC_APB1ENR_I2C1EN_Msk

#define RCC_APB1ENR_I2C1EN_Msk   (0x1U << RCC_APB1ENR_I2C1EN_Pos)

0x00200000

◆ RCC_APB1ENR_I2C1EN_Pos

#define RCC_APB1ENR_I2C1EN_Pos   (21U)

◆ RCC_APB1ENR_I2C2EN

#define RCC_APB1ENR_I2C2EN   RCC_APB1ENR_I2C2EN_Msk

I2C 2 clock enable

◆ RCC_APB1ENR_I2C2EN_Msk

#define RCC_APB1ENR_I2C2EN_Msk   (0x1U << RCC_APB1ENR_I2C2EN_Pos)

0x00400000

◆ RCC_APB1ENR_I2C2EN_Pos

#define RCC_APB1ENR_I2C2EN_Pos   (22U)

◆ RCC_APB1ENR_LCDEN

#define RCC_APB1ENR_LCDEN   RCC_APB1ENR_LCDEN_Msk

LCD clock enable

◆ RCC_APB1ENR_LCDEN_Msk

#define RCC_APB1ENR_LCDEN_Msk   (0x1U << RCC_APB1ENR_LCDEN_Pos)

0x00000200

◆ RCC_APB1ENR_LCDEN_Pos

#define RCC_APB1ENR_LCDEN_Pos   (9U)

◆ RCC_APB1ENR_PWREN

#define RCC_APB1ENR_PWREN   RCC_APB1ENR_PWREN_Msk

Power interface clock enable

◆ RCC_APB1ENR_PWREN_Msk

#define RCC_APB1ENR_PWREN_Msk   (0x1U << RCC_APB1ENR_PWREN_Pos)

0x10000000

◆ RCC_APB1ENR_PWREN_Pos

#define RCC_APB1ENR_PWREN_Pos   (28U)

◆ RCC_APB1ENR_SPI2EN

#define RCC_APB1ENR_SPI2EN   RCC_APB1ENR_SPI2EN_Msk

SPI 2 clock enable

◆ RCC_APB1ENR_SPI2EN_Msk

#define RCC_APB1ENR_SPI2EN_Msk   (0x1U << RCC_APB1ENR_SPI2EN_Pos)

0x00004000

◆ RCC_APB1ENR_SPI2EN_Pos

#define RCC_APB1ENR_SPI2EN_Pos   (14U)

◆ RCC_APB1ENR_SPI3EN

#define RCC_APB1ENR_SPI3EN   RCC_APB1ENR_SPI3EN_Msk

SPI 3 clock enable

◆ RCC_APB1ENR_SPI3EN_Msk

#define RCC_APB1ENR_SPI3EN_Msk   (0x1U << RCC_APB1ENR_SPI3EN_Pos)

0x00008000

◆ RCC_APB1ENR_SPI3EN_Pos

#define RCC_APB1ENR_SPI3EN_Pos   (15U)

◆ RCC_APB1ENR_TIM2EN

#define RCC_APB1ENR_TIM2EN   RCC_APB1ENR_TIM2EN_Msk

Timer 2 clock enabled

◆ RCC_APB1ENR_TIM2EN_Msk

#define RCC_APB1ENR_TIM2EN_Msk   (0x1U << RCC_APB1ENR_TIM2EN_Pos)

0x00000001

◆ RCC_APB1ENR_TIM2EN_Pos

#define RCC_APB1ENR_TIM2EN_Pos   (0U)

◆ RCC_APB1ENR_TIM3EN

#define RCC_APB1ENR_TIM3EN   RCC_APB1ENR_TIM3EN_Msk

Timer 3 clock enable

◆ RCC_APB1ENR_TIM3EN_Msk

#define RCC_APB1ENR_TIM3EN_Msk   (0x1U << RCC_APB1ENR_TIM3EN_Pos)

0x00000002

◆ RCC_APB1ENR_TIM3EN_Pos

#define RCC_APB1ENR_TIM3EN_Pos   (1U)

◆ RCC_APB1ENR_TIM4EN

#define RCC_APB1ENR_TIM4EN   RCC_APB1ENR_TIM4EN_Msk

Timer 4 clock enable

◆ RCC_APB1ENR_TIM4EN_Msk

#define RCC_APB1ENR_TIM4EN_Msk   (0x1U << RCC_APB1ENR_TIM4EN_Pos)

0x00000004

◆ RCC_APB1ENR_TIM4EN_Pos

#define RCC_APB1ENR_TIM4EN_Pos   (2U)

◆ RCC_APB1ENR_TIM5EN

#define RCC_APB1ENR_TIM5EN   RCC_APB1ENR_TIM5EN_Msk

Timer 5 clock enable

◆ RCC_APB1ENR_TIM5EN_Msk

#define RCC_APB1ENR_TIM5EN_Msk   (0x1U << RCC_APB1ENR_TIM5EN_Pos)

0x00000008

◆ RCC_APB1ENR_TIM5EN_Pos

#define RCC_APB1ENR_TIM5EN_Pos   (3U)

◆ RCC_APB1ENR_TIM6EN

#define RCC_APB1ENR_TIM6EN   RCC_APB1ENR_TIM6EN_Msk

Timer 6 clock enable

◆ RCC_APB1ENR_TIM6EN_Msk

#define RCC_APB1ENR_TIM6EN_Msk   (0x1U << RCC_APB1ENR_TIM6EN_Pos)

0x00000010

◆ RCC_APB1ENR_TIM6EN_Pos

#define RCC_APB1ENR_TIM6EN_Pos   (4U)

◆ RCC_APB1ENR_TIM7EN

#define RCC_APB1ENR_TIM7EN   RCC_APB1ENR_TIM7EN_Msk

Timer 7 clock enable

◆ RCC_APB1ENR_TIM7EN_Msk

#define RCC_APB1ENR_TIM7EN_Msk   (0x1U << RCC_APB1ENR_TIM7EN_Pos)

0x00000020

◆ RCC_APB1ENR_TIM7EN_Pos

#define RCC_APB1ENR_TIM7EN_Pos   (5U)

◆ RCC_APB1ENR_UART4EN

#define RCC_APB1ENR_UART4EN   RCC_APB1ENR_UART4EN_Msk

UART 4 clock enable

◆ RCC_APB1ENR_UART4EN_Msk

#define RCC_APB1ENR_UART4EN_Msk   (0x1U << RCC_APB1ENR_UART4EN_Pos)

0x00080000

◆ RCC_APB1ENR_UART4EN_Pos

#define RCC_APB1ENR_UART4EN_Pos   (19U)

◆ RCC_APB1ENR_UART5EN

#define RCC_APB1ENR_UART5EN   RCC_APB1ENR_UART5EN_Msk

UART 5 clock enable

◆ RCC_APB1ENR_UART5EN_Msk

#define RCC_APB1ENR_UART5EN_Msk   (0x1U << RCC_APB1ENR_UART5EN_Pos)

0x00100000

◆ RCC_APB1ENR_UART5EN_Pos

#define RCC_APB1ENR_UART5EN_Pos   (20U)

◆ RCC_APB1ENR_USART2EN

#define RCC_APB1ENR_USART2EN   RCC_APB1ENR_USART2EN_Msk

USART 2 clock enable

◆ RCC_APB1ENR_USART2EN_Msk

#define RCC_APB1ENR_USART2EN_Msk   (0x1U << RCC_APB1ENR_USART2EN_Pos)

0x00020000

◆ RCC_APB1ENR_USART2EN_Pos

#define RCC_APB1ENR_USART2EN_Pos   (17U)

◆ RCC_APB1ENR_USART3EN

#define RCC_APB1ENR_USART3EN   RCC_APB1ENR_USART3EN_Msk

USART 3 clock enable

◆ RCC_APB1ENR_USART3EN_Msk

#define RCC_APB1ENR_USART3EN_Msk   (0x1U << RCC_APB1ENR_USART3EN_Pos)

0x00040000

◆ RCC_APB1ENR_USART3EN_Pos

#define RCC_APB1ENR_USART3EN_Pos   (18U)

◆ RCC_APB1ENR_USBEN

#define RCC_APB1ENR_USBEN   RCC_APB1ENR_USBEN_Msk

USB clock enable

◆ RCC_APB1ENR_USBEN_Msk

#define RCC_APB1ENR_USBEN_Msk   (0x1U << RCC_APB1ENR_USBEN_Pos)

0x00800000

◆ RCC_APB1ENR_USBEN_Pos

#define RCC_APB1ENR_USBEN_Pos   (23U)

◆ RCC_APB1ENR_WWDGEN

#define RCC_APB1ENR_WWDGEN   RCC_APB1ENR_WWDGEN_Msk

Window Watchdog clock enable

◆ RCC_APB1ENR_WWDGEN_Msk

#define RCC_APB1ENR_WWDGEN_Msk   (0x1U << RCC_APB1ENR_WWDGEN_Pos)

0x00000800

◆ RCC_APB1ENR_WWDGEN_Pos

#define RCC_APB1ENR_WWDGEN_Pos   (11U)

◆ RCC_APB1LPENR_COMPLPEN

#define RCC_APB1LPENR_COMPLPEN   RCC_APB1LPENR_COMPLPEN_Msk

Comparator interface clock enabled in sleep mode

◆ RCC_APB1LPENR_COMPLPEN_Msk

#define RCC_APB1LPENR_COMPLPEN_Msk   (0x1U << RCC_APB1LPENR_COMPLPEN_Pos)

0x80000000

◆ RCC_APB1LPENR_COMPLPEN_Pos

#define RCC_APB1LPENR_COMPLPEN_Pos   (31U)

◆ RCC_APB1LPENR_DACLPEN

#define RCC_APB1LPENR_DACLPEN   RCC_APB1LPENR_DACLPEN_Msk

DAC interface clock enabled in sleep mode

◆ RCC_APB1LPENR_DACLPEN_Msk

#define RCC_APB1LPENR_DACLPEN_Msk   (0x1U << RCC_APB1LPENR_DACLPEN_Pos)

0x20000000

◆ RCC_APB1LPENR_DACLPEN_Pos

#define RCC_APB1LPENR_DACLPEN_Pos   (29U)

◆ RCC_APB1LPENR_I2C1LPEN

#define RCC_APB1LPENR_I2C1LPEN   RCC_APB1LPENR_I2C1LPEN_Msk

I2C 1 clock enabled in sleep mode

◆ RCC_APB1LPENR_I2C1LPEN_Msk

#define RCC_APB1LPENR_I2C1LPEN_Msk   (0x1U << RCC_APB1LPENR_I2C1LPEN_Pos)

0x00200000

◆ RCC_APB1LPENR_I2C1LPEN_Pos

#define RCC_APB1LPENR_I2C1LPEN_Pos   (21U)

◆ RCC_APB1LPENR_I2C2LPEN

#define RCC_APB1LPENR_I2C2LPEN   RCC_APB1LPENR_I2C2LPEN_Msk

I2C 2 clock enabled in sleep mode

◆ RCC_APB1LPENR_I2C2LPEN_Msk

#define RCC_APB1LPENR_I2C2LPEN_Msk   (0x1U << RCC_APB1LPENR_I2C2LPEN_Pos)

0x00400000

◆ RCC_APB1LPENR_I2C2LPEN_Pos

#define RCC_APB1LPENR_I2C2LPEN_Pos   (22U)

◆ RCC_APB1LPENR_LCDLPEN

#define RCC_APB1LPENR_LCDLPEN   RCC_APB1LPENR_LCDLPEN_Msk

LCD clock enabled in sleep mode

◆ RCC_APB1LPENR_LCDLPEN_Msk

#define RCC_APB1LPENR_LCDLPEN_Msk   (0x1U << RCC_APB1LPENR_LCDLPEN_Pos)

0x00000200

◆ RCC_APB1LPENR_LCDLPEN_Pos

#define RCC_APB1LPENR_LCDLPEN_Pos   (9U)

◆ RCC_APB1LPENR_PWRLPEN

#define RCC_APB1LPENR_PWRLPEN   RCC_APB1LPENR_PWRLPEN_Msk

Power interface clock enabled in sleep mode

◆ RCC_APB1LPENR_PWRLPEN_Msk

#define RCC_APB1LPENR_PWRLPEN_Msk   (0x1U << RCC_APB1LPENR_PWRLPEN_Pos)

0x10000000

◆ RCC_APB1LPENR_PWRLPEN_Pos

#define RCC_APB1LPENR_PWRLPEN_Pos   (28U)

◆ RCC_APB1LPENR_SPI2LPEN

#define RCC_APB1LPENR_SPI2LPEN   RCC_APB1LPENR_SPI2LPEN_Msk

SPI 2 clock enabled in sleep mode

◆ RCC_APB1LPENR_SPI2LPEN_Msk

#define RCC_APB1LPENR_SPI2LPEN_Msk   (0x1U << RCC_APB1LPENR_SPI2LPEN_Pos)

0x00004000

◆ RCC_APB1LPENR_SPI2LPEN_Pos

#define RCC_APB1LPENR_SPI2LPEN_Pos   (14U)

◆ RCC_APB1LPENR_SPI3LPEN

#define RCC_APB1LPENR_SPI3LPEN   RCC_APB1LPENR_SPI3LPEN_Msk

SPI 3 clock enabled in sleep mode

◆ RCC_APB1LPENR_SPI3LPEN_Msk

#define RCC_APB1LPENR_SPI3LPEN_Msk   (0x1U << RCC_APB1LPENR_SPI3LPEN_Pos)

0x00008000

◆ RCC_APB1LPENR_SPI3LPEN_Pos

#define RCC_APB1LPENR_SPI3LPEN_Pos   (15U)

◆ RCC_APB1LPENR_TIM2LPEN

#define RCC_APB1LPENR_TIM2LPEN   RCC_APB1LPENR_TIM2LPEN_Msk

Timer 2 clock enabled in sleep mode

◆ RCC_APB1LPENR_TIM2LPEN_Msk

#define RCC_APB1LPENR_TIM2LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM2LPEN_Pos)

0x00000001

◆ RCC_APB1LPENR_TIM2LPEN_Pos

#define RCC_APB1LPENR_TIM2LPEN_Pos   (0U)

◆ RCC_APB1LPENR_TIM3LPEN

#define RCC_APB1LPENR_TIM3LPEN   RCC_APB1LPENR_TIM3LPEN_Msk

Timer 3 clock enabled in sleep mode

◆ RCC_APB1LPENR_TIM3LPEN_Msk

#define RCC_APB1LPENR_TIM3LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM3LPEN_Pos)

0x00000002

◆ RCC_APB1LPENR_TIM3LPEN_Pos

#define RCC_APB1LPENR_TIM3LPEN_Pos   (1U)

◆ RCC_APB1LPENR_TIM4LPEN

#define RCC_APB1LPENR_TIM4LPEN   RCC_APB1LPENR_TIM4LPEN_Msk

Timer 4 clock enabled in sleep mode

◆ RCC_APB1LPENR_TIM4LPEN_Msk

#define RCC_APB1LPENR_TIM4LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM4LPEN_Pos)

0x00000004

◆ RCC_APB1LPENR_TIM4LPEN_Pos

#define RCC_APB1LPENR_TIM4LPEN_Pos   (2U)

◆ RCC_APB1LPENR_TIM5LPEN

#define RCC_APB1LPENR_TIM5LPEN   RCC_APB1LPENR_TIM5LPEN_Msk

Timer 5 clock enabled in sleep mode

◆ RCC_APB1LPENR_TIM5LPEN_Msk

#define RCC_APB1LPENR_TIM5LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM5LPEN_Pos)

0x00000008

◆ RCC_APB1LPENR_TIM5LPEN_Pos

#define RCC_APB1LPENR_TIM5LPEN_Pos   (3U)

◆ RCC_APB1LPENR_TIM6LPEN

#define RCC_APB1LPENR_TIM6LPEN   RCC_APB1LPENR_TIM6LPEN_Msk

Timer 6 clock enabled in sleep mode

◆ RCC_APB1LPENR_TIM6LPEN_Msk

#define RCC_APB1LPENR_TIM6LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM6LPEN_Pos)

0x00000010

◆ RCC_APB1LPENR_TIM6LPEN_Pos

#define RCC_APB1LPENR_TIM6LPEN_Pos   (4U)

◆ RCC_APB1LPENR_TIM7LPEN

#define RCC_APB1LPENR_TIM7LPEN   RCC_APB1LPENR_TIM7LPEN_Msk

Timer 7 clock enabled in sleep mode

◆ RCC_APB1LPENR_TIM7LPEN_Msk

#define RCC_APB1LPENR_TIM7LPEN_Msk   (0x1U << RCC_APB1LPENR_TIM7LPEN_Pos)

0x00000020

◆ RCC_APB1LPENR_TIM7LPEN_Pos

#define RCC_APB1LPENR_TIM7LPEN_Pos   (5U)

◆ RCC_APB1LPENR_UART4LPEN

#define RCC_APB1LPENR_UART4LPEN   RCC_APB1LPENR_UART4LPEN_Msk

UART 4 clock enabled in sleep mode

◆ RCC_APB1LPENR_UART4LPEN_Msk

#define RCC_APB1LPENR_UART4LPEN_Msk   (0x1U << RCC_APB1LPENR_UART4LPEN_Pos)

0x00080000

◆ RCC_APB1LPENR_UART4LPEN_Pos

#define RCC_APB1LPENR_UART4LPEN_Pos   (19U)

◆ RCC_APB1LPENR_UART5LPEN

#define RCC_APB1LPENR_UART5LPEN   RCC_APB1LPENR_UART5LPEN_Msk

UART 5 clock enabled in sleep mode

◆ RCC_APB1LPENR_UART5LPEN_Msk

#define RCC_APB1LPENR_UART5LPEN_Msk   (0x1U << RCC_APB1LPENR_UART5LPEN_Pos)

0x00100000

◆ RCC_APB1LPENR_UART5LPEN_Pos

#define RCC_APB1LPENR_UART5LPEN_Pos   (20U)

◆ RCC_APB1LPENR_USART2LPEN

#define RCC_APB1LPENR_USART2LPEN   RCC_APB1LPENR_USART2LPEN_Msk

USART 2 clock enabled in sleep mode

◆ RCC_APB1LPENR_USART2LPEN_Msk

#define RCC_APB1LPENR_USART2LPEN_Msk   (0x1U << RCC_APB1LPENR_USART2LPEN_Pos)

0x00020000

◆ RCC_APB1LPENR_USART2LPEN_Pos

#define RCC_APB1LPENR_USART2LPEN_Pos   (17U)

◆ RCC_APB1LPENR_USART3LPEN

#define RCC_APB1LPENR_USART3LPEN   RCC_APB1LPENR_USART3LPEN_Msk

USART 3 clock enabled in sleep mode

◆ RCC_APB1LPENR_USART3LPEN_Msk

#define RCC_APB1LPENR_USART3LPEN_Msk   (0x1U << RCC_APB1LPENR_USART3LPEN_Pos)

0x00040000

◆ RCC_APB1LPENR_USART3LPEN_Pos

#define RCC_APB1LPENR_USART3LPEN_Pos   (18U)

◆ RCC_APB1LPENR_USBLPEN

#define RCC_APB1LPENR_USBLPEN   RCC_APB1LPENR_USBLPEN_Msk

USB clock enabled in sleep mode

◆ RCC_APB1LPENR_USBLPEN_Msk

#define RCC_APB1LPENR_USBLPEN_Msk   (0x1U << RCC_APB1LPENR_USBLPEN_Pos)

0x00800000

◆ RCC_APB1LPENR_USBLPEN_Pos

#define RCC_APB1LPENR_USBLPEN_Pos   (23U)

◆ RCC_APB1LPENR_WWDGLPEN

#define RCC_APB1LPENR_WWDGLPEN   RCC_APB1LPENR_WWDGLPEN_Msk

Window Watchdog clock enabled in sleep mode

◆ RCC_APB1LPENR_WWDGLPEN_Msk

#define RCC_APB1LPENR_WWDGLPEN_Msk   (0x1U << RCC_APB1LPENR_WWDGLPEN_Pos)

0x00000800

◆ RCC_APB1LPENR_WWDGLPEN_Pos

#define RCC_APB1LPENR_WWDGLPEN_Pos   (11U)

◆ RCC_APB1RSTR_COMPRST

#define RCC_APB1RSTR_COMPRST   RCC_APB1RSTR_COMPRST_Msk

Comparator interface reset

◆ RCC_APB1RSTR_COMPRST_Msk

#define RCC_APB1RSTR_COMPRST_Msk   (0x1U << RCC_APB1RSTR_COMPRST_Pos)

0x80000000

◆ RCC_APB1RSTR_COMPRST_Pos

#define RCC_APB1RSTR_COMPRST_Pos   (31U)

◆ RCC_APB1RSTR_DACRST

#define RCC_APB1RSTR_DACRST   RCC_APB1RSTR_DACRST_Msk

DAC interface reset

◆ RCC_APB1RSTR_DACRST_Msk

#define RCC_APB1RSTR_DACRST_Msk   (0x1U << RCC_APB1RSTR_DACRST_Pos)

0x20000000

◆ RCC_APB1RSTR_DACRST_Pos

#define RCC_APB1RSTR_DACRST_Pos   (29U)

◆ RCC_APB1RSTR_I2C1RST

#define RCC_APB1RSTR_I2C1RST   RCC_APB1RSTR_I2C1RST_Msk

I2C 1 reset

◆ RCC_APB1RSTR_I2C1RST_Msk

#define RCC_APB1RSTR_I2C1RST_Msk   (0x1U << RCC_APB1RSTR_I2C1RST_Pos)

0x00200000

◆ RCC_APB1RSTR_I2C1RST_Pos

#define RCC_APB1RSTR_I2C1RST_Pos   (21U)

◆ RCC_APB1RSTR_I2C2RST

#define RCC_APB1RSTR_I2C2RST   RCC_APB1RSTR_I2C2RST_Msk

I2C 2 reset

◆ RCC_APB1RSTR_I2C2RST_Msk

#define RCC_APB1RSTR_I2C2RST_Msk   (0x1U << RCC_APB1RSTR_I2C2RST_Pos)

0x00400000

◆ RCC_APB1RSTR_I2C2RST_Pos

#define RCC_APB1RSTR_I2C2RST_Pos   (22U)

◆ RCC_APB1RSTR_LCDRST

#define RCC_APB1RSTR_LCDRST   RCC_APB1RSTR_LCDRST_Msk

LCD reset

◆ RCC_APB1RSTR_LCDRST_Msk

#define RCC_APB1RSTR_LCDRST_Msk   (0x1U << RCC_APB1RSTR_LCDRST_Pos)

0x00000200

◆ RCC_APB1RSTR_LCDRST_Pos

#define RCC_APB1RSTR_LCDRST_Pos   (9U)

◆ RCC_APB1RSTR_PWRRST

#define RCC_APB1RSTR_PWRRST   RCC_APB1RSTR_PWRRST_Msk

Power interface reset

◆ RCC_APB1RSTR_PWRRST_Msk

#define RCC_APB1RSTR_PWRRST_Msk   (0x1U << RCC_APB1RSTR_PWRRST_Pos)

0x10000000

◆ RCC_APB1RSTR_PWRRST_Pos

#define RCC_APB1RSTR_PWRRST_Pos   (28U)

◆ RCC_APB1RSTR_SPI2RST

#define RCC_APB1RSTR_SPI2RST   RCC_APB1RSTR_SPI2RST_Msk

SPI 2 reset

◆ RCC_APB1RSTR_SPI2RST_Msk

#define RCC_APB1RSTR_SPI2RST_Msk   (0x1U << RCC_APB1RSTR_SPI2RST_Pos)

0x00004000

◆ RCC_APB1RSTR_SPI2RST_Pos

#define RCC_APB1RSTR_SPI2RST_Pos   (14U)

◆ RCC_APB1RSTR_SPI3RST

#define RCC_APB1RSTR_SPI3RST   RCC_APB1RSTR_SPI3RST_Msk

SPI 3 reset

◆ RCC_APB1RSTR_SPI3RST_Msk

#define RCC_APB1RSTR_SPI3RST_Msk   (0x1U << RCC_APB1RSTR_SPI3RST_Pos)

0x00008000

◆ RCC_APB1RSTR_SPI3RST_Pos

#define RCC_APB1RSTR_SPI3RST_Pos   (15U)

◆ RCC_APB1RSTR_TIM2RST

#define RCC_APB1RSTR_TIM2RST   RCC_APB1RSTR_TIM2RST_Msk

Timer 2 reset

◆ RCC_APB1RSTR_TIM2RST_Msk

#define RCC_APB1RSTR_TIM2RST_Msk   (0x1U << RCC_APB1RSTR_TIM2RST_Pos)

0x00000001

◆ RCC_APB1RSTR_TIM2RST_Pos

#define RCC_APB1RSTR_TIM2RST_Pos   (0U)

◆ RCC_APB1RSTR_TIM3RST

#define RCC_APB1RSTR_TIM3RST   RCC_APB1RSTR_TIM3RST_Msk

Timer 3 reset

◆ RCC_APB1RSTR_TIM3RST_Msk

#define RCC_APB1RSTR_TIM3RST_Msk   (0x1U << RCC_APB1RSTR_TIM3RST_Pos)

0x00000002

◆ RCC_APB1RSTR_TIM3RST_Pos

#define RCC_APB1RSTR_TIM3RST_Pos   (1U)

◆ RCC_APB1RSTR_TIM4RST

#define RCC_APB1RSTR_TIM4RST   RCC_APB1RSTR_TIM4RST_Msk

Timer 4 reset

◆ RCC_APB1RSTR_TIM4RST_Msk

#define RCC_APB1RSTR_TIM4RST_Msk   (0x1U << RCC_APB1RSTR_TIM4RST_Pos)

0x00000004

◆ RCC_APB1RSTR_TIM4RST_Pos

#define RCC_APB1RSTR_TIM4RST_Pos   (2U)

◆ RCC_APB1RSTR_TIM5RST

#define RCC_APB1RSTR_TIM5RST   RCC_APB1RSTR_TIM5RST_Msk

Timer 5 reset

◆ RCC_APB1RSTR_TIM5RST_Msk

#define RCC_APB1RSTR_TIM5RST_Msk   (0x1U << RCC_APB1RSTR_TIM5RST_Pos)

0x00000008

◆ RCC_APB1RSTR_TIM5RST_Pos

#define RCC_APB1RSTR_TIM5RST_Pos   (3U)

◆ RCC_APB1RSTR_TIM6RST

#define RCC_APB1RSTR_TIM6RST   RCC_APB1RSTR_TIM6RST_Msk

Timer 6 reset

◆ RCC_APB1RSTR_TIM6RST_Msk

#define RCC_APB1RSTR_TIM6RST_Msk   (0x1U << RCC_APB1RSTR_TIM6RST_Pos)

0x00000010

◆ RCC_APB1RSTR_TIM6RST_Pos

#define RCC_APB1RSTR_TIM6RST_Pos   (4U)

◆ RCC_APB1RSTR_TIM7RST

#define RCC_APB1RSTR_TIM7RST   RCC_APB1RSTR_TIM7RST_Msk

Timer 7 reset

◆ RCC_APB1RSTR_TIM7RST_Msk

#define RCC_APB1RSTR_TIM7RST_Msk   (0x1U << RCC_APB1RSTR_TIM7RST_Pos)

0x00000020

◆ RCC_APB1RSTR_TIM7RST_Pos

#define RCC_APB1RSTR_TIM7RST_Pos   (5U)

◆ RCC_APB1RSTR_UART4RST

#define RCC_APB1RSTR_UART4RST   RCC_APB1RSTR_UART4RST_Msk

UART 4 reset

◆ RCC_APB1RSTR_UART4RST_Msk

#define RCC_APB1RSTR_UART4RST_Msk   (0x1U << RCC_APB1RSTR_UART4RST_Pos)

0x00080000

◆ RCC_APB1RSTR_UART4RST_Pos

#define RCC_APB1RSTR_UART4RST_Pos   (19U)

◆ RCC_APB1RSTR_UART5RST

#define RCC_APB1RSTR_UART5RST   RCC_APB1RSTR_UART5RST_Msk

UART 5 reset

◆ RCC_APB1RSTR_UART5RST_Msk

#define RCC_APB1RSTR_UART5RST_Msk   (0x1U << RCC_APB1RSTR_UART5RST_Pos)

0x00100000

◆ RCC_APB1RSTR_UART5RST_Pos

#define RCC_APB1RSTR_UART5RST_Pos   (20U)

◆ RCC_APB1RSTR_USART2RST

#define RCC_APB1RSTR_USART2RST   RCC_APB1RSTR_USART2RST_Msk

USART 2 reset

◆ RCC_APB1RSTR_USART2RST_Msk

#define RCC_APB1RSTR_USART2RST_Msk   (0x1U << RCC_APB1RSTR_USART2RST_Pos)

0x00020000

◆ RCC_APB1RSTR_USART2RST_Pos

#define RCC_APB1RSTR_USART2RST_Pos   (17U)

◆ RCC_APB1RSTR_USART3RST

#define RCC_APB1RSTR_USART3RST   RCC_APB1RSTR_USART3RST_Msk

USART 3 reset

◆ RCC_APB1RSTR_USART3RST_Msk

#define RCC_APB1RSTR_USART3RST_Msk   (0x1U << RCC_APB1RSTR_USART3RST_Pos)

0x00040000

◆ RCC_APB1RSTR_USART3RST_Pos

#define RCC_APB1RSTR_USART3RST_Pos   (18U)

◆ RCC_APB1RSTR_USBRST

#define RCC_APB1RSTR_USBRST   RCC_APB1RSTR_USBRST_Msk

USB reset

◆ RCC_APB1RSTR_USBRST_Msk

#define RCC_APB1RSTR_USBRST_Msk   (0x1U << RCC_APB1RSTR_USBRST_Pos)

0x00800000

◆ RCC_APB1RSTR_USBRST_Pos

#define RCC_APB1RSTR_USBRST_Pos   (23U)

◆ RCC_APB1RSTR_WWDGRST

#define RCC_APB1RSTR_WWDGRST   RCC_APB1RSTR_WWDGRST_Msk

Window Watchdog reset

◆ RCC_APB1RSTR_WWDGRST_Msk

#define RCC_APB1RSTR_WWDGRST_Msk   (0x1U << RCC_APB1RSTR_WWDGRST_Pos)

0x00000800

◆ RCC_APB1RSTR_WWDGRST_Pos

#define RCC_APB1RSTR_WWDGRST_Pos   (11U)

◆ RCC_APB2ENR_ADC1EN

#define RCC_APB2ENR_ADC1EN   RCC_APB2ENR_ADC1EN_Msk

ADC1 clock enable

◆ RCC_APB2ENR_ADC1EN_Msk

#define RCC_APB2ENR_ADC1EN_Msk   (0x1U << RCC_APB2ENR_ADC1EN_Pos)

0x00000200

◆ RCC_APB2ENR_ADC1EN_Pos

#define RCC_APB2ENR_ADC1EN_Pos   (9U)

◆ RCC_APB2ENR_SPI1EN

#define RCC_APB2ENR_SPI1EN   RCC_APB2ENR_SPI1EN_Msk

SPI1 clock enable

◆ RCC_APB2ENR_SPI1EN_Msk

#define RCC_APB2ENR_SPI1EN_Msk   (0x1U << RCC_APB2ENR_SPI1EN_Pos)

0x00001000

◆ RCC_APB2ENR_SPI1EN_Pos

#define RCC_APB2ENR_SPI1EN_Pos   (12U)

◆ RCC_APB2ENR_SYSCFGEN

#define RCC_APB2ENR_SYSCFGEN   RCC_APB2ENR_SYSCFGEN_Msk

System Configuration SYSCFG clock enable

◆ RCC_APB2ENR_SYSCFGEN_Msk

#define RCC_APB2ENR_SYSCFGEN_Msk   (0x1U << RCC_APB2ENR_SYSCFGEN_Pos)

0x00000001

◆ RCC_APB2ENR_SYSCFGEN_Pos

#define RCC_APB2ENR_SYSCFGEN_Pos   (0U)

◆ RCC_APB2ENR_TIM10EN

#define RCC_APB2ENR_TIM10EN   RCC_APB2ENR_TIM10EN_Msk

TIM10 interface clock enable

◆ RCC_APB2ENR_TIM10EN_Msk

#define RCC_APB2ENR_TIM10EN_Msk   (0x1U << RCC_APB2ENR_TIM10EN_Pos)

0x00000008

◆ RCC_APB2ENR_TIM10EN_Pos

#define RCC_APB2ENR_TIM10EN_Pos   (3U)

◆ RCC_APB2ENR_TIM11EN

#define RCC_APB2ENR_TIM11EN   RCC_APB2ENR_TIM11EN_Msk

TIM11 Timer clock enable

◆ RCC_APB2ENR_TIM11EN_Msk

#define RCC_APB2ENR_TIM11EN_Msk   (0x1U << RCC_APB2ENR_TIM11EN_Pos)

0x00000010

◆ RCC_APB2ENR_TIM11EN_Pos

#define RCC_APB2ENR_TIM11EN_Pos   (4U)

◆ RCC_APB2ENR_TIM9EN

#define RCC_APB2ENR_TIM9EN   RCC_APB2ENR_TIM9EN_Msk

TIM9 interface clock enable

◆ RCC_APB2ENR_TIM9EN_Msk

#define RCC_APB2ENR_TIM9EN_Msk   (0x1U << RCC_APB2ENR_TIM9EN_Pos)

0x00000004

◆ RCC_APB2ENR_TIM9EN_Pos

#define RCC_APB2ENR_TIM9EN_Pos   (2U)

◆ RCC_APB2ENR_USART1EN

#define RCC_APB2ENR_USART1EN   RCC_APB2ENR_USART1EN_Msk

USART1 clock enable

◆ RCC_APB2ENR_USART1EN_Msk

#define RCC_APB2ENR_USART1EN_Msk   (0x1U << RCC_APB2ENR_USART1EN_Pos)

0x00004000

◆ RCC_APB2ENR_USART1EN_Pos

#define RCC_APB2ENR_USART1EN_Pos   (14U)

◆ RCC_APB2LPENR_ADC1LPEN

#define RCC_APB2LPENR_ADC1LPEN   RCC_APB2LPENR_ADC1LPEN_Msk

ADC1 clock enabled in sleep mode

◆ RCC_APB2LPENR_ADC1LPEN_Msk

#define RCC_APB2LPENR_ADC1LPEN_Msk   (0x1U << RCC_APB2LPENR_ADC1LPEN_Pos)

0x00000200

◆ RCC_APB2LPENR_ADC1LPEN_Pos

#define RCC_APB2LPENR_ADC1LPEN_Pos   (9U)

◆ RCC_APB2LPENR_SPI1LPEN

#define RCC_APB2LPENR_SPI1LPEN   RCC_APB2LPENR_SPI1LPEN_Msk

SPI1 clock enabled in sleep mode

◆ RCC_APB2LPENR_SPI1LPEN_Msk

#define RCC_APB2LPENR_SPI1LPEN_Msk   (0x1U << RCC_APB2LPENR_SPI1LPEN_Pos)

0x00001000

◆ RCC_APB2LPENR_SPI1LPEN_Pos

#define RCC_APB2LPENR_SPI1LPEN_Pos   (12U)

◆ RCC_APB2LPENR_SYSCFGLPEN

#define RCC_APB2LPENR_SYSCFGLPEN   RCC_APB2LPENR_SYSCFGLPEN_Msk

System Configuration SYSCFG clock enabled in sleep mode

◆ RCC_APB2LPENR_SYSCFGLPEN_Msk

#define RCC_APB2LPENR_SYSCFGLPEN_Msk   (0x1U << RCC_APB2LPENR_SYSCFGLPEN_Pos)

0x00000001

◆ RCC_APB2LPENR_SYSCFGLPEN_Pos

#define RCC_APB2LPENR_SYSCFGLPEN_Pos   (0U)

◆ RCC_APB2LPENR_TIM10LPEN

#define RCC_APB2LPENR_TIM10LPEN   RCC_APB2LPENR_TIM10LPEN_Msk

TIM10 interface clock enabled in sleep mode

◆ RCC_APB2LPENR_TIM10LPEN_Msk

#define RCC_APB2LPENR_TIM10LPEN_Msk   (0x1U << RCC_APB2LPENR_TIM10LPEN_Pos)

0x00000008

◆ RCC_APB2LPENR_TIM10LPEN_Pos

#define RCC_APB2LPENR_TIM10LPEN_Pos   (3U)

◆ RCC_APB2LPENR_TIM11LPEN

#define RCC_APB2LPENR_TIM11LPEN   RCC_APB2LPENR_TIM11LPEN_Msk

TIM11 Timer clock enabled in sleep mode

◆ RCC_APB2LPENR_TIM11LPEN_Msk

#define RCC_APB2LPENR_TIM11LPEN_Msk   (0x1U << RCC_APB2LPENR_TIM11LPEN_Pos)

0x00000010

◆ RCC_APB2LPENR_TIM11LPEN_Pos

#define RCC_APB2LPENR_TIM11LPEN_Pos   (4U)

◆ RCC_APB2LPENR_TIM9LPEN

#define RCC_APB2LPENR_TIM9LPEN   RCC_APB2LPENR_TIM9LPEN_Msk

TIM9 interface clock enabled in sleep mode

◆ RCC_APB2LPENR_TIM9LPEN_Msk

#define RCC_APB2LPENR_TIM9LPEN_Msk   (0x1U << RCC_APB2LPENR_TIM9LPEN_Pos)

0x00000004

◆ RCC_APB2LPENR_TIM9LPEN_Pos

#define RCC_APB2LPENR_TIM9LPEN_Pos   (2U)

◆ RCC_APB2LPENR_USART1LPEN

#define RCC_APB2LPENR_USART1LPEN   RCC_APB2LPENR_USART1LPEN_Msk

USART1 clock enabled in sleep mode

◆ RCC_APB2LPENR_USART1LPEN_Msk

#define RCC_APB2LPENR_USART1LPEN_Msk   (0x1U << RCC_APB2LPENR_USART1LPEN_Pos)

0x00004000

◆ RCC_APB2LPENR_USART1LPEN_Pos

#define RCC_APB2LPENR_USART1LPEN_Pos   (14U)

◆ RCC_APB2RSTR_ADC1RST

#define RCC_APB2RSTR_ADC1RST   RCC_APB2RSTR_ADC1RST_Msk

ADC1 reset

◆ RCC_APB2RSTR_ADC1RST_Msk

#define RCC_APB2RSTR_ADC1RST_Msk   (0x1U << RCC_APB2RSTR_ADC1RST_Pos)

0x00000200

◆ RCC_APB2RSTR_ADC1RST_Pos

#define RCC_APB2RSTR_ADC1RST_Pos   (9U)

◆ RCC_APB2RSTR_SPI1RST

#define RCC_APB2RSTR_SPI1RST   RCC_APB2RSTR_SPI1RST_Msk

SPI1 reset

◆ RCC_APB2RSTR_SPI1RST_Msk

#define RCC_APB2RSTR_SPI1RST_Msk   (0x1U << RCC_APB2RSTR_SPI1RST_Pos)

0x00001000

◆ RCC_APB2RSTR_SPI1RST_Pos

#define RCC_APB2RSTR_SPI1RST_Pos   (12U)

◆ RCC_APB2RSTR_SYSCFGRST

#define RCC_APB2RSTR_SYSCFGRST   RCC_APB2RSTR_SYSCFGRST_Msk

System Configuration SYSCFG reset

◆ RCC_APB2RSTR_SYSCFGRST_Msk

#define RCC_APB2RSTR_SYSCFGRST_Msk   (0x1U << RCC_APB2RSTR_SYSCFGRST_Pos)

0x00000001

◆ RCC_APB2RSTR_SYSCFGRST_Pos

#define RCC_APB2RSTR_SYSCFGRST_Pos   (0U)

◆ RCC_APB2RSTR_TIM10RST

#define RCC_APB2RSTR_TIM10RST   RCC_APB2RSTR_TIM10RST_Msk

TIM10 reset

◆ RCC_APB2RSTR_TIM10RST_Msk

#define RCC_APB2RSTR_TIM10RST_Msk   (0x1U << RCC_APB2RSTR_TIM10RST_Pos)

0x00000008

◆ RCC_APB2RSTR_TIM10RST_Pos

#define RCC_APB2RSTR_TIM10RST_Pos   (3U)

◆ RCC_APB2RSTR_TIM11RST

#define RCC_APB2RSTR_TIM11RST   RCC_APB2RSTR_TIM11RST_Msk

TIM11 reset

◆ RCC_APB2RSTR_TIM11RST_Msk

#define RCC_APB2RSTR_TIM11RST_Msk   (0x1U << RCC_APB2RSTR_TIM11RST_Pos)

0x00000010

◆ RCC_APB2RSTR_TIM11RST_Pos

#define RCC_APB2RSTR_TIM11RST_Pos   (4U)

◆ RCC_APB2RSTR_TIM9RST

#define RCC_APB2RSTR_TIM9RST   RCC_APB2RSTR_TIM9RST_Msk

TIM9 reset

◆ RCC_APB2RSTR_TIM9RST_Msk

#define RCC_APB2RSTR_TIM9RST_Msk   (0x1U << RCC_APB2RSTR_TIM9RST_Pos)

0x00000004

◆ RCC_APB2RSTR_TIM9RST_Pos

#define RCC_APB2RSTR_TIM9RST_Pos   (2U)

◆ RCC_APB2RSTR_USART1RST

#define RCC_APB2RSTR_USART1RST   RCC_APB2RSTR_USART1RST_Msk

USART1 reset

◆ RCC_APB2RSTR_USART1RST_Msk

#define RCC_APB2RSTR_USART1RST_Msk   (0x1U << RCC_APB2RSTR_USART1RST_Pos)

0x00004000

◆ RCC_APB2RSTR_USART1RST_Pos

#define RCC_APB2RSTR_USART1RST_Pos   (14U)

◆ RCC_CFGR_HPRE

#define RCC_CFGR_HPRE   RCC_CFGR_HPRE_Msk

HPRE[3:0] bits (AHB prescaler)

◆ RCC_CFGR_HPRE_0

#define RCC_CFGR_HPRE_0   (0x1U << RCC_CFGR_HPRE_Pos)

0x00000010

◆ RCC_CFGR_HPRE_1

#define RCC_CFGR_HPRE_1   (0x2U << RCC_CFGR_HPRE_Pos)

0x00000020

◆ RCC_CFGR_HPRE_2

#define RCC_CFGR_HPRE_2   (0x4U << RCC_CFGR_HPRE_Pos)

0x00000040

◆ RCC_CFGR_HPRE_3

#define RCC_CFGR_HPRE_3   (0x8U << RCC_CFGR_HPRE_Pos)

0x00000080 HPRE configuration

◆ RCC_CFGR_HPRE_DIV1

#define RCC_CFGR_HPRE_DIV1   (0x00000000U)

SYSCLK not divided

◆ RCC_CFGR_HPRE_DIV128

#define RCC_CFGR_HPRE_DIV128   (0x000000D0U)

SYSCLK divided by 128

◆ RCC_CFGR_HPRE_DIV16

#define RCC_CFGR_HPRE_DIV16   (0x000000B0U)

SYSCLK divided by 16

◆ RCC_CFGR_HPRE_DIV2

#define RCC_CFGR_HPRE_DIV2   (0x00000080U)

SYSCLK divided by 2

◆ RCC_CFGR_HPRE_DIV256

#define RCC_CFGR_HPRE_DIV256   (0x000000E0U)

SYSCLK divided by 256

◆ RCC_CFGR_HPRE_DIV4

#define RCC_CFGR_HPRE_DIV4   (0x00000090U)

SYSCLK divided by 4

◆ RCC_CFGR_HPRE_DIV512

#define RCC_CFGR_HPRE_DIV512   (0x000000F0U)

SYSCLK divided by 512

◆ RCC_CFGR_HPRE_DIV64

#define RCC_CFGR_HPRE_DIV64   (0x000000C0U)

SYSCLK divided by 64

◆ RCC_CFGR_HPRE_DIV8

#define RCC_CFGR_HPRE_DIV8   (0x000000A0U)

SYSCLK divided by 8

◆ RCC_CFGR_HPRE_Msk

#define RCC_CFGR_HPRE_Msk   (0xFU << RCC_CFGR_HPRE_Pos)

0x000000F0

◆ RCC_CFGR_HPRE_Pos

#define RCC_CFGR_HPRE_Pos   (4U)

◆ RCC_CFGR_MCO_DIV1

#define RCC_CFGR_MCO_DIV1   RCC_CFGR_MCOPRE_DIV1

◆ RCC_CFGR_MCO_DIV16

#define RCC_CFGR_MCO_DIV16   RCC_CFGR_MCOPRE_DIV16

◆ RCC_CFGR_MCO_DIV2

#define RCC_CFGR_MCO_DIV2   RCC_CFGR_MCOPRE_DIV2

◆ RCC_CFGR_MCO_DIV4

#define RCC_CFGR_MCO_DIV4   RCC_CFGR_MCOPRE_DIV4

◆ RCC_CFGR_MCO_DIV8

#define RCC_CFGR_MCO_DIV8   RCC_CFGR_MCOPRE_DIV8

◆ RCC_CFGR_MCO_HSE

#define RCC_CFGR_MCO_HSE   RCC_CFGR_MCOSEL_HSE

◆ RCC_CFGR_MCO_HSI

#define RCC_CFGR_MCO_HSI   RCC_CFGR_MCOSEL_HSI

◆ RCC_CFGR_MCO_LSE

#define RCC_CFGR_MCO_LSE   RCC_CFGR_MCOSEL_LSE

****************** Bit definition for RCC_CIR register

◆ RCC_CFGR_MCO_LSI

#define RCC_CFGR_MCO_LSI   RCC_CFGR_MCOSEL_LSI

◆ RCC_CFGR_MCO_MSI

#define RCC_CFGR_MCO_MSI   RCC_CFGR_MCOSEL_MSI

◆ RCC_CFGR_MCO_NOCLOCK

#define RCC_CFGR_MCO_NOCLOCK   RCC_CFGR_MCOSEL_NOCLOCK

◆ RCC_CFGR_MCO_PLL

#define RCC_CFGR_MCO_PLL   RCC_CFGR_MCOSEL_PLL

◆ RCC_CFGR_MCO_SYSCLK

#define RCC_CFGR_MCO_SYSCLK   RCC_CFGR_MCOSEL_SYSCLK

◆ RCC_CFGR_MCOPRE

#define RCC_CFGR_MCOPRE   RCC_CFGR_MCOPRE_Msk

MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler)

◆ RCC_CFGR_MCOPRE_0

#define RCC_CFGR_MCOPRE_0   (0x1U << RCC_CFGR_MCOPRE_Pos)

0x10000000

◆ RCC_CFGR_MCOPRE_1

#define RCC_CFGR_MCOPRE_1   (0x2U << RCC_CFGR_MCOPRE_Pos)

0x20000000

◆ RCC_CFGR_MCOPRE_2

#define RCC_CFGR_MCOPRE_2   (0x4U << RCC_CFGR_MCOPRE_Pos)

0x40000000 MCO Prescaler configuration

◆ RCC_CFGR_MCOPRE_DIV1

#define RCC_CFGR_MCOPRE_DIV1   (0x00000000U)

MCO is divided by 1

◆ RCC_CFGR_MCOPRE_DIV16

#define RCC_CFGR_MCOPRE_DIV16   (0x40000000U)

MCO is divided by 16

◆ RCC_CFGR_MCOPRE_DIV2

#define RCC_CFGR_MCOPRE_DIV2   (0x10000000U)

MCO is divided by 2

◆ RCC_CFGR_MCOPRE_DIV4

#define RCC_CFGR_MCOPRE_DIV4   (0x20000000U)

MCO is divided by 4

◆ RCC_CFGR_MCOPRE_DIV8

#define RCC_CFGR_MCOPRE_DIV8   (0x30000000U)

MCO is divided by 8

◆ RCC_CFGR_MCOPRE_Msk

#define RCC_CFGR_MCOPRE_Msk   (0x7U << RCC_CFGR_MCOPRE_Pos)

0x70000000

◆ RCC_CFGR_MCOPRE_Pos

#define RCC_CFGR_MCOPRE_Pos   (28U)

◆ RCC_CFGR_MCOSEL

#define RCC_CFGR_MCOSEL   RCC_CFGR_MCOSEL_Msk

MCO[2:0] bits (Microcontroller Clock Output)

◆ RCC_CFGR_MCOSEL_0

#define RCC_CFGR_MCOSEL_0   (0x1U << RCC_CFGR_MCOSEL_Pos)

0x01000000

◆ RCC_CFGR_MCOSEL_1

#define RCC_CFGR_MCOSEL_1   (0x2U << RCC_CFGR_MCOSEL_Pos)

0x02000000

◆ RCC_CFGR_MCOSEL_2

#define RCC_CFGR_MCOSEL_2   (0x4U << RCC_CFGR_MCOSEL_Pos)

0x04000000 MCO configuration

◆ RCC_CFGR_MCOSEL_HSE

#define RCC_CFGR_MCOSEL_HSE   RCC_CFGR_MCOSEL_HSE_Msk

External 1-25 MHz oscillator clock selected

◆ RCC_CFGR_MCOSEL_HSE_Msk

#define RCC_CFGR_MCOSEL_HSE_Msk   (0x1U << RCC_CFGR_MCOSEL_HSE_Pos)

0x04000000

◆ RCC_CFGR_MCOSEL_HSE_Pos

#define RCC_CFGR_MCOSEL_HSE_Pos   (26U)

◆ RCC_CFGR_MCOSEL_HSI

#define RCC_CFGR_MCOSEL_HSI   RCC_CFGR_MCOSEL_HSI_Msk

Internal 16 MHz RC oscillator clock selected

◆ RCC_CFGR_MCOSEL_HSI_Msk

#define RCC_CFGR_MCOSEL_HSI_Msk   (0x1U << RCC_CFGR_MCOSEL_HSI_Pos)

0x02000000

◆ RCC_CFGR_MCOSEL_HSI_Pos

#define RCC_CFGR_MCOSEL_HSI_Pos   (25U)

◆ RCC_CFGR_MCOSEL_LSE

#define RCC_CFGR_MCOSEL_LSE   RCC_CFGR_MCOSEL_LSE_Msk

LSE selected

◆ RCC_CFGR_MCOSEL_LSE_Msk

#define RCC_CFGR_MCOSEL_LSE_Msk   (0x7U << RCC_CFGR_MCOSEL_LSE_Pos)

0x07000000

◆ RCC_CFGR_MCOSEL_LSE_Pos

#define RCC_CFGR_MCOSEL_LSE_Pos   (24U)

◆ RCC_CFGR_MCOSEL_LSI

#define RCC_CFGR_MCOSEL_LSI   RCC_CFGR_MCOSEL_LSI_Msk

LSI selected

◆ RCC_CFGR_MCOSEL_LSI_Msk

#define RCC_CFGR_MCOSEL_LSI_Msk   (0x3U << RCC_CFGR_MCOSEL_LSI_Pos)

0x06000000

◆ RCC_CFGR_MCOSEL_LSI_Pos

#define RCC_CFGR_MCOSEL_LSI_Pos   (25U)

◆ RCC_CFGR_MCOSEL_MSI

#define RCC_CFGR_MCOSEL_MSI   RCC_CFGR_MCOSEL_MSI_Msk

Internal Medium Speed RC oscillator clock selected

◆ RCC_CFGR_MCOSEL_MSI_Msk

#define RCC_CFGR_MCOSEL_MSI_Msk   (0x3U << RCC_CFGR_MCOSEL_MSI_Pos)

0x03000000

◆ RCC_CFGR_MCOSEL_MSI_Pos

#define RCC_CFGR_MCOSEL_MSI_Pos   (24U)

◆ RCC_CFGR_MCOSEL_Msk

#define RCC_CFGR_MCOSEL_Msk   (0x7U << RCC_CFGR_MCOSEL_Pos)

0x07000000

◆ RCC_CFGR_MCOSEL_NOCLOCK

#define RCC_CFGR_MCOSEL_NOCLOCK   (0x00000000U)

No clock

◆ RCC_CFGR_MCOSEL_PLL

#define RCC_CFGR_MCOSEL_PLL   RCC_CFGR_MCOSEL_PLL_Msk

PLL clock divided

◆ RCC_CFGR_MCOSEL_PLL_Msk

#define RCC_CFGR_MCOSEL_PLL_Msk   (0x5U << RCC_CFGR_MCOSEL_PLL_Pos)

0x05000000

◆ RCC_CFGR_MCOSEL_PLL_Pos

#define RCC_CFGR_MCOSEL_PLL_Pos   (24U)

◆ RCC_CFGR_MCOSEL_Pos

#define RCC_CFGR_MCOSEL_Pos   (24U)

◆ RCC_CFGR_MCOSEL_SYSCLK

#define RCC_CFGR_MCOSEL_SYSCLK   RCC_CFGR_MCOSEL_SYSCLK_Msk

System clock selected

◆ RCC_CFGR_MCOSEL_SYSCLK_Msk

#define RCC_CFGR_MCOSEL_SYSCLK_Msk   (0x1U << RCC_CFGR_MCOSEL_SYSCLK_Pos)

0x01000000

◆ RCC_CFGR_MCOSEL_SYSCLK_Pos

#define RCC_CFGR_MCOSEL_SYSCLK_Pos   (24U)

◆ RCC_CFGR_PLLDIV

#define RCC_CFGR_PLLDIV   RCC_CFGR_PLLDIV_Msk

PLLDIV[1:0] bits (PLL Output Division)

◆ RCC_CFGR_PLLDIV1

#define RCC_CFGR_PLLDIV1   (0x00000000U)

PLL clock output = CKVCO / 1

◆ RCC_CFGR_PLLDIV2

#define RCC_CFGR_PLLDIV2   RCC_CFGR_PLLDIV2_Msk

PLL clock output = CKVCO / 2

◆ RCC_CFGR_PLLDIV2_Msk

#define RCC_CFGR_PLLDIV2_Msk   (0x1U << RCC_CFGR_PLLDIV2_Pos)

0x00400000

◆ RCC_CFGR_PLLDIV2_Pos

#define RCC_CFGR_PLLDIV2_Pos   (22U)

◆ RCC_CFGR_PLLDIV3

#define RCC_CFGR_PLLDIV3   RCC_CFGR_PLLDIV3_Msk

PLL clock output = CKVCO / 3

◆ RCC_CFGR_PLLDIV3_Msk

#define RCC_CFGR_PLLDIV3_Msk   (0x1U << RCC_CFGR_PLLDIV3_Pos)

0x00800000

◆ RCC_CFGR_PLLDIV3_Pos

#define RCC_CFGR_PLLDIV3_Pos   (23U)

◆ RCC_CFGR_PLLDIV4

#define RCC_CFGR_PLLDIV4   RCC_CFGR_PLLDIV4_Msk

PLL clock output = CKVCO / 4

◆ RCC_CFGR_PLLDIV4_Msk

#define RCC_CFGR_PLLDIV4_Msk   (0x3U << RCC_CFGR_PLLDIV4_Pos)

0x00C00000

◆ RCC_CFGR_PLLDIV4_Pos

#define RCC_CFGR_PLLDIV4_Pos   (22U)

◆ RCC_CFGR_PLLDIV_0

#define RCC_CFGR_PLLDIV_0   (0x1U << RCC_CFGR_PLLDIV_Pos)

0x00400000

◆ RCC_CFGR_PLLDIV_1

#define RCC_CFGR_PLLDIV_1   (0x2U << RCC_CFGR_PLLDIV_Pos)

0x00800000 PLLDIV configuration

◆ RCC_CFGR_PLLDIV_Msk

#define RCC_CFGR_PLLDIV_Msk   (0x3U << RCC_CFGR_PLLDIV_Pos)

0x00C00000

◆ RCC_CFGR_PLLDIV_Pos

#define RCC_CFGR_PLLDIV_Pos   (22U)

◆ RCC_CFGR_PLLMUL

#define RCC_CFGR_PLLMUL   RCC_CFGR_PLLMUL_Msk

PLLMUL[3:0] bits (PLL multiplication factor)

◆ RCC_CFGR_PLLMUL12

#define RCC_CFGR_PLLMUL12   (0x00100000U)

PLL input clock * 12

◆ RCC_CFGR_PLLMUL16

#define RCC_CFGR_PLLMUL16   (0x00140000U)

PLL input clock * 16

◆ RCC_CFGR_PLLMUL24

#define RCC_CFGR_PLLMUL24   (0x00180000U)

PLL input clock * 24

◆ RCC_CFGR_PLLMUL3

#define RCC_CFGR_PLLMUL3   (0x00000000U)

PLL input clock * 3

◆ RCC_CFGR_PLLMUL32

#define RCC_CFGR_PLLMUL32   (0x001C0000U)

PLL input clock * 32

◆ RCC_CFGR_PLLMUL4

#define RCC_CFGR_PLLMUL4   (0x00040000U)

PLL input clock * 4

◆ RCC_CFGR_PLLMUL48

#define RCC_CFGR_PLLMUL48   (0x00200000U)

PLL input clock * 48 PLLDIV configuration

◆ RCC_CFGR_PLLMUL6

#define RCC_CFGR_PLLMUL6   (0x00080000U)

PLL input clock * 6

◆ RCC_CFGR_PLLMUL8

#define RCC_CFGR_PLLMUL8   (0x000C0000U)

PLL input clock * 8

◆ RCC_CFGR_PLLMUL_0

#define RCC_CFGR_PLLMUL_0   (0x1U << RCC_CFGR_PLLMUL_Pos)

0x00040000

◆ RCC_CFGR_PLLMUL_1

#define RCC_CFGR_PLLMUL_1   (0x2U << RCC_CFGR_PLLMUL_Pos)

0x00080000

◆ RCC_CFGR_PLLMUL_2

#define RCC_CFGR_PLLMUL_2   (0x4U << RCC_CFGR_PLLMUL_Pos)

0x00100000

◆ RCC_CFGR_PLLMUL_3

#define RCC_CFGR_PLLMUL_3   (0x8U << RCC_CFGR_PLLMUL_Pos)

0x00200000 PLLMUL configuration

◆ RCC_CFGR_PLLMUL_Msk

#define RCC_CFGR_PLLMUL_Msk   (0xFU << RCC_CFGR_PLLMUL_Pos)

0x003C0000

◆ RCC_CFGR_PLLMUL_Pos

#define RCC_CFGR_PLLMUL_Pos   (18U)

◆ RCC_CFGR_PLLSRC

#define RCC_CFGR_PLLSRC   RCC_CFGR_PLLSRC_Msk

PLL entry clock source

◆ RCC_CFGR_PLLSRC_HSE

#define RCC_CFGR_PLLSRC_HSE   (0x00010000U)

HSE as PLL entry clock source PLLMUL configuration

◆ RCC_CFGR_PLLSRC_HSI

#define RCC_CFGR_PLLSRC_HSI   (0x00000000U)

HSI as PLL entry clock source

◆ RCC_CFGR_PLLSRC_Msk

#define RCC_CFGR_PLLSRC_Msk   (0x1U << RCC_CFGR_PLLSRC_Pos)

0x00010000

◆ RCC_CFGR_PLLSRC_Pos

#define RCC_CFGR_PLLSRC_Pos   (16U)

◆ RCC_CFGR_PPRE1

#define RCC_CFGR_PPRE1   RCC_CFGR_PPRE1_Msk

PRE1[2:0] bits (APB1 prescaler)

◆ RCC_CFGR_PPRE1_0

#define RCC_CFGR_PPRE1_0   (0x1U << RCC_CFGR_PPRE1_Pos)

0x00000100

◆ RCC_CFGR_PPRE1_1

#define RCC_CFGR_PPRE1_1   (0x2U << RCC_CFGR_PPRE1_Pos)

0x00000200

◆ RCC_CFGR_PPRE1_2

#define RCC_CFGR_PPRE1_2   (0x4U << RCC_CFGR_PPRE1_Pos)

0x00000400 PPRE1 configuration

◆ RCC_CFGR_PPRE1_DIV1

#define RCC_CFGR_PPRE1_DIV1   (0x00000000U)

HCLK not divided

◆ RCC_CFGR_PPRE1_DIV16

#define RCC_CFGR_PPRE1_DIV16   (0x00000700U)

HCLK divided by 16

◆ RCC_CFGR_PPRE1_DIV2

#define RCC_CFGR_PPRE1_DIV2   (0x00000400U)

HCLK divided by 2

◆ RCC_CFGR_PPRE1_DIV4

#define RCC_CFGR_PPRE1_DIV4   (0x00000500U)

HCLK divided by 4

◆ RCC_CFGR_PPRE1_DIV8

#define RCC_CFGR_PPRE1_DIV8   (0x00000600U)

HCLK divided by 8

◆ RCC_CFGR_PPRE1_Msk

#define RCC_CFGR_PPRE1_Msk   (0x7U << RCC_CFGR_PPRE1_Pos)

0x00000700

◆ RCC_CFGR_PPRE1_Pos

#define RCC_CFGR_PPRE1_Pos   (8U)

◆ RCC_CFGR_PPRE2

#define RCC_CFGR_PPRE2   RCC_CFGR_PPRE2_Msk

PRE2[2:0] bits (APB2 prescaler)

◆ RCC_CFGR_PPRE2_0

#define RCC_CFGR_PPRE2_0   (0x1U << RCC_CFGR_PPRE2_Pos)

0x00000800

◆ RCC_CFGR_PPRE2_1

#define RCC_CFGR_PPRE2_1   (0x2U << RCC_CFGR_PPRE2_Pos)

0x00001000

◆ RCC_CFGR_PPRE2_2

#define RCC_CFGR_PPRE2_2   (0x4U << RCC_CFGR_PPRE2_Pos)

0x00002000 PPRE2 configuration

◆ RCC_CFGR_PPRE2_DIV1

#define RCC_CFGR_PPRE2_DIV1   (0x00000000U)

HCLK not divided

◆ RCC_CFGR_PPRE2_DIV16

#define RCC_CFGR_PPRE2_DIV16   (0x00003800U)

HCLK divided by 16 PLL entry clock source

◆ RCC_CFGR_PPRE2_DIV2

#define RCC_CFGR_PPRE2_DIV2   (0x00002000U)

HCLK divided by 2

◆ RCC_CFGR_PPRE2_DIV4

#define RCC_CFGR_PPRE2_DIV4   (0x00002800U)

HCLK divided by 4

◆ RCC_CFGR_PPRE2_DIV8

#define RCC_CFGR_PPRE2_DIV8   (0x00003000U)

HCLK divided by 8

◆ RCC_CFGR_PPRE2_Msk

#define RCC_CFGR_PPRE2_Msk   (0x7U << RCC_CFGR_PPRE2_Pos)

0x00003800

◆ RCC_CFGR_PPRE2_Pos

#define RCC_CFGR_PPRE2_Pos   (11U)

◆ RCC_CFGR_SW

#define RCC_CFGR_SW   RCC_CFGR_SW_Msk

SW[1:0] bits (System clock Switch)

◆ RCC_CFGR_SW_0

#define RCC_CFGR_SW_0   (0x1U << RCC_CFGR_SW_Pos)

0x00000001

◆ RCC_CFGR_SW_1

#define RCC_CFGR_SW_1   (0x2U << RCC_CFGR_SW_Pos)

0x00000002 SW configuration

◆ RCC_CFGR_SW_HSE

#define RCC_CFGR_SW_HSE   (0x00000002U)

HSE selected as system clock

◆ RCC_CFGR_SW_HSI

#define RCC_CFGR_SW_HSI   (0x00000001U)

HSI selected as system clock

◆ RCC_CFGR_SW_MSI

#define RCC_CFGR_SW_MSI   (0x00000000U)

MSI selected as system clock

◆ RCC_CFGR_SW_Msk

#define RCC_CFGR_SW_Msk   (0x3U << RCC_CFGR_SW_Pos)

0x00000003

◆ RCC_CFGR_SW_PLL

#define RCC_CFGR_SW_PLL   (0x00000003U)

PLL selected as system clock

◆ RCC_CFGR_SW_Pos

#define RCC_CFGR_SW_Pos   (0U)

◆ RCC_CFGR_SWS

#define RCC_CFGR_SWS   RCC_CFGR_SWS_Msk

SWS[1:0] bits (System Clock Switch Status)

◆ RCC_CFGR_SWS_0

#define RCC_CFGR_SWS_0   (0x1U << RCC_CFGR_SWS_Pos)

0x00000004

◆ RCC_CFGR_SWS_1

#define RCC_CFGR_SWS_1   (0x2U << RCC_CFGR_SWS_Pos)

0x00000008 SWS configuration

◆ RCC_CFGR_SWS_HSE

#define RCC_CFGR_SWS_HSE   (0x00000008U)

HSE oscillator used as system clock

◆ RCC_CFGR_SWS_HSI

#define RCC_CFGR_SWS_HSI   (0x00000004U)

HSI oscillator used as system clock

◆ RCC_CFGR_SWS_MSI

#define RCC_CFGR_SWS_MSI   (0x00000000U)

MSI oscillator used as system clock

◆ RCC_CFGR_SWS_Msk

#define RCC_CFGR_SWS_Msk   (0x3U << RCC_CFGR_SWS_Pos)

0x0000000C

◆ RCC_CFGR_SWS_PLL

#define RCC_CFGR_SWS_PLL   (0x0000000CU)

PLL used as system clock

◆ RCC_CFGR_SWS_Pos

#define RCC_CFGR_SWS_Pos   (2U)

◆ RCC_CIR_CSSC

#define RCC_CIR_CSSC   RCC_CIR_CSSC_Msk

Clock Security System Interrupt Clear

◆ RCC_CIR_CSSC_Msk

#define RCC_CIR_CSSC_Msk   (0x1U << RCC_CIR_CSSC_Pos)

0x00800000

◆ RCC_CIR_CSSC_Pos

#define RCC_CIR_CSSC_Pos   (23U)

◆ RCC_CIR_CSSF

#define RCC_CIR_CSSF   RCC_CIR_CSSF_Msk

Clock Security System Interrupt flag

◆ RCC_CIR_CSSF_Msk

#define RCC_CIR_CSSF_Msk   (0x1U << RCC_CIR_CSSF_Pos)

0x00000080

◆ RCC_CIR_CSSF_Pos

#define RCC_CIR_CSSF_Pos   (7U)

◆ RCC_CIR_HSERDYC

#define RCC_CIR_HSERDYC   RCC_CIR_HSERDYC_Msk

HSE Ready Interrupt Clear

◆ RCC_CIR_HSERDYC_Msk

#define RCC_CIR_HSERDYC_Msk   (0x1U << RCC_CIR_HSERDYC_Pos)

0x00080000

◆ RCC_CIR_HSERDYC_Pos

#define RCC_CIR_HSERDYC_Pos   (19U)

◆ RCC_CIR_HSERDYF

#define RCC_CIR_HSERDYF   RCC_CIR_HSERDYF_Msk

HSE Ready Interrupt flag

◆ RCC_CIR_HSERDYF_Msk

#define RCC_CIR_HSERDYF_Msk   (0x1U << RCC_CIR_HSERDYF_Pos)

0x00000008

◆ RCC_CIR_HSERDYF_Pos

#define RCC_CIR_HSERDYF_Pos   (3U)

◆ RCC_CIR_HSERDYIE

#define RCC_CIR_HSERDYIE   RCC_CIR_HSERDYIE_Msk

HSE Ready Interrupt Enable

◆ RCC_CIR_HSERDYIE_Msk

#define RCC_CIR_HSERDYIE_Msk   (0x1U << RCC_CIR_HSERDYIE_Pos)

0x00000800

◆ RCC_CIR_HSERDYIE_Pos

#define RCC_CIR_HSERDYIE_Pos   (11U)

◆ RCC_CIR_HSIRDYC

#define RCC_CIR_HSIRDYC   RCC_CIR_HSIRDYC_Msk

HSI Ready Interrupt Clear

◆ RCC_CIR_HSIRDYC_Msk

#define RCC_CIR_HSIRDYC_Msk   (0x1U << RCC_CIR_HSIRDYC_Pos)

0x00040000

◆ RCC_CIR_HSIRDYC_Pos

#define RCC_CIR_HSIRDYC_Pos   (18U)

◆ RCC_CIR_HSIRDYF

#define RCC_CIR_HSIRDYF   RCC_CIR_HSIRDYF_Msk

HSI Ready Interrupt flag

◆ RCC_CIR_HSIRDYF_Msk

#define RCC_CIR_HSIRDYF_Msk   (0x1U << RCC_CIR_HSIRDYF_Pos)

0x00000004

◆ RCC_CIR_HSIRDYF_Pos

#define RCC_CIR_HSIRDYF_Pos   (2U)

◆ RCC_CIR_HSIRDYIE

#define RCC_CIR_HSIRDYIE   RCC_CIR_HSIRDYIE_Msk

HSI Ready Interrupt Enable

◆ RCC_CIR_HSIRDYIE_Msk

#define RCC_CIR_HSIRDYIE_Msk   (0x1U << RCC_CIR_HSIRDYIE_Pos)

0x00000400

◆ RCC_CIR_HSIRDYIE_Pos

#define RCC_CIR_HSIRDYIE_Pos   (10U)

◆ RCC_CIR_LSECSSC

#define RCC_CIR_LSECSSC   RCC_CIR_LSECSSC_Msk

LSE CSS Interrupt Clear

◆ RCC_CIR_LSECSSC_Msk

#define RCC_CIR_LSECSSC_Msk   (0x1U << RCC_CIR_LSECSSC_Pos)

0x00400000

◆ RCC_CIR_LSECSSC_Pos

#define RCC_CIR_LSECSSC_Pos   (22U)

◆ RCC_CIR_LSECSSF

#define RCC_CIR_LSECSSF   RCC_CIR_LSECSSF_Msk

LSE CSS Interrupt flag

◆ RCC_CIR_LSECSSF_Msk

#define RCC_CIR_LSECSSF_Msk   (0x1U << RCC_CIR_LSECSSF_Pos)

0x00000040

◆ RCC_CIR_LSECSSF_Pos

#define RCC_CIR_LSECSSF_Pos   (6U)

◆ RCC_CIR_LSECSSIE

#define RCC_CIR_LSECSSIE   RCC_CIR_LSECSSIE_Msk

LSE CSS Interrupt Enable

◆ RCC_CIR_LSECSSIE_Msk

#define RCC_CIR_LSECSSIE_Msk   (0x1U << RCC_CIR_LSECSSIE_Pos)

0x00004000

◆ RCC_CIR_LSECSSIE_Pos

#define RCC_CIR_LSECSSIE_Pos   (14U)

◆ RCC_CIR_LSERDYC

#define RCC_CIR_LSERDYC   RCC_CIR_LSERDYC_Msk

LSE Ready Interrupt Clear

◆ RCC_CIR_LSERDYC_Msk

#define RCC_CIR_LSERDYC_Msk   (0x1U << RCC_CIR_LSERDYC_Pos)

0x00020000

◆ RCC_CIR_LSERDYC_Pos

#define RCC_CIR_LSERDYC_Pos   (17U)

◆ RCC_CIR_LSERDYF

#define RCC_CIR_LSERDYF   RCC_CIR_LSERDYF_Msk

LSE Ready Interrupt flag

◆ RCC_CIR_LSERDYF_Msk

#define RCC_CIR_LSERDYF_Msk   (0x1U << RCC_CIR_LSERDYF_Pos)

0x00000002

◆ RCC_CIR_LSERDYF_Pos

#define RCC_CIR_LSERDYF_Pos   (1U)

◆ RCC_CIR_LSERDYIE

#define RCC_CIR_LSERDYIE   RCC_CIR_LSERDYIE_Msk

LSE Ready Interrupt Enable

◆ RCC_CIR_LSERDYIE_Msk

#define RCC_CIR_LSERDYIE_Msk   (0x1U << RCC_CIR_LSERDYIE_Pos)

0x00000200

◆ RCC_CIR_LSERDYIE_Pos

#define RCC_CIR_LSERDYIE_Pos   (9U)

◆ RCC_CIR_LSIRDYC

#define RCC_CIR_LSIRDYC   RCC_CIR_LSIRDYC_Msk

LSI Ready Interrupt Clear

◆ RCC_CIR_LSIRDYC_Msk

#define RCC_CIR_LSIRDYC_Msk   (0x1U << RCC_CIR_LSIRDYC_Pos)

0x00010000

◆ RCC_CIR_LSIRDYC_Pos

#define RCC_CIR_LSIRDYC_Pos   (16U)

◆ RCC_CIR_LSIRDYF

#define RCC_CIR_LSIRDYF   RCC_CIR_LSIRDYF_Msk

LSI Ready Interrupt flag

◆ RCC_CIR_LSIRDYF_Msk

#define RCC_CIR_LSIRDYF_Msk   (0x1U << RCC_CIR_LSIRDYF_Pos)

0x00000001

◆ RCC_CIR_LSIRDYF_Pos

#define RCC_CIR_LSIRDYF_Pos   (0U)

◆ RCC_CIR_LSIRDYIE

#define RCC_CIR_LSIRDYIE   RCC_CIR_LSIRDYIE_Msk

LSI Ready Interrupt Enable

◆ RCC_CIR_LSIRDYIE_Msk

#define RCC_CIR_LSIRDYIE_Msk   (0x1U << RCC_CIR_LSIRDYIE_Pos)

0x00000100

◆ RCC_CIR_LSIRDYIE_Pos

#define RCC_CIR_LSIRDYIE_Pos   (8U)

◆ RCC_CIR_MSIRDYC

#define RCC_CIR_MSIRDYC   RCC_CIR_MSIRDYC_Msk

MSI Ready Interrupt Clear

◆ RCC_CIR_MSIRDYC_Msk

#define RCC_CIR_MSIRDYC_Msk   (0x1U << RCC_CIR_MSIRDYC_Pos)

0x00200000

◆ RCC_CIR_MSIRDYC_Pos

#define RCC_CIR_MSIRDYC_Pos   (21U)

◆ RCC_CIR_MSIRDYF

#define RCC_CIR_MSIRDYF   RCC_CIR_MSIRDYF_Msk

MSI Ready Interrupt flag

◆ RCC_CIR_MSIRDYF_Msk

#define RCC_CIR_MSIRDYF_Msk   (0x1U << RCC_CIR_MSIRDYF_Pos)

0x00000020

◆ RCC_CIR_MSIRDYF_Pos

#define RCC_CIR_MSIRDYF_Pos   (5U)

◆ RCC_CIR_MSIRDYIE

#define RCC_CIR_MSIRDYIE   RCC_CIR_MSIRDYIE_Msk

MSI Ready Interrupt Enable

◆ RCC_CIR_MSIRDYIE_Msk

#define RCC_CIR_MSIRDYIE_Msk   (0x1U << RCC_CIR_MSIRDYIE_Pos)

0x00002000

◆ RCC_CIR_MSIRDYIE_Pos

#define RCC_CIR_MSIRDYIE_Pos   (13U)

◆ RCC_CIR_PLLRDYC

#define RCC_CIR_PLLRDYC   RCC_CIR_PLLRDYC_Msk

PLL Ready Interrupt Clear

◆ RCC_CIR_PLLRDYC_Msk

#define RCC_CIR_PLLRDYC_Msk   (0x1U << RCC_CIR_PLLRDYC_Pos)

0x00100000

◆ RCC_CIR_PLLRDYC_Pos

#define RCC_CIR_PLLRDYC_Pos   (20U)

◆ RCC_CIR_PLLRDYF

#define RCC_CIR_PLLRDYF   RCC_CIR_PLLRDYF_Msk

PLL Ready Interrupt flag

◆ RCC_CIR_PLLRDYF_Msk

#define RCC_CIR_PLLRDYF_Msk   (0x1U << RCC_CIR_PLLRDYF_Pos)

0x00000010

◆ RCC_CIR_PLLRDYF_Pos

#define RCC_CIR_PLLRDYF_Pos   (4U)

◆ RCC_CIR_PLLRDYIE

#define RCC_CIR_PLLRDYIE   RCC_CIR_PLLRDYIE_Msk

PLL Ready Interrupt Enable

◆ RCC_CIR_PLLRDYIE_Msk

#define RCC_CIR_PLLRDYIE_Msk   (0x1U << RCC_CIR_PLLRDYIE_Pos)

0x00001000

◆ RCC_CIR_PLLRDYIE_Pos

#define RCC_CIR_PLLRDYIE_Pos   (12U)

◆ RCC_CR_CSSON

#define RCC_CR_CSSON   RCC_CR_CSSON_Msk

Clock Security System enable

◆ RCC_CR_CSSON_Msk

#define RCC_CR_CSSON_Msk   (0x1U << RCC_CR_CSSON_Pos)

0x10000000

◆ RCC_CR_CSSON_Pos

#define RCC_CR_CSSON_Pos   (28U)

◆ RCC_CR_HSEBYP

#define RCC_CR_HSEBYP   RCC_CR_HSEBYP_Msk

External High Speed clock Bypass

◆ RCC_CR_HSEBYP_Msk

#define RCC_CR_HSEBYP_Msk   (0x1U << RCC_CR_HSEBYP_Pos)

0x00040000

◆ RCC_CR_HSEBYP_Pos

#define RCC_CR_HSEBYP_Pos   (18U)

◆ RCC_CR_HSEON

#define RCC_CR_HSEON   RCC_CR_HSEON_Msk

External High Speed clock enable

◆ RCC_CR_HSEON_Msk

#define RCC_CR_HSEON_Msk   (0x1U << RCC_CR_HSEON_Pos)

0x00010000

◆ RCC_CR_HSEON_Pos

#define RCC_CR_HSEON_Pos   (16U)

◆ RCC_CR_HSERDY

#define RCC_CR_HSERDY   RCC_CR_HSERDY_Msk

External High Speed clock ready flag

◆ RCC_CR_HSERDY_Msk

#define RCC_CR_HSERDY_Msk   (0x1U << RCC_CR_HSERDY_Pos)

0x00020000

◆ RCC_CR_HSERDY_Pos

#define RCC_CR_HSERDY_Pos   (17U)

◆ RCC_CR_HSION

#define RCC_CR_HSION   RCC_CR_HSION_Msk

Internal High Speed clock enable

◆ RCC_CR_HSION_Msk

#define RCC_CR_HSION_Msk   (0x1U << RCC_CR_HSION_Pos)

0x00000001

◆ RCC_CR_HSION_Pos

#define RCC_CR_HSION_Pos   (0U)

◆ RCC_CR_HSIRDY

#define RCC_CR_HSIRDY   RCC_CR_HSIRDY_Msk

Internal High Speed clock ready flag

◆ RCC_CR_HSIRDY_Msk

#define RCC_CR_HSIRDY_Msk   (0x1U << RCC_CR_HSIRDY_Pos)

0x00000002

◆ RCC_CR_HSIRDY_Pos

#define RCC_CR_HSIRDY_Pos   (1U)

◆ RCC_CR_MSION

#define RCC_CR_MSION   RCC_CR_MSION_Msk

Internal Multi Speed clock enable

◆ RCC_CR_MSION_Msk

#define RCC_CR_MSION_Msk   (0x1U << RCC_CR_MSION_Pos)

0x00000100

◆ RCC_CR_MSION_Pos

#define RCC_CR_MSION_Pos   (8U)

◆ RCC_CR_MSIRDY

#define RCC_CR_MSIRDY   RCC_CR_MSIRDY_Msk

Internal Multi Speed clock ready flag

◆ RCC_CR_MSIRDY_Msk

#define RCC_CR_MSIRDY_Msk   (0x1U << RCC_CR_MSIRDY_Pos)

0x00000200

◆ RCC_CR_MSIRDY_Pos

#define RCC_CR_MSIRDY_Pos   (9U)

◆ RCC_CR_PLLON

#define RCC_CR_PLLON   RCC_CR_PLLON_Msk

PLL enable

◆ RCC_CR_PLLON_Msk

#define RCC_CR_PLLON_Msk   (0x1U << RCC_CR_PLLON_Pos)

0x01000000

◆ RCC_CR_PLLON_Pos

#define RCC_CR_PLLON_Pos   (24U)

◆ RCC_CR_PLLRDY

#define RCC_CR_PLLRDY   RCC_CR_PLLRDY_Msk

PLL clock ready flag

◆ RCC_CR_PLLRDY_Msk

#define RCC_CR_PLLRDY_Msk   (0x1U << RCC_CR_PLLRDY_Pos)

0x02000000

◆ RCC_CR_PLLRDY_Pos

#define RCC_CR_PLLRDY_Pos   (25U)

◆ RCC_CR_RTCPRE

#define RCC_CR_RTCPRE   RCC_CR_RTCPRE_Msk

RTC/LCD Prescaler

◆ RCC_CR_RTCPRE_0

#define RCC_CR_RTCPRE_0   (0x20000000U)

Bit0

◆ RCC_CR_RTCPRE_1

#define RCC_CR_RTCPRE_1   (0x40000000U)

Bit1

◆ RCC_CR_RTCPRE_Msk

#define RCC_CR_RTCPRE_Msk   (0x3U << RCC_CR_RTCPRE_Pos)

0x60000000

◆ RCC_CR_RTCPRE_Pos

#define RCC_CR_RTCPRE_Pos   (29U)

◆ RCC_CSR_IWDGRSTF

#define RCC_CSR_IWDGRSTF   RCC_CSR_IWDGRSTF_Msk

Independent Watchdog reset flag

◆ RCC_CSR_IWDGRSTF_Msk

#define RCC_CSR_IWDGRSTF_Msk   (0x1U << RCC_CSR_IWDGRSTF_Pos)

0x20000000

◆ RCC_CSR_IWDGRSTF_Pos

#define RCC_CSR_IWDGRSTF_Pos   (29U)

◆ RCC_CSR_LPWRRSTF

#define RCC_CSR_LPWRRSTF   RCC_CSR_LPWRRSTF_Msk

Low-Power reset flag

◆ RCC_CSR_LPWRRSTF_Msk

#define RCC_CSR_LPWRRSTF_Msk   (0x1U << RCC_CSR_LPWRRSTF_Pos)

0x80000000

◆ RCC_CSR_LPWRRSTF_Pos

#define RCC_CSR_LPWRRSTF_Pos   (31U)

◆ RCC_CSR_LSEBYP

#define RCC_CSR_LSEBYP   RCC_CSR_LSEBYP_Msk

External Low Speed oscillator Bypass

◆ RCC_CSR_LSEBYP_Msk

#define RCC_CSR_LSEBYP_Msk   (0x1U << RCC_CSR_LSEBYP_Pos)

0x00000400

◆ RCC_CSR_LSEBYP_Pos

#define RCC_CSR_LSEBYP_Pos   (10U)

◆ RCC_CSR_LSECSSD

#define RCC_CSR_LSECSSD   RCC_CSR_LSECSSD_Msk

External Low Speed oscillator CSS Detected

◆ RCC_CSR_LSECSSD_Msk

#define RCC_CSR_LSECSSD_Msk   (0x1U << RCC_CSR_LSECSSD_Pos)

0x00001000

◆ RCC_CSR_LSECSSD_Pos

#define RCC_CSR_LSECSSD_Pos   (12U)

◆ RCC_CSR_LSECSSON

#define RCC_CSR_LSECSSON   RCC_CSR_LSECSSON_Msk

External Low Speed oscillator CSS Enable

◆ RCC_CSR_LSECSSON_Msk

#define RCC_CSR_LSECSSON_Msk   (0x1U << RCC_CSR_LSECSSON_Pos)

0x00000800

◆ RCC_CSR_LSECSSON_Pos

#define RCC_CSR_LSECSSON_Pos   (11U)

◆ RCC_CSR_LSEON

#define RCC_CSR_LSEON   RCC_CSR_LSEON_Msk

External Low Speed oscillator enable

◆ RCC_CSR_LSEON_Msk

#define RCC_CSR_LSEON_Msk   (0x1U << RCC_CSR_LSEON_Pos)

0x00000100

◆ RCC_CSR_LSEON_Pos

#define RCC_CSR_LSEON_Pos   (8U)

◆ RCC_CSR_LSERDY

#define RCC_CSR_LSERDY   RCC_CSR_LSERDY_Msk

External Low Speed oscillator Ready

◆ RCC_CSR_LSERDY_Msk

#define RCC_CSR_LSERDY_Msk   (0x1U << RCC_CSR_LSERDY_Pos)

0x00000200

◆ RCC_CSR_LSERDY_Pos

#define RCC_CSR_LSERDY_Pos   (9U)

◆ RCC_CSR_LSION

#define RCC_CSR_LSION   RCC_CSR_LSION_Msk

Internal Low Speed oscillator enable

◆ RCC_CSR_LSION_Msk

#define RCC_CSR_LSION_Msk   (0x1U << RCC_CSR_LSION_Pos)

0x00000001

◆ RCC_CSR_LSION_Pos

#define RCC_CSR_LSION_Pos   (0U)

◆ RCC_CSR_LSIRDY

#define RCC_CSR_LSIRDY   RCC_CSR_LSIRDY_Msk

Internal Low Speed oscillator Ready

◆ RCC_CSR_LSIRDY_Msk

#define RCC_CSR_LSIRDY_Msk   (0x1U << RCC_CSR_LSIRDY_Pos)

0x00000002

◆ RCC_CSR_LSIRDY_Pos

#define RCC_CSR_LSIRDY_Pos   (1U)

◆ RCC_CSR_OBLRSTF

#define RCC_CSR_OBLRSTF   RCC_CSR_OBLRSTF_Msk

Option Bytes Loader reset flag

◆ RCC_CSR_OBLRSTF_Msk

#define RCC_CSR_OBLRSTF_Msk   (0x1U << RCC_CSR_OBLRSTF_Pos)

0x02000000

◆ RCC_CSR_OBLRSTF_Pos

#define RCC_CSR_OBLRSTF_Pos   (25U)

◆ RCC_CSR_PINRSTF

#define RCC_CSR_PINRSTF   RCC_CSR_PINRSTF_Msk

PIN reset flag

◆ RCC_CSR_PINRSTF_Msk

#define RCC_CSR_PINRSTF_Msk   (0x1U << RCC_CSR_PINRSTF_Pos)

0x04000000

◆ RCC_CSR_PINRSTF_Pos

#define RCC_CSR_PINRSTF_Pos   (26U)

◆ RCC_CSR_PORRSTF

#define RCC_CSR_PORRSTF   RCC_CSR_PORRSTF_Msk

POR/PDR reset flag

◆ RCC_CSR_PORRSTF_Msk

#define RCC_CSR_PORRSTF_Msk   (0x1U << RCC_CSR_PORRSTF_Pos)

0x08000000

◆ RCC_CSR_PORRSTF_Pos

#define RCC_CSR_PORRSTF_Pos   (27U)

◆ RCC_CSR_RMVF

#define RCC_CSR_RMVF   RCC_CSR_RMVF_Msk

Remove reset flag

◆ RCC_CSR_RMVF_Msk

#define RCC_CSR_RMVF_Msk   (0x1U << RCC_CSR_RMVF_Pos)

0x01000000

◆ RCC_CSR_RMVF_Pos

#define RCC_CSR_RMVF_Pos   (24U)

◆ RCC_CSR_RTCEN

#define RCC_CSR_RTCEN   RCC_CSR_RTCEN_Msk

RTC clock enable

◆ RCC_CSR_RTCEN_Msk

#define RCC_CSR_RTCEN_Msk   (0x1U << RCC_CSR_RTCEN_Pos)

0x00400000

◆ RCC_CSR_RTCEN_Pos

#define RCC_CSR_RTCEN_Pos   (22U)

◆ RCC_CSR_RTCRST

#define RCC_CSR_RTCRST   RCC_CSR_RTCRST_Msk

RTC reset

◆ RCC_CSR_RTCRST_Msk

#define RCC_CSR_RTCRST_Msk   (0x1U << RCC_CSR_RTCRST_Pos)

0x00800000

◆ RCC_CSR_RTCRST_Pos

#define RCC_CSR_RTCRST_Pos   (23U)

◆ RCC_CSR_RTCSEL

#define RCC_CSR_RTCSEL   RCC_CSR_RTCSEL_Msk

RTCSEL[1:0] bits (RTC clock source selection)

◆ RCC_CSR_RTCSEL_0

#define RCC_CSR_RTCSEL_0   (0x1U << RCC_CSR_RTCSEL_Pos)

0x00010000

◆ RCC_CSR_RTCSEL_1

#define RCC_CSR_RTCSEL_1   (0x2U << RCC_CSR_RTCSEL_Pos)

0x00020000 RTC congiguration

◆ RCC_CSR_RTCSEL_HSE

#define RCC_CSR_RTCSEL_HSE   RCC_CSR_RTCSEL_HSE_Msk

HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock

◆ RCC_CSR_RTCSEL_HSE_Msk

#define RCC_CSR_RTCSEL_HSE_Msk   (0x3U << RCC_CSR_RTCSEL_HSE_Pos)

0x00030000

◆ RCC_CSR_RTCSEL_HSE_Pos

#define RCC_CSR_RTCSEL_HSE_Pos   (16U)

◆ RCC_CSR_RTCSEL_LSE

#define RCC_CSR_RTCSEL_LSE   RCC_CSR_RTCSEL_LSE_Msk

LSE oscillator clock used as RTC clock

◆ RCC_CSR_RTCSEL_LSE_Msk

#define RCC_CSR_RTCSEL_LSE_Msk   (0x1U << RCC_CSR_RTCSEL_LSE_Pos)

0x00010000

◆ RCC_CSR_RTCSEL_LSE_Pos

#define RCC_CSR_RTCSEL_LSE_Pos   (16U)

◆ RCC_CSR_RTCSEL_LSI

#define RCC_CSR_RTCSEL_LSI   RCC_CSR_RTCSEL_LSI_Msk

LSI oscillator clock used as RTC clock

◆ RCC_CSR_RTCSEL_LSI_Msk

#define RCC_CSR_RTCSEL_LSI_Msk   (0x1U << RCC_CSR_RTCSEL_LSI_Pos)

0x00020000

◆ RCC_CSR_RTCSEL_LSI_Pos

#define RCC_CSR_RTCSEL_LSI_Pos   (17U)

◆ RCC_CSR_RTCSEL_Msk

#define RCC_CSR_RTCSEL_Msk   (0x3U << RCC_CSR_RTCSEL_Pos)

0x00030000

◆ RCC_CSR_RTCSEL_NOCLOCK

#define RCC_CSR_RTCSEL_NOCLOCK   (0x00000000U)

No clock

◆ RCC_CSR_RTCSEL_Pos

#define RCC_CSR_RTCSEL_Pos   (16U)

◆ RCC_CSR_SFTRSTF

#define RCC_CSR_SFTRSTF   RCC_CSR_SFTRSTF_Msk

Software Reset flag

◆ RCC_CSR_SFTRSTF_Msk

#define RCC_CSR_SFTRSTF_Msk   (0x1U << RCC_CSR_SFTRSTF_Pos)

0x10000000

◆ RCC_CSR_SFTRSTF_Pos

#define RCC_CSR_SFTRSTF_Pos   (28U)

◆ RCC_CSR_WWDGRSTF

#define RCC_CSR_WWDGRSTF   RCC_CSR_WWDGRSTF_Msk

Window watchdog reset flag

◆ RCC_CSR_WWDGRSTF_Msk

#define RCC_CSR_WWDGRSTF_Msk   (0x1U << RCC_CSR_WWDGRSTF_Pos)

0x40000000

◆ RCC_CSR_WWDGRSTF_Pos

#define RCC_CSR_WWDGRSTF_Pos   (30U)

◆ RCC_ICSCR_HSICAL

#define RCC_ICSCR_HSICAL   RCC_ICSCR_HSICAL_Msk

Internal High Speed clock Calibration

◆ RCC_ICSCR_HSICAL_Msk

#define RCC_ICSCR_HSICAL_Msk   (0xFFU << RCC_ICSCR_HSICAL_Pos)

0x000000FF

◆ RCC_ICSCR_HSICAL_Pos

#define RCC_ICSCR_HSICAL_Pos   (0U)

◆ RCC_ICSCR_HSITRIM

#define RCC_ICSCR_HSITRIM   RCC_ICSCR_HSITRIM_Msk

Internal High Speed clock trimming

◆ RCC_ICSCR_HSITRIM_Msk

#define RCC_ICSCR_HSITRIM_Msk   (0x1FU << RCC_ICSCR_HSITRIM_Pos)

0x00001F00

◆ RCC_ICSCR_HSITRIM_Pos

#define RCC_ICSCR_HSITRIM_Pos   (8U)

◆ RCC_ICSCR_MSICAL

#define RCC_ICSCR_MSICAL   RCC_ICSCR_MSICAL_Msk

Internal Multi Speed clock Calibration

◆ RCC_ICSCR_MSICAL_Msk

#define RCC_ICSCR_MSICAL_Msk   (0xFFU << RCC_ICSCR_MSICAL_Pos)

0x00FF0000

◆ RCC_ICSCR_MSICAL_Pos

#define RCC_ICSCR_MSICAL_Pos   (16U)

◆ RCC_ICSCR_MSIRANGE

#define RCC_ICSCR_MSIRANGE   RCC_ICSCR_MSIRANGE_Msk

Internal Multi Speed clock Range

◆ RCC_ICSCR_MSIRANGE_0

#define RCC_ICSCR_MSIRANGE_0   (0x0U << RCC_ICSCR_MSIRANGE_Pos)

0x00000000

◆ RCC_ICSCR_MSIRANGE_1

#define RCC_ICSCR_MSIRANGE_1   (0x1U << RCC_ICSCR_MSIRANGE_Pos)

0x00002000

◆ RCC_ICSCR_MSIRANGE_2

#define RCC_ICSCR_MSIRANGE_2   (0x2U << RCC_ICSCR_MSIRANGE_Pos)

0x00004000

◆ RCC_ICSCR_MSIRANGE_3

#define RCC_ICSCR_MSIRANGE_3   (0x3U << RCC_ICSCR_MSIRANGE_Pos)

0x00006000

◆ RCC_ICSCR_MSIRANGE_4

#define RCC_ICSCR_MSIRANGE_4   (0x4U << RCC_ICSCR_MSIRANGE_Pos)

0x00008000

◆ RCC_ICSCR_MSIRANGE_5

#define RCC_ICSCR_MSIRANGE_5   (0x5U << RCC_ICSCR_MSIRANGE_Pos)

0x0000A000

◆ RCC_ICSCR_MSIRANGE_6

#define RCC_ICSCR_MSIRANGE_6   (0x6U << RCC_ICSCR_MSIRANGE_Pos)

0x0000C000

◆ RCC_ICSCR_MSIRANGE_Msk

#define RCC_ICSCR_MSIRANGE_Msk   (0x7U << RCC_ICSCR_MSIRANGE_Pos)

0x0000E000

◆ RCC_ICSCR_MSIRANGE_Pos

#define RCC_ICSCR_MSIRANGE_Pos   (13U)

◆ RCC_ICSCR_MSITRIM

#define RCC_ICSCR_MSITRIM   RCC_ICSCR_MSITRIM_Msk

Internal Multi Speed clock trimming

◆ RCC_ICSCR_MSITRIM_Msk

#define RCC_ICSCR_MSITRIM_Msk   (0xFFU << RCC_ICSCR_MSITRIM_Pos)

0xFF000000

◆ RCC_ICSCR_MSITRIM_Pos

#define RCC_ICSCR_MSITRIM_Pos   (24U)

◆ RCC_LSECSS_SUPPORT

#define RCC_LSECSS_SUPPORT

LSE CSS feature support

◆ RI_ASCR1_CH

#define RI_ASCR1_CH   RI_ASCR1_CH_Msk

AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits)

◆ RI_ASCR1_CH_0

#define RI_ASCR1_CH_0   (0x00000001U)

Bit 0

◆ RI_ASCR1_CH_1

#define RI_ASCR1_CH_1   (0x00000002U)

Bit 1

◆ RI_ASCR1_CH_10

#define RI_ASCR1_CH_10   (0x00000400U)

Bit 10

◆ RI_ASCR1_CH_11

#define RI_ASCR1_CH_11   (0x00000800U)

Bit 11

◆ RI_ASCR1_CH_12

#define RI_ASCR1_CH_12   (0x00001000U)

Bit 12

◆ RI_ASCR1_CH_13

#define RI_ASCR1_CH_13   (0x00002000U)

Bit 13

◆ RI_ASCR1_CH_14

#define RI_ASCR1_CH_14   (0x00004000U)

Bit 14

◆ RI_ASCR1_CH_15

#define RI_ASCR1_CH_15   (0x00008000U)

Bit 15

◆ RI_ASCR1_CH_18

#define RI_ASCR1_CH_18   (0x00040000U)

Bit 18

◆ RI_ASCR1_CH_19

#define RI_ASCR1_CH_19   (0x00080000U)

Bit 19

◆ RI_ASCR1_CH_2

#define RI_ASCR1_CH_2   (0x00000004U)

Bit 2

◆ RI_ASCR1_CH_20

#define RI_ASCR1_CH_20   (0x00100000U)

Bit 20

◆ RI_ASCR1_CH_21

#define RI_ASCR1_CH_21   (0x00200000U)

Bit 21

◆ RI_ASCR1_CH_22

#define RI_ASCR1_CH_22   (0x00400000U)

Bit 22

◆ RI_ASCR1_CH_23

#define RI_ASCR1_CH_23   (0x00800000U)

Bit 23

◆ RI_ASCR1_CH_24

#define RI_ASCR1_CH_24   (0x01000000U)

Bit 24

◆ RI_ASCR1_CH_25

#define RI_ASCR1_CH_25   (0x02000000U)

Bit 25

◆ RI_ASCR1_CH_27

#define RI_ASCR1_CH_27   (0x08000000U)

Bit 27

◆ RI_ASCR1_CH_28

#define RI_ASCR1_CH_28   (0x10000000U)

Bit 28

◆ RI_ASCR1_CH_29

#define RI_ASCR1_CH_29   (0x20000000U)

Bit 29

◆ RI_ASCR1_CH_3

#define RI_ASCR1_CH_3   (0x00000008U)

Bit 3

◆ RI_ASCR1_CH_30

#define RI_ASCR1_CH_30   (0x40000000U)

Bit 30

◆ RI_ASCR1_CH_31

#define RI_ASCR1_CH_31   (0x00010000U)

Bit 16

◆ RI_ASCR1_CH_4

#define RI_ASCR1_CH_4   (0x00000010U)

Bit 4

◆ RI_ASCR1_CH_5

#define RI_ASCR1_CH_5   (0x00000020U)

Bit 5

◆ RI_ASCR1_CH_6

#define RI_ASCR1_CH_6   (0x00000040U)

Bit 6

◆ RI_ASCR1_CH_7

#define RI_ASCR1_CH_7   (0x00000080U)

Bit 7

◆ RI_ASCR1_CH_8

#define RI_ASCR1_CH_8   (0x00000100U)

Bit 8

◆ RI_ASCR1_CH_9

#define RI_ASCR1_CH_9   (0x00000200U)

Bit 9

◆ RI_ASCR1_CH_Msk

#define RI_ASCR1_CH_Msk   (0x7BFDFFFFU << RI_ASCR1_CH_Pos)

0x7BFDFFFF

◆ RI_ASCR1_CH_Pos

#define RI_ASCR1_CH_Pos   (0U)

◆ RI_ASCR1_SCM

#define RI_ASCR1_SCM   RI_ASCR1_SCM_Msk

I/O Switch control mode

◆ RI_ASCR1_SCM_Msk

#define RI_ASCR1_SCM_Msk   (0x1U << RI_ASCR1_SCM_Pos)

0x80000000

◆ RI_ASCR1_SCM_Pos

#define RI_ASCR1_SCM_Pos   (31U)

◆ RI_ASCR1_VCOMP

#define RI_ASCR1_VCOMP   RI_ASCR1_VCOMP_Msk

ADC analog switch selection for internal node to COMP1

◆ RI_ASCR1_VCOMP_Msk

#define RI_ASCR1_VCOMP_Msk   (0x1U << RI_ASCR1_VCOMP_Pos)

0x04000000

◆ RI_ASCR1_VCOMP_Pos

#define RI_ASCR1_VCOMP_Pos   (26U)

◆ RI_ASCR2_CH0b

#define RI_ASCR2_CH0b   RI_ASCR2_CH0b_Msk

CH0b selection bit

◆ RI_ASCR2_CH0b_Msk

#define RI_ASCR2_CH0b_Msk   (0x1U << RI_ASCR2_CH0b_Pos)

0x00010000

◆ RI_ASCR2_CH0b_Pos

#define RI_ASCR2_CH0b_Pos   (16U)

◆ RI_ASCR2_CH10b

#define RI_ASCR2_CH10b   RI_ASCR2_CH10b_Msk

CH10b selection bit

◆ RI_ASCR2_CH10b_Msk

#define RI_ASCR2_CH10b_Msk   (0x1U << RI_ASCR2_CH10b_Pos)

0x01000000

◆ RI_ASCR2_CH10b_Pos

#define RI_ASCR2_CH10b_Pos   (24U)

◆ RI_ASCR2_CH11b

#define RI_ASCR2_CH11b   RI_ASCR2_CH11b_Msk

CH11b selection bit

◆ RI_ASCR2_CH11b_Msk

#define RI_ASCR2_CH11b_Msk   (0x1U << RI_ASCR2_CH11b_Pos)

0x02000000

◆ RI_ASCR2_CH11b_Pos

#define RI_ASCR2_CH11b_Pos   (25U)

◆ RI_ASCR2_CH12b

#define RI_ASCR2_CH12b   RI_ASCR2_CH12b_Msk

CH12b selection bit

◆ RI_ASCR2_CH12b_Msk

#define RI_ASCR2_CH12b_Msk   (0x1U << RI_ASCR2_CH12b_Pos)

0x04000000

◆ RI_ASCR2_CH12b_Pos

#define RI_ASCR2_CH12b_Pos   (26U)

◆ RI_ASCR2_CH1b

#define RI_ASCR2_CH1b   RI_ASCR2_CH1b_Msk

CH1b selection bit

◆ RI_ASCR2_CH1b_Msk

#define RI_ASCR2_CH1b_Msk   (0x1U << RI_ASCR2_CH1b_Pos)

0x00020000

◆ RI_ASCR2_CH1b_Pos

#define RI_ASCR2_CH1b_Pos   (17U)

◆ RI_ASCR2_CH2b

#define RI_ASCR2_CH2b   RI_ASCR2_CH2b_Msk

CH2b selection bit

◆ RI_ASCR2_CH2b_Msk

#define RI_ASCR2_CH2b_Msk   (0x1U << RI_ASCR2_CH2b_Pos)

0x00040000

◆ RI_ASCR2_CH2b_Pos

#define RI_ASCR2_CH2b_Pos   (18U)

◆ RI_ASCR2_CH3b

#define RI_ASCR2_CH3b   RI_ASCR2_CH3b_Msk

CH3b selection bit

◆ RI_ASCR2_CH3b_Msk

#define RI_ASCR2_CH3b_Msk   (0x1U << RI_ASCR2_CH3b_Pos)

0x00080000

◆ RI_ASCR2_CH3b_Pos

#define RI_ASCR2_CH3b_Pos   (19U)

◆ RI_ASCR2_CH6b

#define RI_ASCR2_CH6b   RI_ASCR2_CH6b_Msk

CH6b selection bit

◆ RI_ASCR2_CH6b_Msk

#define RI_ASCR2_CH6b_Msk   (0x1U << RI_ASCR2_CH6b_Pos)

0x00100000

◆ RI_ASCR2_CH6b_Pos

#define RI_ASCR2_CH6b_Pos   (20U)

◆ RI_ASCR2_CH7b

#define RI_ASCR2_CH7b   RI_ASCR2_CH7b_Msk

CH7b selection bit

◆ RI_ASCR2_CH7b_Msk

#define RI_ASCR2_CH7b_Msk   (0x1U << RI_ASCR2_CH7b_Pos)

0x00200000

◆ RI_ASCR2_CH7b_Pos

#define RI_ASCR2_CH7b_Pos   (21U)

◆ RI_ASCR2_CH8b

#define RI_ASCR2_CH8b   RI_ASCR2_CH8b_Msk

CH8b selection bit

◆ RI_ASCR2_CH8b_Msk

#define RI_ASCR2_CH8b_Msk   (0x1U << RI_ASCR2_CH8b_Pos)

0x00400000

◆ RI_ASCR2_CH8b_Pos

#define RI_ASCR2_CH8b_Pos   (22U)

◆ RI_ASCR2_CH9b

#define RI_ASCR2_CH9b   RI_ASCR2_CH9b_Msk

CH9b selection bit

◆ RI_ASCR2_CH9b_Msk

#define RI_ASCR2_CH9b_Msk   (0x1U << RI_ASCR2_CH9b_Pos)

0x00800000

◆ RI_ASCR2_CH9b_Pos

#define RI_ASCR2_CH9b_Pos   (23U)

◆ RI_ASCR2_GR10_1

#define RI_ASCR2_GR10_1   (0x00000001U)

GR10-1 selection bit

◆ RI_ASCR2_GR10_2

#define RI_ASCR2_GR10_2   (0x00000002U)

GR10-2 selection bit

◆ RI_ASCR2_GR10_3

#define RI_ASCR2_GR10_3   (0x00000004U)

GR10-3 selection bit

◆ RI_ASCR2_GR10_4

#define RI_ASCR2_GR10_4   (0x00000008U)

GR10-4 selection bit

◆ RI_ASCR2_GR4_1

#define RI_ASCR2_GR4_1   (0x00000200U)

GR4-1 selection bit

◆ RI_ASCR2_GR4_2

#define RI_ASCR2_GR4_2   (0x00000400U)

GR4-2 selection bit

◆ RI_ASCR2_GR4_3

#define RI_ASCR2_GR4_3   (0x00000800U)

GR4-3 selection bit

◆ RI_ASCR2_GR4_4

#define RI_ASCR2_GR4_4   (0x00008000U)

GR4-4 selection bit

◆ RI_ASCR2_GR5_1

#define RI_ASCR2_GR5_1   (0x00000040U)

GR5-1 selection bit

◆ RI_ASCR2_GR5_2

#define RI_ASCR2_GR5_2   (0x00000080U)

GR5-2 selection bit

◆ RI_ASCR2_GR5_3

#define RI_ASCR2_GR5_3   (0x00000100U)

GR5-3 selection bit

◆ RI_ASCR2_GR6

#define RI_ASCR2_GR6   RI_ASCR2_GR6_Msk

GR6 selection bits

◆ RI_ASCR2_GR6_1

#define RI_ASCR2_GR6_1   (0x0000001U << RI_ASCR2_GR6_Pos)

0x00000010

◆ RI_ASCR2_GR6_2

#define RI_ASCR2_GR6_2   (0x0000002U << RI_ASCR2_GR6_Pos)

0x00000020

◆ RI_ASCR2_GR6_3

#define RI_ASCR2_GR6_3   (0x0800000U << RI_ASCR2_GR6_Pos)

0x08000000

◆ RI_ASCR2_GR6_4

#define RI_ASCR2_GR6_4   (0x1000000U << RI_ASCR2_GR6_Pos)

0x10000000

◆ RI_ASCR2_GR6_Msk

#define RI_ASCR2_GR6_Msk   (0x1800003U << RI_ASCR2_GR6_Pos)

0x18000030

◆ RI_ASCR2_GR6_Pos

#define RI_ASCR2_GR6_Pos   (4U)

◆ RI_ASMR1_PA

#define RI_ASMR1_PA   RI_ASMR1_PA_Msk

PA[15:0] Port A selection

◆ RI_ASMR1_PA_0

#define RI_ASMR1_PA_0   (0x0001U << RI_ASMR1_PA_Pos)

0x00000001

◆ RI_ASMR1_PA_1

#define RI_ASMR1_PA_1   (0x0002U << RI_ASMR1_PA_Pos)

0x00000002

◆ RI_ASMR1_PA_10

#define RI_ASMR1_PA_10   (0x0400U << RI_ASMR1_PA_Pos)

0x00000400

◆ RI_ASMR1_PA_11

#define RI_ASMR1_PA_11   (0x0800U << RI_ASMR1_PA_Pos)

0x00000800

◆ RI_ASMR1_PA_12

#define RI_ASMR1_PA_12   (0x1000U << RI_ASMR1_PA_Pos)

0x00001000

◆ RI_ASMR1_PA_13

#define RI_ASMR1_PA_13   (0x2000U << RI_ASMR1_PA_Pos)

0x00002000

◆ RI_ASMR1_PA_14

#define RI_ASMR1_PA_14   (0x4000U << RI_ASMR1_PA_Pos)

0x00004000

◆ RI_ASMR1_PA_15

#define RI_ASMR1_PA_15   (0x8000U << RI_ASMR1_PA_Pos)

0x00008000

◆ RI_ASMR1_PA_2

#define RI_ASMR1_PA_2   (0x0004U << RI_ASMR1_PA_Pos)

0x00000004

◆ RI_ASMR1_PA_3

#define RI_ASMR1_PA_3   (0x0008U << RI_ASMR1_PA_Pos)

0x00000008

◆ RI_ASMR1_PA_4

#define RI_ASMR1_PA_4   (0x0010U << RI_ASMR1_PA_Pos)

0x00000010

◆ RI_ASMR1_PA_5

#define RI_ASMR1_PA_5   (0x0020U << RI_ASMR1_PA_Pos)

0x00000020

◆ RI_ASMR1_PA_6

#define RI_ASMR1_PA_6   (0x0040U << RI_ASMR1_PA_Pos)

0x00000040

◆ RI_ASMR1_PA_7

#define RI_ASMR1_PA_7   (0x0080U << RI_ASMR1_PA_Pos)

0x00000080

◆ RI_ASMR1_PA_8

#define RI_ASMR1_PA_8   (0x0100U << RI_ASMR1_PA_Pos)

0x00000100

◆ RI_ASMR1_PA_9

#define RI_ASMR1_PA_9   (0x0200U << RI_ASMR1_PA_Pos)

0x00000200

◆ RI_ASMR1_PA_Msk

#define RI_ASMR1_PA_Msk   (0xFFFFU << RI_ASMR1_PA_Pos)

0x0000FFFF

◆ RI_ASMR1_PA_Pos

#define RI_ASMR1_PA_Pos   (0U)

◆ RI_ASMR2_PB

#define RI_ASMR2_PB   RI_ASMR2_PB_Msk

PB[15:0] Port B selection

◆ RI_ASMR2_PB_0

#define RI_ASMR2_PB_0   (0x0001U << RI_ASMR2_PB_Pos)

0x00000001

◆ RI_ASMR2_PB_1

#define RI_ASMR2_PB_1   (0x0002U << RI_ASMR2_PB_Pos)

0x00000002

◆ RI_ASMR2_PB_10

#define RI_ASMR2_PB_10   (0x0400U << RI_ASMR2_PB_Pos)

0x00000400

◆ RI_ASMR2_PB_11

#define RI_ASMR2_PB_11   (0x0800U << RI_ASMR2_PB_Pos)

0x00000800

◆ RI_ASMR2_PB_12

#define RI_ASMR2_PB_12   (0x1000U << RI_ASMR2_PB_Pos)

0x00001000

◆ RI_ASMR2_PB_13

#define RI_ASMR2_PB_13   (0x2000U << RI_ASMR2_PB_Pos)

0x00002000

◆ RI_ASMR2_PB_14

#define RI_ASMR2_PB_14   (0x4000U << RI_ASMR2_PB_Pos)

0x00004000

◆ RI_ASMR2_PB_15

#define RI_ASMR2_PB_15   (0x8000U << RI_ASMR2_PB_Pos)

0x00008000

◆ RI_ASMR2_PB_2

#define RI_ASMR2_PB_2   (0x0004U << RI_ASMR2_PB_Pos)

0x00000004

◆ RI_ASMR2_PB_3

#define RI_ASMR2_PB_3   (0x0008U << RI_ASMR2_PB_Pos)

0x00000008

◆ RI_ASMR2_PB_4

#define RI_ASMR2_PB_4   (0x0010U << RI_ASMR2_PB_Pos)

0x00000010

◆ RI_ASMR2_PB_5

#define RI_ASMR2_PB_5   (0x0020U << RI_ASMR2_PB_Pos)

0x00000020

◆ RI_ASMR2_PB_6

#define RI_ASMR2_PB_6   (0x0040U << RI_ASMR2_PB_Pos)

0x00000040

◆ RI_ASMR2_PB_7

#define RI_ASMR2_PB_7   (0x0080U << RI_ASMR2_PB_Pos)

0x00000080

◆ RI_ASMR2_PB_8

#define RI_ASMR2_PB_8   (0x0100U << RI_ASMR2_PB_Pos)

0x00000100

◆ RI_ASMR2_PB_9

#define RI_ASMR2_PB_9   (0x0200U << RI_ASMR2_PB_Pos)

0x00000200

◆ RI_ASMR2_PB_Msk

#define RI_ASMR2_PB_Msk   (0xFFFFU << RI_ASMR2_PB_Pos)

0x0000FFFF

◆ RI_ASMR2_PB_Pos

#define RI_ASMR2_PB_Pos   (0U)

◆ RI_ASMR3_PC

#define RI_ASMR3_PC   RI_ASMR3_PC_Msk

PC[15:0] Port C selection

◆ RI_ASMR3_PC_0

#define RI_ASMR3_PC_0   (0x0001U << RI_ASMR3_PC_Pos)

0x00000001

◆ RI_ASMR3_PC_1

#define RI_ASMR3_PC_1   (0x0002U << RI_ASMR3_PC_Pos)

0x00000002

◆ RI_ASMR3_PC_10

#define RI_ASMR3_PC_10   (0x0400U << RI_ASMR3_PC_Pos)

0x00000400

◆ RI_ASMR3_PC_11

#define RI_ASMR3_PC_11   (0x0800U << RI_ASMR3_PC_Pos)

0x00000800

◆ RI_ASMR3_PC_12

#define RI_ASMR3_PC_12   (0x1000U << RI_ASMR3_PC_Pos)

0x00001000

◆ RI_ASMR3_PC_13

#define RI_ASMR3_PC_13   (0x2000U << RI_ASMR3_PC_Pos)

0x00002000

◆ RI_ASMR3_PC_14

#define RI_ASMR3_PC_14   (0x4000U << RI_ASMR3_PC_Pos)

0x00004000

◆ RI_ASMR3_PC_15

#define RI_ASMR3_PC_15   (0x8000U << RI_ASMR3_PC_Pos)

0x00008000

◆ RI_ASMR3_PC_2

#define RI_ASMR3_PC_2   (0x0004U << RI_ASMR3_PC_Pos)

0x00000004

◆ RI_ASMR3_PC_3

#define RI_ASMR3_PC_3   (0x0008U << RI_ASMR3_PC_Pos)

0x00000008

◆ RI_ASMR3_PC_4

#define RI_ASMR3_PC_4   (0x0010U << RI_ASMR3_PC_Pos)

0x00000010

◆ RI_ASMR3_PC_5

#define RI_ASMR3_PC_5   (0x0020U << RI_ASMR3_PC_Pos)

0x00000020

◆ RI_ASMR3_PC_6

#define RI_ASMR3_PC_6   (0x0040U << RI_ASMR3_PC_Pos)

0x00000040

◆ RI_ASMR3_PC_7

#define RI_ASMR3_PC_7   (0x0080U << RI_ASMR3_PC_Pos)

0x00000080

◆ RI_ASMR3_PC_8

#define RI_ASMR3_PC_8   (0x0100U << RI_ASMR3_PC_Pos)

0x00000100

◆ RI_ASMR3_PC_9

#define RI_ASMR3_PC_9   (0x0200U << RI_ASMR3_PC_Pos)

0x00000200

◆ RI_ASMR3_PC_Msk

#define RI_ASMR3_PC_Msk   (0xFFFFU << RI_ASMR3_PC_Pos)

0x0000FFFF

◆ RI_ASMR3_PC_Pos

#define RI_ASMR3_PC_Pos   (0U)

◆ RI_ASMR4_PF

#define RI_ASMR4_PF   RI_ASMR4_PF_Msk

PF[15:0] Port F selection

◆ RI_ASMR4_PF_0

#define RI_ASMR4_PF_0   (0x0001U << RI_ASMR4_PF_Pos)

0x00000001

◆ RI_ASMR4_PF_1

#define RI_ASMR4_PF_1   (0x0002U << RI_ASMR4_PF_Pos)

0x00000002

◆ RI_ASMR4_PF_10

#define RI_ASMR4_PF_10   (0x0400U << RI_ASMR4_PF_Pos)

0x00000400

◆ RI_ASMR4_PF_11

#define RI_ASMR4_PF_11   (0x0800U << RI_ASMR4_PF_Pos)

0x00000800

◆ RI_ASMR4_PF_12

#define RI_ASMR4_PF_12   (0x1000U << RI_ASMR4_PF_Pos)

0x00001000

◆ RI_ASMR4_PF_13

#define RI_ASMR4_PF_13   (0x2000U << RI_ASMR4_PF_Pos)

0x00002000

◆ RI_ASMR4_PF_14

#define RI_ASMR4_PF_14   (0x4000U << RI_ASMR4_PF_Pos)

0x00004000

◆ RI_ASMR4_PF_15

#define RI_ASMR4_PF_15   (0x8000U << RI_ASMR4_PF_Pos)

0x00008000

◆ RI_ASMR4_PF_2

#define RI_ASMR4_PF_2   (0x0004U << RI_ASMR4_PF_Pos)

0x00000004

◆ RI_ASMR4_PF_3

#define RI_ASMR4_PF_3   (0x0008U << RI_ASMR4_PF_Pos)

0x00000008

◆ RI_ASMR4_PF_4

#define RI_ASMR4_PF_4   (0x0010U << RI_ASMR4_PF_Pos)

0x00000010

◆ RI_ASMR4_PF_5

#define RI_ASMR4_PF_5   (0x0020U << RI_ASMR4_PF_Pos)

0x00000020

◆ RI_ASMR4_PF_6

#define RI_ASMR4_PF_6   (0x0040U << RI_ASMR4_PF_Pos)

0x00000040

◆ RI_ASMR4_PF_7

#define RI_ASMR4_PF_7   (0x0080U << RI_ASMR4_PF_Pos)

0x00000080

◆ RI_ASMR4_PF_8

#define RI_ASMR4_PF_8   (0x0100U << RI_ASMR4_PF_Pos)

0x00000100

◆ RI_ASMR4_PF_9

#define RI_ASMR4_PF_9   (0x0200U << RI_ASMR4_PF_Pos)

0x00000200

◆ RI_ASMR4_PF_Msk

#define RI_ASMR4_PF_Msk   (0xFFFFU << RI_ASMR4_PF_Pos)

0x0000FFFF

◆ RI_ASMR4_PF_Pos

#define RI_ASMR4_PF_Pos   (0U)

◆ RI_ASMR5_PG

#define RI_ASMR5_PG   RI_ASMR5_PG_Msk

PG[15:0] Port G selection

◆ RI_ASMR5_PG_0

#define RI_ASMR5_PG_0   (0x0001U << RI_ASMR5_PG_Pos)

0x00000001

◆ RI_ASMR5_PG_1

#define RI_ASMR5_PG_1   (0x0002U << RI_ASMR5_PG_Pos)

0x00000002

◆ RI_ASMR5_PG_10

#define RI_ASMR5_PG_10   (0x0400U << RI_ASMR5_PG_Pos)

0x00000400

◆ RI_ASMR5_PG_11

#define RI_ASMR5_PG_11   (0x0800U << RI_ASMR5_PG_Pos)

0x00000800

◆ RI_ASMR5_PG_12

#define RI_ASMR5_PG_12   (0x1000U << RI_ASMR5_PG_Pos)

0x00001000

◆ RI_ASMR5_PG_13

#define RI_ASMR5_PG_13   (0x2000U << RI_ASMR5_PG_Pos)

0x00002000

◆ RI_ASMR5_PG_14

#define RI_ASMR5_PG_14   (0x4000U << RI_ASMR5_PG_Pos)

0x00004000

◆ RI_ASMR5_PG_15

#define RI_ASMR5_PG_15   (0x8000U << RI_ASMR5_PG_Pos)

0x00008000

◆ RI_ASMR5_PG_2

#define RI_ASMR5_PG_2   (0x0004U << RI_ASMR5_PG_Pos)

0x00000004

◆ RI_ASMR5_PG_3

#define RI_ASMR5_PG_3   (0x0008U << RI_ASMR5_PG_Pos)

0x00000008

◆ RI_ASMR5_PG_4

#define RI_ASMR5_PG_4   (0x0010U << RI_ASMR5_PG_Pos)

0x00000010

◆ RI_ASMR5_PG_5

#define RI_ASMR5_PG_5   (0x0020U << RI_ASMR5_PG_Pos)

0x00000020

◆ RI_ASMR5_PG_6

#define RI_ASMR5_PG_6   (0x0040U << RI_ASMR5_PG_Pos)

0x00000040

◆ RI_ASMR5_PG_7

#define RI_ASMR5_PG_7   (0x0080U << RI_ASMR5_PG_Pos)

0x00000080

◆ RI_ASMR5_PG_8

#define RI_ASMR5_PG_8   (0x0100U << RI_ASMR5_PG_Pos)

0x00000100

◆ RI_ASMR5_PG_9

#define RI_ASMR5_PG_9   (0x0200U << RI_ASMR5_PG_Pos)

0x00000200

◆ RI_ASMR5_PG_Msk

#define RI_ASMR5_PG_Msk   (0xFFFFU << RI_ASMR5_PG_Pos)

0x0000FFFF

◆ RI_ASMR5_PG_Pos

#define RI_ASMR5_PG_Pos   (0U)

◆ RI_CICR1_PA

#define RI_CICR1_PA   RI_CICR1_PA_Msk

PA[15:0] Port A selection

◆ RI_CICR1_PA_0

#define RI_CICR1_PA_0   (0x0001U << RI_CICR1_PA_Pos)

0x00000001

◆ RI_CICR1_PA_1

#define RI_CICR1_PA_1   (0x0002U << RI_CICR1_PA_Pos)

0x00000002

◆ RI_CICR1_PA_10

#define RI_CICR1_PA_10   (0x0400U << RI_CICR1_PA_Pos)

0x00000400

◆ RI_CICR1_PA_11

#define RI_CICR1_PA_11   (0x0800U << RI_CICR1_PA_Pos)

0x00000800

◆ RI_CICR1_PA_12

#define RI_CICR1_PA_12   (0x1000U << RI_CICR1_PA_Pos)

0x00001000

◆ RI_CICR1_PA_13

#define RI_CICR1_PA_13   (0x2000U << RI_CICR1_PA_Pos)

0x00002000

◆ RI_CICR1_PA_14

#define RI_CICR1_PA_14   (0x4000U << RI_CICR1_PA_Pos)

0x00004000

◆ RI_CICR1_PA_15

#define RI_CICR1_PA_15   (0x8000U << RI_CICR1_PA_Pos)

0x00008000

◆ RI_CICR1_PA_2

#define RI_CICR1_PA_2   (0x0004U << RI_CICR1_PA_Pos)

0x00000004

◆ RI_CICR1_PA_3

#define RI_CICR1_PA_3   (0x0008U << RI_CICR1_PA_Pos)

0x00000008

◆ RI_CICR1_PA_4

#define RI_CICR1_PA_4   (0x0010U << RI_CICR1_PA_Pos)

0x00000010

◆ RI_CICR1_PA_5

#define RI_CICR1_PA_5   (0x0020U << RI_CICR1_PA_Pos)

0x00000020

◆ RI_CICR1_PA_6

#define RI_CICR1_PA_6   (0x0040U << RI_CICR1_PA_Pos)

0x00000040

◆ RI_CICR1_PA_7

#define RI_CICR1_PA_7   (0x0080U << RI_CICR1_PA_Pos)

0x00000080

◆ RI_CICR1_PA_8

#define RI_CICR1_PA_8   (0x0100U << RI_CICR1_PA_Pos)

0x00000100

◆ RI_CICR1_PA_9

#define RI_CICR1_PA_9   (0x0200U << RI_CICR1_PA_Pos)

0x00000200

◆ RI_CICR1_PA_Msk

#define RI_CICR1_PA_Msk   (0xFFFFU << RI_CICR1_PA_Pos)

0x0000FFFF

◆ RI_CICR1_PA_Pos

#define RI_CICR1_PA_Pos   (0U)

◆ RI_CICR2_PB

#define RI_CICR2_PB   RI_CICR2_PB_Msk

PB[15:0] Port B selection

◆ RI_CICR2_PB_0

#define RI_CICR2_PB_0   (0x0001U << RI_CICR2_PB_Pos)

0x00000001

◆ RI_CICR2_PB_1

#define RI_CICR2_PB_1   (0x0002U << RI_CICR2_PB_Pos)

0x00000002

◆ RI_CICR2_PB_10

#define RI_CICR2_PB_10   (0x0400U << RI_CICR2_PB_Pos)

0x00000400

◆ RI_CICR2_PB_11

#define RI_CICR2_PB_11   (0x0800U << RI_CICR2_PB_Pos)

0x00000800

◆ RI_CICR2_PB_12

#define RI_CICR2_PB_12   (0x1000U << RI_CICR2_PB_Pos)

0x00001000

◆ RI_CICR2_PB_13

#define RI_CICR2_PB_13   (0x2000U << RI_CICR2_PB_Pos)

0x00002000

◆ RI_CICR2_PB_14

#define RI_CICR2_PB_14   (0x4000U << RI_CICR2_PB_Pos)

0x00004000

◆ RI_CICR2_PB_15

#define RI_CICR2_PB_15   (0x8000U << RI_CICR2_PB_Pos)

0x00008000

◆ RI_CICR2_PB_2

#define RI_CICR2_PB_2   (0x0004U << RI_CICR2_PB_Pos)

0x00000004

◆ RI_CICR2_PB_3

#define RI_CICR2_PB_3   (0x0008U << RI_CICR2_PB_Pos)

0x00000008

◆ RI_CICR2_PB_4

#define RI_CICR2_PB_4   (0x0010U << RI_CICR2_PB_Pos)

0x00000010

◆ RI_CICR2_PB_5

#define RI_CICR2_PB_5   (0x0020U << RI_CICR2_PB_Pos)

0x00000020

◆ RI_CICR2_PB_6

#define RI_CICR2_PB_6   (0x0040U << RI_CICR2_PB_Pos)

0x00000040

◆ RI_CICR2_PB_7

#define RI_CICR2_PB_7   (0x0080U << RI_CICR2_PB_Pos)

0x00000080

◆ RI_CICR2_PB_8

#define RI_CICR2_PB_8   (0x0100U << RI_CICR2_PB_Pos)

0x00000100

◆ RI_CICR2_PB_9

#define RI_CICR2_PB_9   (0x0200U << RI_CICR2_PB_Pos)

0x00000200

◆ RI_CICR2_PB_Msk

#define RI_CICR2_PB_Msk   (0xFFFFU << RI_CICR2_PB_Pos)

0x0000FFFF

◆ RI_CICR2_PB_Pos

#define RI_CICR2_PB_Pos   (0U)

◆ RI_CICR3_PC

#define RI_CICR3_PC   RI_CICR3_PC_Msk

PC[15:0] Port C selection

◆ RI_CICR3_PC_0

#define RI_CICR3_PC_0   (0x0001U << RI_CICR3_PC_Pos)

0x00000001

◆ RI_CICR3_PC_1

#define RI_CICR3_PC_1   (0x0002U << RI_CICR3_PC_Pos)

0x00000002

◆ RI_CICR3_PC_10

#define RI_CICR3_PC_10   (0x0400U << RI_CICR3_PC_Pos)

0x00000400

◆ RI_CICR3_PC_11

#define RI_CICR3_PC_11   (0x0800U << RI_CICR3_PC_Pos)

0x00000800

◆ RI_CICR3_PC_12

#define RI_CICR3_PC_12   (0x1000U << RI_CICR3_PC_Pos)

0x00001000

◆ RI_CICR3_PC_13

#define RI_CICR3_PC_13   (0x2000U << RI_CICR3_PC_Pos)

0x00002000

◆ RI_CICR3_PC_14

#define RI_CICR3_PC_14   (0x4000U << RI_CICR3_PC_Pos)

0x00004000

◆ RI_CICR3_PC_15

#define RI_CICR3_PC_15   (0x8000U << RI_CICR3_PC_Pos)

0x00008000

◆ RI_CICR3_PC_2

#define RI_CICR3_PC_2   (0x0004U << RI_CICR3_PC_Pos)

0x00000004

◆ RI_CICR3_PC_3

#define RI_CICR3_PC_3   (0x0008U << RI_CICR3_PC_Pos)

0x00000008

◆ RI_CICR3_PC_4

#define RI_CICR3_PC_4   (0x0010U << RI_CICR3_PC_Pos)

0x00000010

◆ RI_CICR3_PC_5

#define RI_CICR3_PC_5   (0x0020U << RI_CICR3_PC_Pos)

0x00000020

◆ RI_CICR3_PC_6

#define RI_CICR3_PC_6   (0x0040U << RI_CICR3_PC_Pos)

0x00000040

◆ RI_CICR3_PC_7

#define RI_CICR3_PC_7   (0x0080U << RI_CICR3_PC_Pos)

0x00000080

◆ RI_CICR3_PC_8

#define RI_CICR3_PC_8   (0x0100U << RI_CICR3_PC_Pos)

0x00000100

◆ RI_CICR3_PC_9

#define RI_CICR3_PC_9   (0x0200U << RI_CICR3_PC_Pos)

0x00000200

◆ RI_CICR3_PC_Msk

#define RI_CICR3_PC_Msk   (0xFFFFU << RI_CICR3_PC_Pos)

0x0000FFFF

◆ RI_CICR3_PC_Pos

#define RI_CICR3_PC_Pos   (0U)

◆ RI_CICR4_PF

#define RI_CICR4_PF   RI_CICR4_PF_Msk

PF[15:0] Port F selection

◆ RI_CICR4_PF_0

#define RI_CICR4_PF_0   (0x0001U << RI_CICR4_PF_Pos)

0x00000001

◆ RI_CICR4_PF_1

#define RI_CICR4_PF_1   (0x0002U << RI_CICR4_PF_Pos)

0x00000002

◆ RI_CICR4_PF_10

#define RI_CICR4_PF_10   (0x0400U << RI_CICR4_PF_Pos)

0x00000400

◆ RI_CICR4_PF_11

#define RI_CICR4_PF_11   (0x0800U << RI_CICR4_PF_Pos)

0x00000800

◆ RI_CICR4_PF_12

#define RI_CICR4_PF_12   (0x1000U << RI_CICR4_PF_Pos)

0x00001000

◆ RI_CICR4_PF_13

#define RI_CICR4_PF_13   (0x2000U << RI_CICR4_PF_Pos)

0x00002000

◆ RI_CICR4_PF_14

#define RI_CICR4_PF_14   (0x4000U << RI_CICR4_PF_Pos)

0x00004000

◆ RI_CICR4_PF_15

#define RI_CICR4_PF_15   (0x8000U << RI_CICR4_PF_Pos)

0x00008000

◆ RI_CICR4_PF_2

#define RI_CICR4_PF_2   (0x0004U << RI_CICR4_PF_Pos)

0x00000004

◆ RI_CICR4_PF_3

#define RI_CICR4_PF_3   (0x0008U << RI_CICR4_PF_Pos)

0x00000008

◆ RI_CICR4_PF_4

#define RI_CICR4_PF_4   (0x0010U << RI_CICR4_PF_Pos)

0x00000010

◆ RI_CICR4_PF_5

#define RI_CICR4_PF_5   (0x0020U << RI_CICR4_PF_Pos)

0x00000020

◆ RI_CICR4_PF_6

#define RI_CICR4_PF_6   (0x0040U << RI_CICR4_PF_Pos)

0x00000040

◆ RI_CICR4_PF_7

#define RI_CICR4_PF_7   (0x0080U << RI_CICR4_PF_Pos)

0x00000080

◆ RI_CICR4_PF_8

#define RI_CICR4_PF_8   (0x0100U << RI_CICR4_PF_Pos)

0x00000100

◆ RI_CICR4_PF_9

#define RI_CICR4_PF_9   (0x0200U << RI_CICR4_PF_Pos)

0x00000200

◆ RI_CICR4_PF_Msk

#define RI_CICR4_PF_Msk   (0xFFFFU << RI_CICR4_PF_Pos)

0x0000FFFF

◆ RI_CICR4_PF_Pos

#define RI_CICR4_PF_Pos   (0U)

◆ RI_CICR5_PG

#define RI_CICR5_PG   RI_CICR5_PG_Msk

PG[15:0] Port G selection

◆ RI_CICR5_PG_0

#define RI_CICR5_PG_0   (0x0001U << RI_CICR5_PG_Pos)

0x00000001

◆ RI_CICR5_PG_1

#define RI_CICR5_PG_1   (0x0002U << RI_CICR5_PG_Pos)

0x00000002

◆ RI_CICR5_PG_10

#define RI_CICR5_PG_10   (0x0400U << RI_CICR5_PG_Pos)

0x00000400

◆ RI_CICR5_PG_11

#define RI_CICR5_PG_11   (0x0800U << RI_CICR5_PG_Pos)

0x00000800

◆ RI_CICR5_PG_12

#define RI_CICR5_PG_12   (0x1000U << RI_CICR5_PG_Pos)

0x00001000

◆ RI_CICR5_PG_13

#define RI_CICR5_PG_13   (0x2000U << RI_CICR5_PG_Pos)

0x00002000

◆ RI_CICR5_PG_14

#define RI_CICR5_PG_14   (0x4000U << RI_CICR5_PG_Pos)

0x00004000

◆ RI_CICR5_PG_15

#define RI_CICR5_PG_15   (0x8000U << RI_CICR5_PG_Pos)

0x00008000

◆ RI_CICR5_PG_2

#define RI_CICR5_PG_2   (0x0004U << RI_CICR5_PG_Pos)

0x00000004

◆ RI_CICR5_PG_3

#define RI_CICR5_PG_3   (0x0008U << RI_CICR5_PG_Pos)

0x00000008

◆ RI_CICR5_PG_4

#define RI_CICR5_PG_4   (0x0010U << RI_CICR5_PG_Pos)

0x00000010

◆ RI_CICR5_PG_5

#define RI_CICR5_PG_5   (0x0020U << RI_CICR5_PG_Pos)

0x00000020

◆ RI_CICR5_PG_6

#define RI_CICR5_PG_6   (0x0040U << RI_CICR5_PG_Pos)

0x00000040

◆ RI_CICR5_PG_7

#define RI_CICR5_PG_7   (0x0080U << RI_CICR5_PG_Pos)

0x00000080

◆ RI_CICR5_PG_8

#define RI_CICR5_PG_8   (0x0100U << RI_CICR5_PG_Pos)

0x00000100

◆ RI_CICR5_PG_9

#define RI_CICR5_PG_9   (0x0200U << RI_CICR5_PG_Pos)

0x00000200

◆ RI_CICR5_PG_Msk

#define RI_CICR5_PG_Msk   (0xFFFFU << RI_CICR5_PG_Pos)

0x0000FFFF

◆ RI_CICR5_PG_Pos

#define RI_CICR5_PG_Pos   (0U)

◆ RI_CMR1_PA

#define RI_CMR1_PA   RI_CMR1_PA_Msk

PA[15:0] Port A selection

◆ RI_CMR1_PA_0

#define RI_CMR1_PA_0   (0x0001U << RI_CMR1_PA_Pos)

0x00000001

◆ RI_CMR1_PA_1

#define RI_CMR1_PA_1   (0x0002U << RI_CMR1_PA_Pos)

0x00000002

◆ RI_CMR1_PA_10

#define RI_CMR1_PA_10   (0x0400U << RI_CMR1_PA_Pos)

0x00000400

◆ RI_CMR1_PA_11

#define RI_CMR1_PA_11   (0x0800U << RI_CMR1_PA_Pos)

0x00000800

◆ RI_CMR1_PA_12

#define RI_CMR1_PA_12   (0x1000U << RI_CMR1_PA_Pos)

0x00001000

◆ RI_CMR1_PA_13

#define RI_CMR1_PA_13   (0x2000U << RI_CMR1_PA_Pos)

0x00002000

◆ RI_CMR1_PA_14

#define RI_CMR1_PA_14   (0x4000U << RI_CMR1_PA_Pos)

0x00004000

◆ RI_CMR1_PA_15

#define RI_CMR1_PA_15   (0x8000U << RI_CMR1_PA_Pos)

0x00008000

◆ RI_CMR1_PA_2

#define RI_CMR1_PA_2   (0x0004U << RI_CMR1_PA_Pos)

0x00000004

◆ RI_CMR1_PA_3

#define RI_CMR1_PA_3   (0x0008U << RI_CMR1_PA_Pos)

0x00000008

◆ RI_CMR1_PA_4

#define RI_CMR1_PA_4   (0x0010U << RI_CMR1_PA_Pos)

0x00000010

◆ RI_CMR1_PA_5

#define RI_CMR1_PA_5   (0x0020U << RI_CMR1_PA_Pos)

0x00000020

◆ RI_CMR1_PA_6

#define RI_CMR1_PA_6   (0x0040U << RI_CMR1_PA_Pos)

0x00000040

◆ RI_CMR1_PA_7

#define RI_CMR1_PA_7   (0x0080U << RI_CMR1_PA_Pos)

0x00000080

◆ RI_CMR1_PA_8

#define RI_CMR1_PA_8   (0x0100U << RI_CMR1_PA_Pos)

0x00000100

◆ RI_CMR1_PA_9

#define RI_CMR1_PA_9   (0x0200U << RI_CMR1_PA_Pos)

0x00000200

◆ RI_CMR1_PA_Msk

#define RI_CMR1_PA_Msk   (0xFFFFU << RI_CMR1_PA_Pos)

0x0000FFFF

◆ RI_CMR1_PA_Pos

#define RI_CMR1_PA_Pos   (0U)

◆ RI_CMR2_PB

#define RI_CMR2_PB   RI_CMR2_PB_Msk

PB[15:0] Port B selection

◆ RI_CMR2_PB_0

#define RI_CMR2_PB_0   (0x0001U << RI_CMR2_PB_Pos)

0x00000001

◆ RI_CMR2_PB_1

#define RI_CMR2_PB_1   (0x0002U << RI_CMR2_PB_Pos)

0x00000002

◆ RI_CMR2_PB_10

#define RI_CMR2_PB_10   (0x0400U << RI_CMR2_PB_Pos)

0x00000400

◆ RI_CMR2_PB_11

#define RI_CMR2_PB_11   (0x0800U << RI_CMR2_PB_Pos)

0x00000800

◆ RI_CMR2_PB_12

#define RI_CMR2_PB_12   (0x1000U << RI_CMR2_PB_Pos)

0x00001000

◆ RI_CMR2_PB_13

#define RI_CMR2_PB_13   (0x2000U << RI_CMR2_PB_Pos)

0x00002000

◆ RI_CMR2_PB_14

#define RI_CMR2_PB_14   (0x4000U << RI_CMR2_PB_Pos)

0x00004000

◆ RI_CMR2_PB_15

#define RI_CMR2_PB_15   (0x8000U << RI_CMR2_PB_Pos)

0x00008000

◆ RI_CMR2_PB_2

#define RI_CMR2_PB_2   (0x0004U << RI_CMR2_PB_Pos)

0x00000004

◆ RI_CMR2_PB_3

#define RI_CMR2_PB_3   (0x0008U << RI_CMR2_PB_Pos)

0x00000008

◆ RI_CMR2_PB_4

#define RI_CMR2_PB_4   (0x0010U << RI_CMR2_PB_Pos)

0x00000010

◆ RI_CMR2_PB_5

#define RI_CMR2_PB_5   (0x0020U << RI_CMR2_PB_Pos)

0x00000020

◆ RI_CMR2_PB_6

#define RI_CMR2_PB_6   (0x0040U << RI_CMR2_PB_Pos)

0x00000040

◆ RI_CMR2_PB_7

#define RI_CMR2_PB_7   (0x0080U << RI_CMR2_PB_Pos)

0x00000080

◆ RI_CMR2_PB_8

#define RI_CMR2_PB_8   (0x0100U << RI_CMR2_PB_Pos)

0x00000100

◆ RI_CMR2_PB_9

#define RI_CMR2_PB_9   (0x0200U << RI_CMR2_PB_Pos)

0x00000200

◆ RI_CMR2_PB_Msk

#define RI_CMR2_PB_Msk   (0xFFFFU << RI_CMR2_PB_Pos)

0x0000FFFF

◆ RI_CMR2_PB_Pos

#define RI_CMR2_PB_Pos   (0U)

◆ RI_CMR3_PC

#define RI_CMR3_PC   RI_CMR3_PC_Msk

PC[15:0] Port C selection

◆ RI_CMR3_PC_0

#define RI_CMR3_PC_0   (0x0001U << RI_CMR3_PC_Pos)

0x00000001

◆ RI_CMR3_PC_1

#define RI_CMR3_PC_1   (0x0002U << RI_CMR3_PC_Pos)

0x00000002

◆ RI_CMR3_PC_10

#define RI_CMR3_PC_10   (0x0400U << RI_CMR3_PC_Pos)

0x00000400

◆ RI_CMR3_PC_11

#define RI_CMR3_PC_11   (0x0800U << RI_CMR3_PC_Pos)

0x00000800

◆ RI_CMR3_PC_12

#define RI_CMR3_PC_12   (0x1000U << RI_CMR3_PC_Pos)

0x00001000

◆ RI_CMR3_PC_13

#define RI_CMR3_PC_13   (0x2000U << RI_CMR3_PC_Pos)

0x00002000

◆ RI_CMR3_PC_14

#define RI_CMR3_PC_14   (0x4000U << RI_CMR3_PC_Pos)

0x00004000

◆ RI_CMR3_PC_15

#define RI_CMR3_PC_15   (0x8000U << RI_CMR3_PC_Pos)

0x00008000

◆ RI_CMR3_PC_2

#define RI_CMR3_PC_2   (0x0004U << RI_CMR3_PC_Pos)

0x00000004

◆ RI_CMR3_PC_3

#define RI_CMR3_PC_3   (0x0008U << RI_CMR3_PC_Pos)

0x00000008

◆ RI_CMR3_PC_4

#define RI_CMR3_PC_4   (0x0010U << RI_CMR3_PC_Pos)

0x00000010

◆ RI_CMR3_PC_5

#define RI_CMR3_PC_5   (0x0020U << RI_CMR3_PC_Pos)

0x00000020

◆ RI_CMR3_PC_6

#define RI_CMR3_PC_6   (0x0040U << RI_CMR3_PC_Pos)

0x00000040

◆ RI_CMR3_PC_7

#define RI_CMR3_PC_7   (0x0080U << RI_CMR3_PC_Pos)

0x00000080

◆ RI_CMR3_PC_8

#define RI_CMR3_PC_8   (0x0100U << RI_CMR3_PC_Pos)

0x00000100

◆ RI_CMR3_PC_9

#define RI_CMR3_PC_9   (0x0200U << RI_CMR3_PC_Pos)

0x00000200

◆ RI_CMR3_PC_Msk

#define RI_CMR3_PC_Msk   (0xFFFFU << RI_CMR3_PC_Pos)

0x0000FFFF

◆ RI_CMR3_PC_Pos

#define RI_CMR3_PC_Pos   (0U)

◆ RI_CMR4_PF

#define RI_CMR4_PF   RI_CMR4_PF_Msk

PF[15:0] Port F selection

◆ RI_CMR4_PF_0

#define RI_CMR4_PF_0   (0x0001U << RI_CMR4_PF_Pos)

0x00000001

◆ RI_CMR4_PF_1

#define RI_CMR4_PF_1   (0x0002U << RI_CMR4_PF_Pos)

0x00000002

◆ RI_CMR4_PF_10

#define RI_CMR4_PF_10   (0x0400U << RI_CMR4_PF_Pos)

0x00000400

◆ RI_CMR4_PF_11

#define RI_CMR4_PF_11   (0x0800U << RI_CMR4_PF_Pos)

0x00000800

◆ RI_CMR4_PF_12

#define RI_CMR4_PF_12   (0x1000U << RI_CMR4_PF_Pos)

0x00001000

◆ RI_CMR4_PF_13

#define RI_CMR4_PF_13   (0x2000U << RI_CMR4_PF_Pos)

0x00002000

◆ RI_CMR4_PF_14

#define RI_CMR4_PF_14   (0x4000U << RI_CMR4_PF_Pos)

0x00004000

◆ RI_CMR4_PF_15

#define RI_CMR4_PF_15   (0x8000U << RI_CMR4_PF_Pos)

0x00008000

◆ RI_CMR4_PF_2

#define RI_CMR4_PF_2   (0x0004U << RI_CMR4_PF_Pos)

0x00000004

◆ RI_CMR4_PF_3

#define RI_CMR4_PF_3   (0x0008U << RI_CMR4_PF_Pos)

0x00000008

◆ RI_CMR4_PF_4

#define RI_CMR4_PF_4   (0x0010U << RI_CMR4_PF_Pos)

0x00000010

◆ RI_CMR4_PF_5

#define RI_CMR4_PF_5   (0x0020U << RI_CMR4_PF_Pos)

0x00000020

◆ RI_CMR4_PF_6

#define RI_CMR4_PF_6   (0x0040U << RI_CMR4_PF_Pos)

0x00000040

◆ RI_CMR4_PF_7

#define RI_CMR4_PF_7   (0x0080U << RI_CMR4_PF_Pos)

0x00000080

◆ RI_CMR4_PF_8

#define RI_CMR4_PF_8   (0x0100U << RI_CMR4_PF_Pos)

0x00000100

◆ RI_CMR4_PF_9

#define RI_CMR4_PF_9   (0x0200U << RI_CMR4_PF_Pos)

0x00000200

◆ RI_CMR4_PF_Msk

#define RI_CMR4_PF_Msk   (0xFFFFU << RI_CMR4_PF_Pos)

0x0000FFFF

◆ RI_CMR4_PF_Pos

#define RI_CMR4_PF_Pos   (0U)

◆ RI_CMR5_PG

#define RI_CMR5_PG   RI_CMR5_PG_Msk

PG[15:0] Port G selection

◆ RI_CMR5_PG_0

#define RI_CMR5_PG_0   (0x0001U << RI_CMR5_PG_Pos)

0x00000001

◆ RI_CMR5_PG_1

#define RI_CMR5_PG_1   (0x0002U << RI_CMR5_PG_Pos)

0x00000002

◆ RI_CMR5_PG_10

#define RI_CMR5_PG_10   (0x0400U << RI_CMR5_PG_Pos)

0x00000400

◆ RI_CMR5_PG_11

#define RI_CMR5_PG_11   (0x0800U << RI_CMR5_PG_Pos)

0x00000800

◆ RI_CMR5_PG_12

#define RI_CMR5_PG_12   (0x1000U << RI_CMR5_PG_Pos)

0x00001000

◆ RI_CMR5_PG_13

#define RI_CMR5_PG_13   (0x2000U << RI_CMR5_PG_Pos)

0x00002000

◆ RI_CMR5_PG_14

#define RI_CMR5_PG_14   (0x4000U << RI_CMR5_PG_Pos)

0x00004000

◆ RI_CMR5_PG_15

#define RI_CMR5_PG_15   (0x8000U << RI_CMR5_PG_Pos)

0x00008000

◆ RI_CMR5_PG_2

#define RI_CMR5_PG_2   (0x0004U << RI_CMR5_PG_Pos)

0x00000004

◆ RI_CMR5_PG_3

#define RI_CMR5_PG_3   (0x0008U << RI_CMR5_PG_Pos)

0x00000008

◆ RI_CMR5_PG_4

#define RI_CMR5_PG_4   (0x0010U << RI_CMR5_PG_Pos)

0x00000010

◆ RI_CMR5_PG_5

#define RI_CMR5_PG_5   (0x0020U << RI_CMR5_PG_Pos)

0x00000020

◆ RI_CMR5_PG_6

#define RI_CMR5_PG_6   (0x0040U << RI_CMR5_PG_Pos)

0x00000040

◆ RI_CMR5_PG_7

#define RI_CMR5_PG_7   (0x0080U << RI_CMR5_PG_Pos)

0x00000080

◆ RI_CMR5_PG_8

#define RI_CMR5_PG_8   (0x0100U << RI_CMR5_PG_Pos)

0x00000100

◆ RI_CMR5_PG_9

#define RI_CMR5_PG_9   (0x0200U << RI_CMR5_PG_Pos)

0x00000200

◆ RI_CMR5_PG_Msk

#define RI_CMR5_PG_Msk   (0xFFFFU << RI_CMR5_PG_Pos)

0x0000FFFF

◆ RI_CMR5_PG_Pos

#define RI_CMR5_PG_Pos   (0U)

◆ RI_HYSCR1_PA

#define RI_HYSCR1_PA   RI_HYSCR1_PA_Msk

PA[15:0] Port A Hysteresis selection

◆ RI_HYSCR1_PA_0

#define RI_HYSCR1_PA_0   (0x0001U << RI_HYSCR1_PA_Pos)

0x00000001

◆ RI_HYSCR1_PA_1

#define RI_HYSCR1_PA_1   (0x0002U << RI_HYSCR1_PA_Pos)

0x00000002

◆ RI_HYSCR1_PA_10

#define RI_HYSCR1_PA_10   (0x0400U << RI_HYSCR1_PA_Pos)

0x00000400

◆ RI_HYSCR1_PA_11

#define RI_HYSCR1_PA_11   (0x0800U << RI_HYSCR1_PA_Pos)

0x00000800

◆ RI_HYSCR1_PA_12

#define RI_HYSCR1_PA_12   (0x1000U << RI_HYSCR1_PA_Pos)

0x00001000

◆ RI_HYSCR1_PA_13

#define RI_HYSCR1_PA_13   (0x2000U << RI_HYSCR1_PA_Pos)

0x00002000

◆ RI_HYSCR1_PA_14

#define RI_HYSCR1_PA_14   (0x4000U << RI_HYSCR1_PA_Pos)

0x00004000

◆ RI_HYSCR1_PA_15

#define RI_HYSCR1_PA_15   (0x8000U << RI_HYSCR1_PA_Pos)

0x00008000

◆ RI_HYSCR1_PA_2

#define RI_HYSCR1_PA_2   (0x0004U << RI_HYSCR1_PA_Pos)

0x00000004

◆ RI_HYSCR1_PA_3

#define RI_HYSCR1_PA_3   (0x0008U << RI_HYSCR1_PA_Pos)

0x00000008

◆ RI_HYSCR1_PA_4

#define RI_HYSCR1_PA_4   (0x0010U << RI_HYSCR1_PA_Pos)

0x00000010

◆ RI_HYSCR1_PA_5

#define RI_HYSCR1_PA_5   (0x0020U << RI_HYSCR1_PA_Pos)

0x00000020

◆ RI_HYSCR1_PA_6

#define RI_HYSCR1_PA_6   (0x0040U << RI_HYSCR1_PA_Pos)

0x00000040

◆ RI_HYSCR1_PA_7

#define RI_HYSCR1_PA_7   (0x0080U << RI_HYSCR1_PA_Pos)

0x00000080

◆ RI_HYSCR1_PA_8

#define RI_HYSCR1_PA_8   (0x0100U << RI_HYSCR1_PA_Pos)

0x00000100

◆ RI_HYSCR1_PA_9

#define RI_HYSCR1_PA_9   (0x0200U << RI_HYSCR1_PA_Pos)

0x00000200

◆ RI_HYSCR1_PA_Msk

#define RI_HYSCR1_PA_Msk   (0xFFFFU << RI_HYSCR1_PA_Pos)

0x0000FFFF

◆ RI_HYSCR1_PA_Pos

#define RI_HYSCR1_PA_Pos   (0U)

◆ RI_HYSCR1_PB

#define RI_HYSCR1_PB   RI_HYSCR1_PB_Msk

PB[15:0] Port B Hysteresis selection

◆ RI_HYSCR1_PB_0

#define RI_HYSCR1_PB_0   (0x0001U << RI_HYSCR1_PB_Pos)

0x00010000

◆ RI_HYSCR1_PB_1

#define RI_HYSCR1_PB_1   (0x0002U << RI_HYSCR1_PB_Pos)

0x00020000

◆ RI_HYSCR1_PB_10

#define RI_HYSCR1_PB_10   (0x0400U << RI_HYSCR1_PB_Pos)

0x04000000

◆ RI_HYSCR1_PB_11

#define RI_HYSCR1_PB_11   (0x0800U << RI_HYSCR1_PB_Pos)

0x08000000

◆ RI_HYSCR1_PB_12

#define RI_HYSCR1_PB_12   (0x1000U << RI_HYSCR1_PB_Pos)

0x10000000

◆ RI_HYSCR1_PB_13

#define RI_HYSCR1_PB_13   (0x2000U << RI_HYSCR1_PB_Pos)

0x20000000

◆ RI_HYSCR1_PB_14

#define RI_HYSCR1_PB_14   (0x4000U << RI_HYSCR1_PB_Pos)

0x40000000

◆ RI_HYSCR1_PB_15

#define RI_HYSCR1_PB_15   (0x8000U << RI_HYSCR1_PB_Pos)

0x80000000

◆ RI_HYSCR1_PB_2

#define RI_HYSCR1_PB_2   (0x0004U << RI_HYSCR1_PB_Pos)

0x00040000

◆ RI_HYSCR1_PB_3

#define RI_HYSCR1_PB_3   (0x0008U << RI_HYSCR1_PB_Pos)

0x00080000

◆ RI_HYSCR1_PB_4

#define RI_HYSCR1_PB_4   (0x0010U << RI_HYSCR1_PB_Pos)

0x00100000

◆ RI_HYSCR1_PB_5

#define RI_HYSCR1_PB_5   (0x0020U << RI_HYSCR1_PB_Pos)

0x00200000

◆ RI_HYSCR1_PB_6

#define RI_HYSCR1_PB_6   (0x0040U << RI_HYSCR1_PB_Pos)

0x00400000

◆ RI_HYSCR1_PB_7

#define RI_HYSCR1_PB_7   (0x0080U << RI_HYSCR1_PB_Pos)

0x00800000

◆ RI_HYSCR1_PB_8

#define RI_HYSCR1_PB_8   (0x0100U << RI_HYSCR1_PB_Pos)

0x01000000

◆ RI_HYSCR1_PB_9

#define RI_HYSCR1_PB_9   (0x0200U << RI_HYSCR1_PB_Pos)

0x02000000

◆ RI_HYSCR1_PB_Msk

#define RI_HYSCR1_PB_Msk   (0xFFFFU << RI_HYSCR1_PB_Pos)

0xFFFF0000

◆ RI_HYSCR1_PB_Pos

#define RI_HYSCR1_PB_Pos   (16U)

◆ RI_HYSCR2_PC

#define RI_HYSCR2_PC   RI_HYSCR2_PC_Msk

PC[15:0] Port C Hysteresis selection

◆ RI_HYSCR2_PC_0

#define RI_HYSCR2_PC_0   (0x0001U << RI_HYSCR2_PC_Pos)

0x00000001

◆ RI_HYSCR2_PC_1

#define RI_HYSCR2_PC_1   (0x0002U << RI_HYSCR2_PC_Pos)

0x00000002

◆ RI_HYSCR2_PC_10

#define RI_HYSCR2_PC_10   (0x0400U << RI_HYSCR2_PC_Pos)

0x00000400

◆ RI_HYSCR2_PC_11

#define RI_HYSCR2_PC_11   (0x0800U << RI_HYSCR2_PC_Pos)

0x00000800

◆ RI_HYSCR2_PC_12

#define RI_HYSCR2_PC_12   (0x1000U << RI_HYSCR2_PC_Pos)

0x00001000

◆ RI_HYSCR2_PC_13

#define RI_HYSCR2_PC_13   (0x2000U << RI_HYSCR2_PC_Pos)

0x00002000

◆ RI_HYSCR2_PC_14

#define RI_HYSCR2_PC_14   (0x4000U << RI_HYSCR2_PC_Pos)

0x00004000

◆ RI_HYSCR2_PC_15

#define RI_HYSCR2_PC_15   (0x8000U << RI_HYSCR2_PC_Pos)

0x00008000

◆ RI_HYSCR2_PC_2

#define RI_HYSCR2_PC_2   (0x0004U << RI_HYSCR2_PC_Pos)

0x00000004

◆ RI_HYSCR2_PC_3

#define RI_HYSCR2_PC_3   (0x0008U << RI_HYSCR2_PC_Pos)

0x00000008

◆ RI_HYSCR2_PC_4

#define RI_HYSCR2_PC_4   (0x0010U << RI_HYSCR2_PC_Pos)

0x00000010

◆ RI_HYSCR2_PC_5

#define RI_HYSCR2_PC_5   (0x0020U << RI_HYSCR2_PC_Pos)

0x00000020

◆ RI_HYSCR2_PC_6

#define RI_HYSCR2_PC_6   (0x0040U << RI_HYSCR2_PC_Pos)

0x00000040

◆ RI_HYSCR2_PC_7

#define RI_HYSCR2_PC_7   (0x0080U << RI_HYSCR2_PC_Pos)

0x00000080

◆ RI_HYSCR2_PC_8

#define RI_HYSCR2_PC_8   (0x0100U << RI_HYSCR2_PC_Pos)

0x00000100

◆ RI_HYSCR2_PC_9

#define RI_HYSCR2_PC_9   (0x0200U << RI_HYSCR2_PC_Pos)

0x00000200

◆ RI_HYSCR2_PC_Msk

#define RI_HYSCR2_PC_Msk   (0xFFFFU << RI_HYSCR2_PC_Pos)

0x0000FFFF

◆ RI_HYSCR2_PC_Pos

#define RI_HYSCR2_PC_Pos   (0U)

◆ RI_HYSCR2_PD

#define RI_HYSCR2_PD   RI_HYSCR2_PD_Msk

PD[15:0] Port D Hysteresis selection

◆ RI_HYSCR2_PD_0

#define RI_HYSCR2_PD_0   (0x0001U << RI_HYSCR2_PD_Pos)

0x00010000

◆ RI_HYSCR2_PD_1

#define RI_HYSCR2_PD_1   (0x0002U << RI_HYSCR2_PD_Pos)

0x00020000

◆ RI_HYSCR2_PD_10

#define RI_HYSCR2_PD_10   (0x0400U << RI_HYSCR2_PD_Pos)

0x04000000

◆ RI_HYSCR2_PD_11

#define RI_HYSCR2_PD_11   (0x0800U << RI_HYSCR2_PD_Pos)

0x08000000

◆ RI_HYSCR2_PD_12

#define RI_HYSCR2_PD_12   (0x1000U << RI_HYSCR2_PD_Pos)

0x10000000

◆ RI_HYSCR2_PD_13

#define RI_HYSCR2_PD_13   (0x2000U << RI_HYSCR2_PD_Pos)

0x20000000

◆ RI_HYSCR2_PD_14

#define RI_HYSCR2_PD_14   (0x4000U << RI_HYSCR2_PD_Pos)

0x40000000

◆ RI_HYSCR2_PD_15

#define RI_HYSCR2_PD_15   (0x8000U << RI_HYSCR2_PD_Pos)

0x80000000

◆ RI_HYSCR2_PD_2

#define RI_HYSCR2_PD_2   (0x0004U << RI_HYSCR2_PD_Pos)

0x00040000

◆ RI_HYSCR2_PD_3

#define RI_HYSCR2_PD_3   (0x0008U << RI_HYSCR2_PD_Pos)

0x00080000

◆ RI_HYSCR2_PD_4

#define RI_HYSCR2_PD_4   (0x0010U << RI_HYSCR2_PD_Pos)

0x00100000

◆ RI_HYSCR2_PD_5

#define RI_HYSCR2_PD_5   (0x0020U << RI_HYSCR2_PD_Pos)

0x00200000

◆ RI_HYSCR2_PD_6

#define RI_HYSCR2_PD_6   (0x0040U << RI_HYSCR2_PD_Pos)

0x00400000

◆ RI_HYSCR2_PD_7

#define RI_HYSCR2_PD_7   (0x0080U << RI_HYSCR2_PD_Pos)

0x00800000

◆ RI_HYSCR2_PD_8

#define RI_HYSCR2_PD_8   (0x0100U << RI_HYSCR2_PD_Pos)

0x01000000

◆ RI_HYSCR2_PD_9

#define RI_HYSCR2_PD_9   (0x0200U << RI_HYSCR2_PD_Pos)

0x02000000

◆ RI_HYSCR2_PD_Msk

#define RI_HYSCR2_PD_Msk   (0xFFFFU << RI_HYSCR2_PD_Pos)

0xFFFF0000

◆ RI_HYSCR2_PD_Pos

#define RI_HYSCR2_PD_Pos   (16U)

◆ RI_HYSCR3_PE

#define RI_HYSCR3_PE   RI_HYSCR3_PE_Msk

PE[15:0] Port E Hysteresis selection

◆ RI_HYSCR3_PE_0

#define RI_HYSCR3_PE_0   (0x0001U << RI_HYSCR3_PE_Pos)

0x00000001

◆ RI_HYSCR3_PE_1

#define RI_HYSCR3_PE_1   (0x0002U << RI_HYSCR3_PE_Pos)

0x00000002

◆ RI_HYSCR3_PE_10

#define RI_HYSCR3_PE_10   (0x0400U << RI_HYSCR3_PE_Pos)

0x00000400

◆ RI_HYSCR3_PE_11

#define RI_HYSCR3_PE_11   (0x0800U << RI_HYSCR3_PE_Pos)

0x00000800

◆ RI_HYSCR3_PE_12

#define RI_HYSCR3_PE_12   (0x1000U << RI_HYSCR3_PE_Pos)

0x00001000

◆ RI_HYSCR3_PE_13

#define RI_HYSCR3_PE_13   (0x2000U << RI_HYSCR3_PE_Pos)

0x00002000

◆ RI_HYSCR3_PE_14

#define RI_HYSCR3_PE_14   (0x4000U << RI_HYSCR3_PE_Pos)

0x00004000

◆ RI_HYSCR3_PE_15

#define RI_HYSCR3_PE_15   (0x8000U << RI_HYSCR3_PE_Pos)

0x00008000

◆ RI_HYSCR3_PE_2

#define RI_HYSCR3_PE_2   (0x0004U << RI_HYSCR3_PE_Pos)

0x00000004

◆ RI_HYSCR3_PE_3

#define RI_HYSCR3_PE_3   (0x0008U << RI_HYSCR3_PE_Pos)

0x00000008

◆ RI_HYSCR3_PE_4

#define RI_HYSCR3_PE_4   (0x0010U << RI_HYSCR3_PE_Pos)

0x00000010

◆ RI_HYSCR3_PE_5

#define RI_HYSCR3_PE_5   (0x0020U << RI_HYSCR3_PE_Pos)

0x00000020

◆ RI_HYSCR3_PE_6

#define RI_HYSCR3_PE_6   (0x0040U << RI_HYSCR3_PE_Pos)

0x00000040

◆ RI_HYSCR3_PE_7

#define RI_HYSCR3_PE_7   (0x0080U << RI_HYSCR3_PE_Pos)

0x00000080

◆ RI_HYSCR3_PE_8

#define RI_HYSCR3_PE_8   (0x0100U << RI_HYSCR3_PE_Pos)

0x00000100

◆ RI_HYSCR3_PE_9

#define RI_HYSCR3_PE_9   (0x0200U << RI_HYSCR3_PE_Pos)

0x00000200

◆ RI_HYSCR3_PE_Msk

#define RI_HYSCR3_PE_Msk   (0xFFFFU << RI_HYSCR3_PE_Pos)

0x0000FFFF

◆ RI_HYSCR3_PE_Pos

#define RI_HYSCR3_PE_Pos   (0U)

◆ RI_HYSCR3_PF

#define RI_HYSCR3_PF   RI_HYSCR3_PF_Msk

PF[15:0] Port F Hysteresis selection

◆ RI_HYSCR3_PF_0

#define RI_HYSCR3_PF_0   (0x0001U << RI_HYSCR3_PF_Pos)

0x00010000

◆ RI_HYSCR3_PF_1

#define RI_HYSCR3_PF_1   (0x0002U << RI_HYSCR3_PF_Pos)

0x00020000

◆ RI_HYSCR3_PF_10

#define RI_HYSCR3_PF_10   (0x0400U << RI_HYSCR3_PF_Pos)

0x04000000

◆ RI_HYSCR3_PF_11

#define RI_HYSCR3_PF_11   (0x0800U << RI_HYSCR3_PF_Pos)

0x08000000

◆ RI_HYSCR3_PF_12

#define RI_HYSCR3_PF_12   (0x1000U << RI_HYSCR3_PF_Pos)

0x10000000

◆ RI_HYSCR3_PF_13

#define RI_HYSCR3_PF_13   (0x2000U << RI_HYSCR3_PF_Pos)

0x20000000

◆ RI_HYSCR3_PF_14

#define RI_HYSCR3_PF_14   (0x4000U << RI_HYSCR3_PF_Pos)

0x40000000

◆ RI_HYSCR3_PF_15

#define RI_HYSCR3_PF_15   (0x8000U << RI_HYSCR3_PF_Pos)

0x80000000

◆ RI_HYSCR3_PF_2

#define RI_HYSCR3_PF_2   (0x0004U << RI_HYSCR3_PF_Pos)

0x00040000

◆ RI_HYSCR3_PF_3

#define RI_HYSCR3_PF_3   (0x0008U << RI_HYSCR3_PF_Pos)

0x00080000

◆ RI_HYSCR3_PF_4

#define RI_HYSCR3_PF_4   (0x0010U << RI_HYSCR3_PF_Pos)

0x00100000

◆ RI_HYSCR3_PF_5

#define RI_HYSCR3_PF_5   (0x0020U << RI_HYSCR3_PF_Pos)

0x00200000

◆ RI_HYSCR3_PF_6

#define RI_HYSCR3_PF_6   (0x0040U << RI_HYSCR3_PF_Pos)

0x00400000

◆ RI_HYSCR3_PF_7

#define RI_HYSCR3_PF_7   (0x0080U << RI_HYSCR3_PF_Pos)

0x00800000

◆ RI_HYSCR3_PF_8

#define RI_HYSCR3_PF_8   (0x0100U << RI_HYSCR3_PF_Pos)

0x01000000

◆ RI_HYSCR3_PF_9

#define RI_HYSCR3_PF_9   (0x0200U << RI_HYSCR3_PF_Pos)

0x02000000

◆ RI_HYSCR3_PF_Msk

#define RI_HYSCR3_PF_Msk   (0xFFFFU << RI_HYSCR3_PF_Pos)

0xFFFF0000

◆ RI_HYSCR3_PF_Pos

#define RI_HYSCR3_PF_Pos   (16U)

◆ RI_HYSCR4_PG

#define RI_HYSCR4_PG   RI_HYSCR4_PG_Msk

PG[15:0] Port G Hysteresis selection

◆ RI_HYSCR4_PG_0

#define RI_HYSCR4_PG_0   (0x0001U << RI_HYSCR4_PG_Pos)

0x00000001

◆ RI_HYSCR4_PG_1

#define RI_HYSCR4_PG_1   (0x0002U << RI_HYSCR4_PG_Pos)

0x00000002

◆ RI_HYSCR4_PG_10

#define RI_HYSCR4_PG_10   (0x0400U << RI_HYSCR4_PG_Pos)

0x00000400

◆ RI_HYSCR4_PG_11

#define RI_HYSCR4_PG_11   (0x0800U << RI_HYSCR4_PG_Pos)

0x00000800

◆ RI_HYSCR4_PG_12

#define RI_HYSCR4_PG_12   (0x1000U << RI_HYSCR4_PG_Pos)

0x00001000

◆ RI_HYSCR4_PG_13

#define RI_HYSCR4_PG_13   (0x2000U << RI_HYSCR4_PG_Pos)

0x00002000

◆ RI_HYSCR4_PG_14

#define RI_HYSCR4_PG_14   (0x4000U << RI_HYSCR4_PG_Pos)

0x00004000

◆ RI_HYSCR4_PG_15

#define RI_HYSCR4_PG_15   (0x8000U << RI_HYSCR4_PG_Pos)

0x00008000

◆ RI_HYSCR4_PG_2

#define RI_HYSCR4_PG_2   (0x0004U << RI_HYSCR4_PG_Pos)

0x00000004

◆ RI_HYSCR4_PG_3

#define RI_HYSCR4_PG_3   (0x0008U << RI_HYSCR4_PG_Pos)

0x00000008

◆ RI_HYSCR4_PG_4

#define RI_HYSCR4_PG_4   (0x0010U << RI_HYSCR4_PG_Pos)

0x00000010

◆ RI_HYSCR4_PG_5

#define RI_HYSCR4_PG_5   (0x0020U << RI_HYSCR4_PG_Pos)

0x00000020

◆ RI_HYSCR4_PG_6

#define RI_HYSCR4_PG_6   (0x0040U << RI_HYSCR4_PG_Pos)

0x00000040

◆ RI_HYSCR4_PG_7

#define RI_HYSCR4_PG_7   (0x0080U << RI_HYSCR4_PG_Pos)

0x00000080

◆ RI_HYSCR4_PG_8

#define RI_HYSCR4_PG_8   (0x0100U << RI_HYSCR4_PG_Pos)

0x00000100

◆ RI_HYSCR4_PG_9

#define RI_HYSCR4_PG_9   (0x0200U << RI_HYSCR4_PG_Pos)

0x00000200

◆ RI_HYSCR4_PG_Msk

#define RI_HYSCR4_PG_Msk   (0xFFFFU << RI_HYSCR4_PG_Pos)

0x0000FFFF

◆ RI_HYSCR4_PG_Pos

#define RI_HYSCR4_PG_Pos   (0U)

◆ RI_ICR_IC1

#define RI_ICR_IC1   RI_ICR_IC1_Msk

Input capture 1

◆ RI_ICR_IC1_Msk

#define RI_ICR_IC1_Msk   (0x1U << RI_ICR_IC1_Pos)

0x00040000

◆ RI_ICR_IC1_Pos

#define RI_ICR_IC1_Pos   (18U)

◆ RI_ICR_IC1OS

#define RI_ICR_IC1OS   RI_ICR_IC1OS_Msk

IC1OS[3:0] bits (Input Capture 1 select bits)

◆ RI_ICR_IC1OS_0

#define RI_ICR_IC1OS_0   (0x1U << RI_ICR_IC1OS_Pos)

0x00000001

◆ RI_ICR_IC1OS_1

#define RI_ICR_IC1OS_1   (0x2U << RI_ICR_IC1OS_Pos)

0x00000002

◆ RI_ICR_IC1OS_2

#define RI_ICR_IC1OS_2   (0x4U << RI_ICR_IC1OS_Pos)

0x00000004

◆ RI_ICR_IC1OS_3

#define RI_ICR_IC1OS_3   (0x8U << RI_ICR_IC1OS_Pos)

0x00000008

◆ RI_ICR_IC1OS_Msk

#define RI_ICR_IC1OS_Msk   (0xFU << RI_ICR_IC1OS_Pos)

0x0000000F

◆ RI_ICR_IC1OS_Pos

#define RI_ICR_IC1OS_Pos   (0U)

◆ RI_ICR_IC2

#define RI_ICR_IC2   RI_ICR_IC2_Msk

Input capture 2

◆ RI_ICR_IC2_Msk

#define RI_ICR_IC2_Msk   (0x1U << RI_ICR_IC2_Pos)

0x00080000

◆ RI_ICR_IC2_Pos

#define RI_ICR_IC2_Pos   (19U)

◆ RI_ICR_IC2OS

#define RI_ICR_IC2OS   RI_ICR_IC2OS_Msk

IC2OS[3:0] bits (Input Capture 2 select bits)

◆ RI_ICR_IC2OS_0

#define RI_ICR_IC2OS_0   (0x1U << RI_ICR_IC2OS_Pos)

0x00000010

◆ RI_ICR_IC2OS_1

#define RI_ICR_IC2OS_1   (0x2U << RI_ICR_IC2OS_Pos)

0x00000020

◆ RI_ICR_IC2OS_2

#define RI_ICR_IC2OS_2   (0x4U << RI_ICR_IC2OS_Pos)

0x00000040

◆ RI_ICR_IC2OS_3

#define RI_ICR_IC2OS_3   (0x8U << RI_ICR_IC2OS_Pos)

0x00000080

◆ RI_ICR_IC2OS_Msk

#define RI_ICR_IC2OS_Msk   (0xFU << RI_ICR_IC2OS_Pos)

0x000000F0

◆ RI_ICR_IC2OS_Pos

#define RI_ICR_IC2OS_Pos   (4U)

◆ RI_ICR_IC3

#define RI_ICR_IC3   RI_ICR_IC3_Msk

Input capture 3

◆ RI_ICR_IC3_Msk

#define RI_ICR_IC3_Msk   (0x1U << RI_ICR_IC3_Pos)

0x00100000

◆ RI_ICR_IC3_Pos

#define RI_ICR_IC3_Pos   (20U)

◆ RI_ICR_IC3OS

#define RI_ICR_IC3OS   RI_ICR_IC3OS_Msk

IC3OS[3:0] bits (Input Capture 3 select bits)

◆ RI_ICR_IC3OS_0

#define RI_ICR_IC3OS_0   (0x1U << RI_ICR_IC3OS_Pos)

0x00000100

◆ RI_ICR_IC3OS_1

#define RI_ICR_IC3OS_1   (0x2U << RI_ICR_IC3OS_Pos)

0x00000200

◆ RI_ICR_IC3OS_2

#define RI_ICR_IC3OS_2   (0x4U << RI_ICR_IC3OS_Pos)

0x00000400

◆ RI_ICR_IC3OS_3

#define RI_ICR_IC3OS_3   (0x8U << RI_ICR_IC3OS_Pos)

0x00000800

◆ RI_ICR_IC3OS_Msk

#define RI_ICR_IC3OS_Msk   (0xFU << RI_ICR_IC3OS_Pos)

0x00000F00

◆ RI_ICR_IC3OS_Pos

#define RI_ICR_IC3OS_Pos   (8U)

◆ RI_ICR_IC4

#define RI_ICR_IC4   RI_ICR_IC4_Msk

Input capture 4

◆ RI_ICR_IC4_Msk

#define RI_ICR_IC4_Msk   (0x1U << RI_ICR_IC4_Pos)

0x00200000

◆ RI_ICR_IC4_Pos

#define RI_ICR_IC4_Pos   (21U)

◆ RI_ICR_IC4OS

#define RI_ICR_IC4OS   RI_ICR_IC4OS_Msk

IC4OS[3:0] bits (Input Capture 4 select bits)

◆ RI_ICR_IC4OS_0

#define RI_ICR_IC4OS_0   (0x1U << RI_ICR_IC4OS_Pos)

0x00001000

◆ RI_ICR_IC4OS_1

#define RI_ICR_IC4OS_1   (0x2U << RI_ICR_IC4OS_Pos)

0x00002000

◆ RI_ICR_IC4OS_2

#define RI_ICR_IC4OS_2   (0x4U << RI_ICR_IC4OS_Pos)

0x00004000

◆ RI_ICR_IC4OS_3

#define RI_ICR_IC4OS_3   (0x8U << RI_ICR_IC4OS_Pos)

0x00008000

◆ RI_ICR_IC4OS_Msk

#define RI_ICR_IC4OS_Msk   (0xFU << RI_ICR_IC4OS_Pos)

0x0000F000

◆ RI_ICR_IC4OS_Pos

#define RI_ICR_IC4OS_Pos   (12U)

◆ RI_ICR_TIM

#define RI_ICR_TIM   RI_ICR_TIM_Msk

TIM[3:0] bits (Timers select bits)

◆ RI_ICR_TIM_0

#define RI_ICR_TIM_0   (0x1U << RI_ICR_TIM_Pos)

0x00010000

◆ RI_ICR_TIM_1

#define RI_ICR_TIM_1   (0x2U << RI_ICR_TIM_Pos)

0x00020000

◆ RI_ICR_TIM_Msk

#define RI_ICR_TIM_Msk   (0x3U << RI_ICR_TIM_Pos)

0x00030000

◆ RI_ICR_TIM_Pos

#define RI_ICR_TIM_Pos   (16U)

◆ RTC_ALRMAR_DT

#define RTC_ALRMAR_DT   RTC_ALRMAR_DT_Msk

◆ RTC_ALRMAR_DT_0

#define RTC_ALRMAR_DT_0   (0x1U << RTC_ALRMAR_DT_Pos)

0x10000000

◆ RTC_ALRMAR_DT_1

#define RTC_ALRMAR_DT_1   (0x2U << RTC_ALRMAR_DT_Pos)

0x20000000

◆ RTC_ALRMAR_DT_Msk

#define RTC_ALRMAR_DT_Msk   (0x3U << RTC_ALRMAR_DT_Pos)

0x30000000

◆ RTC_ALRMAR_DT_Pos

#define RTC_ALRMAR_DT_Pos   (28U)

◆ RTC_ALRMAR_DU

#define RTC_ALRMAR_DU   RTC_ALRMAR_DU_Msk

◆ RTC_ALRMAR_DU_0

#define RTC_ALRMAR_DU_0   (0x1U << RTC_ALRMAR_DU_Pos)

0x01000000

◆ RTC_ALRMAR_DU_1

#define RTC_ALRMAR_DU_1   (0x2U << RTC_ALRMAR_DU_Pos)

0x02000000

◆ RTC_ALRMAR_DU_2

#define RTC_ALRMAR_DU_2   (0x4U << RTC_ALRMAR_DU_Pos)

0x04000000

◆ RTC_ALRMAR_DU_3

#define RTC_ALRMAR_DU_3   (0x8U << RTC_ALRMAR_DU_Pos)

0x08000000

◆ RTC_ALRMAR_DU_Msk

#define RTC_ALRMAR_DU_Msk   (0xFU << RTC_ALRMAR_DU_Pos)

0x0F000000

◆ RTC_ALRMAR_DU_Pos

#define RTC_ALRMAR_DU_Pos   (24U)

◆ RTC_ALRMAR_HT

#define RTC_ALRMAR_HT   RTC_ALRMAR_HT_Msk

◆ RTC_ALRMAR_HT_0

#define RTC_ALRMAR_HT_0   (0x1U << RTC_ALRMAR_HT_Pos)

0x00100000

◆ RTC_ALRMAR_HT_1

#define RTC_ALRMAR_HT_1   (0x2U << RTC_ALRMAR_HT_Pos)

0x00200000

◆ RTC_ALRMAR_HT_Msk

#define RTC_ALRMAR_HT_Msk   (0x3U << RTC_ALRMAR_HT_Pos)

0x00300000

◆ RTC_ALRMAR_HT_Pos

#define RTC_ALRMAR_HT_Pos   (20U)

◆ RTC_ALRMAR_HU

#define RTC_ALRMAR_HU   RTC_ALRMAR_HU_Msk

◆ RTC_ALRMAR_HU_0

#define RTC_ALRMAR_HU_0   (0x1U << RTC_ALRMAR_HU_Pos)

0x00010000

◆ RTC_ALRMAR_HU_1

#define RTC_ALRMAR_HU_1   (0x2U << RTC_ALRMAR_HU_Pos)

0x00020000

◆ RTC_ALRMAR_HU_2

#define RTC_ALRMAR_HU_2   (0x4U << RTC_ALRMAR_HU_Pos)

0x00040000

◆ RTC_ALRMAR_HU_3

#define RTC_ALRMAR_HU_3   (0x8U << RTC_ALRMAR_HU_Pos)

0x00080000

◆ RTC_ALRMAR_HU_Msk

#define RTC_ALRMAR_HU_Msk   (0xFU << RTC_ALRMAR_HU_Pos)

0x000F0000

◆ RTC_ALRMAR_HU_Pos

#define RTC_ALRMAR_HU_Pos   (16U)

◆ RTC_ALRMAR_MNT

#define RTC_ALRMAR_MNT   RTC_ALRMAR_MNT_Msk

◆ RTC_ALRMAR_MNT_0

#define RTC_ALRMAR_MNT_0   (0x1U << RTC_ALRMAR_MNT_Pos)

0x00001000

◆ RTC_ALRMAR_MNT_1

#define RTC_ALRMAR_MNT_1   (0x2U << RTC_ALRMAR_MNT_Pos)

0x00002000

◆ RTC_ALRMAR_MNT_2

#define RTC_ALRMAR_MNT_2   (0x4U << RTC_ALRMAR_MNT_Pos)

0x00004000

◆ RTC_ALRMAR_MNT_Msk

#define RTC_ALRMAR_MNT_Msk   (0x7U << RTC_ALRMAR_MNT_Pos)

0x00007000

◆ RTC_ALRMAR_MNT_Pos

#define RTC_ALRMAR_MNT_Pos   (12U)

◆ RTC_ALRMAR_MNU

#define RTC_ALRMAR_MNU   RTC_ALRMAR_MNU_Msk

◆ RTC_ALRMAR_MNU_0

#define RTC_ALRMAR_MNU_0   (0x1U << RTC_ALRMAR_MNU_Pos)

0x00000100

◆ RTC_ALRMAR_MNU_1

#define RTC_ALRMAR_MNU_1   (0x2U << RTC_ALRMAR_MNU_Pos)

0x00000200

◆ RTC_ALRMAR_MNU_2

#define RTC_ALRMAR_MNU_2   (0x4U << RTC_ALRMAR_MNU_Pos)

0x00000400

◆ RTC_ALRMAR_MNU_3

#define RTC_ALRMAR_MNU_3   (0x8U << RTC_ALRMAR_MNU_Pos)

0x00000800

◆ RTC_ALRMAR_MNU_Msk

#define RTC_ALRMAR_MNU_Msk   (0xFU << RTC_ALRMAR_MNU_Pos)

0x00000F00

◆ RTC_ALRMAR_MNU_Pos

#define RTC_ALRMAR_MNU_Pos   (8U)

◆ RTC_ALRMAR_MSK1

#define RTC_ALRMAR_MSK1   RTC_ALRMAR_MSK1_Msk

◆ RTC_ALRMAR_MSK1_Msk

#define RTC_ALRMAR_MSK1_Msk   (0x1U << RTC_ALRMAR_MSK1_Pos)

0x00000080

◆ RTC_ALRMAR_MSK1_Pos

#define RTC_ALRMAR_MSK1_Pos   (7U)

◆ RTC_ALRMAR_MSK2

#define RTC_ALRMAR_MSK2   RTC_ALRMAR_MSK2_Msk

◆ RTC_ALRMAR_MSK2_Msk

#define RTC_ALRMAR_MSK2_Msk   (0x1U << RTC_ALRMAR_MSK2_Pos)

0x00008000

◆ RTC_ALRMAR_MSK2_Pos

#define RTC_ALRMAR_MSK2_Pos   (15U)

◆ RTC_ALRMAR_MSK3

#define RTC_ALRMAR_MSK3   RTC_ALRMAR_MSK3_Msk

◆ RTC_ALRMAR_MSK3_Msk

#define RTC_ALRMAR_MSK3_Msk   (0x1U << RTC_ALRMAR_MSK3_Pos)

0x00800000

◆ RTC_ALRMAR_MSK3_Pos

#define RTC_ALRMAR_MSK3_Pos   (23U)

◆ RTC_ALRMAR_MSK4

#define RTC_ALRMAR_MSK4   RTC_ALRMAR_MSK4_Msk

◆ RTC_ALRMAR_MSK4_Msk

#define RTC_ALRMAR_MSK4_Msk   (0x1U << RTC_ALRMAR_MSK4_Pos)

0x80000000

◆ RTC_ALRMAR_MSK4_Pos

#define RTC_ALRMAR_MSK4_Pos   (31U)

◆ RTC_ALRMAR_PM

#define RTC_ALRMAR_PM   RTC_ALRMAR_PM_Msk

◆ RTC_ALRMAR_PM_Msk

#define RTC_ALRMAR_PM_Msk   (0x1U << RTC_ALRMAR_PM_Pos)

0x00400000

◆ RTC_ALRMAR_PM_Pos

#define RTC_ALRMAR_PM_Pos   (22U)

◆ RTC_ALRMAR_ST

#define RTC_ALRMAR_ST   RTC_ALRMAR_ST_Msk

◆ RTC_ALRMAR_ST_0

#define RTC_ALRMAR_ST_0   (0x1U << RTC_ALRMAR_ST_Pos)

0x00000010

◆ RTC_ALRMAR_ST_1

#define RTC_ALRMAR_ST_1   (0x2U << RTC_ALRMAR_ST_Pos)

0x00000020

◆ RTC_ALRMAR_ST_2

#define RTC_ALRMAR_ST_2   (0x4U << RTC_ALRMAR_ST_Pos)

0x00000040

◆ RTC_ALRMAR_ST_Msk

#define RTC_ALRMAR_ST_Msk   (0x7U << RTC_ALRMAR_ST_Pos)

0x00000070

◆ RTC_ALRMAR_ST_Pos

#define RTC_ALRMAR_ST_Pos   (4U)

◆ RTC_ALRMAR_SU

#define RTC_ALRMAR_SU   RTC_ALRMAR_SU_Msk

◆ RTC_ALRMAR_SU_0

#define RTC_ALRMAR_SU_0   (0x1U << RTC_ALRMAR_SU_Pos)

0x00000001

◆ RTC_ALRMAR_SU_1

#define RTC_ALRMAR_SU_1   (0x2U << RTC_ALRMAR_SU_Pos)

0x00000002

◆ RTC_ALRMAR_SU_2

#define RTC_ALRMAR_SU_2   (0x4U << RTC_ALRMAR_SU_Pos)

0x00000004

◆ RTC_ALRMAR_SU_3

#define RTC_ALRMAR_SU_3   (0x8U << RTC_ALRMAR_SU_Pos)

0x00000008

◆ RTC_ALRMAR_SU_Msk

#define RTC_ALRMAR_SU_Msk   (0xFU << RTC_ALRMAR_SU_Pos)

0x0000000F

◆ RTC_ALRMAR_SU_Pos

#define RTC_ALRMAR_SU_Pos   (0U)

◆ RTC_ALRMAR_WDSEL

#define RTC_ALRMAR_WDSEL   RTC_ALRMAR_WDSEL_Msk

◆ RTC_ALRMAR_WDSEL_Msk

#define RTC_ALRMAR_WDSEL_Msk   (0x1U << RTC_ALRMAR_WDSEL_Pos)

0x40000000

◆ RTC_ALRMAR_WDSEL_Pos

#define RTC_ALRMAR_WDSEL_Pos   (30U)

◆ RTC_ALRMASSR_MASKSS

#define RTC_ALRMASSR_MASKSS   RTC_ALRMASSR_MASKSS_Msk

◆ RTC_ALRMASSR_MASKSS_0

#define RTC_ALRMASSR_MASKSS_0   (0x1U << RTC_ALRMASSR_MASKSS_Pos)

0x01000000

◆ RTC_ALRMASSR_MASKSS_1

#define RTC_ALRMASSR_MASKSS_1   (0x2U << RTC_ALRMASSR_MASKSS_Pos)

0x02000000

◆ RTC_ALRMASSR_MASKSS_2

#define RTC_ALRMASSR_MASKSS_2   (0x4U << RTC_ALRMASSR_MASKSS_Pos)

0x04000000

◆ RTC_ALRMASSR_MASKSS_3

#define RTC_ALRMASSR_MASKSS_3   (0x8U << RTC_ALRMASSR_MASKSS_Pos)

0x08000000

◆ RTC_ALRMASSR_MASKSS_Msk

#define RTC_ALRMASSR_MASKSS_Msk   (0xFU << RTC_ALRMASSR_MASKSS_Pos)

0x0F000000

◆ RTC_ALRMASSR_MASKSS_Pos

#define RTC_ALRMASSR_MASKSS_Pos   (24U)

◆ RTC_ALRMASSR_SS

#define RTC_ALRMASSR_SS   RTC_ALRMASSR_SS_Msk

◆ RTC_ALRMASSR_SS_Msk

#define RTC_ALRMASSR_SS_Msk   (0x7FFFU << RTC_ALRMASSR_SS_Pos)

0x00007FFF

◆ RTC_ALRMASSR_SS_Pos

#define RTC_ALRMASSR_SS_Pos   (0U)

◆ RTC_ALRMBR_DT

#define RTC_ALRMBR_DT   RTC_ALRMBR_DT_Msk

◆ RTC_ALRMBR_DT_0

#define RTC_ALRMBR_DT_0   (0x1U << RTC_ALRMBR_DT_Pos)

0x10000000

◆ RTC_ALRMBR_DT_1

#define RTC_ALRMBR_DT_1   (0x2U << RTC_ALRMBR_DT_Pos)

0x20000000

◆ RTC_ALRMBR_DT_Msk

#define RTC_ALRMBR_DT_Msk   (0x3U << RTC_ALRMBR_DT_Pos)

0x30000000

◆ RTC_ALRMBR_DT_Pos

#define RTC_ALRMBR_DT_Pos   (28U)

◆ RTC_ALRMBR_DU

#define RTC_ALRMBR_DU   RTC_ALRMBR_DU_Msk

◆ RTC_ALRMBR_DU_0

#define RTC_ALRMBR_DU_0   (0x1U << RTC_ALRMBR_DU_Pos)

0x01000000

◆ RTC_ALRMBR_DU_1

#define RTC_ALRMBR_DU_1   (0x2U << RTC_ALRMBR_DU_Pos)

0x02000000

◆ RTC_ALRMBR_DU_2

#define RTC_ALRMBR_DU_2   (0x4U << RTC_ALRMBR_DU_Pos)

0x04000000

◆ RTC_ALRMBR_DU_3

#define RTC_ALRMBR_DU_3   (0x8U << RTC_ALRMBR_DU_Pos)

0x08000000

◆ RTC_ALRMBR_DU_Msk

#define RTC_ALRMBR_DU_Msk   (0xFU << RTC_ALRMBR_DU_Pos)

0x0F000000

◆ RTC_ALRMBR_DU_Pos

#define RTC_ALRMBR_DU_Pos   (24U)

◆ RTC_ALRMBR_HT

#define RTC_ALRMBR_HT   RTC_ALRMBR_HT_Msk

◆ RTC_ALRMBR_HT_0

#define RTC_ALRMBR_HT_0   (0x1U << RTC_ALRMBR_HT_Pos)

0x00100000

◆ RTC_ALRMBR_HT_1

#define RTC_ALRMBR_HT_1   (0x2U << RTC_ALRMBR_HT_Pos)

0x00200000

◆ RTC_ALRMBR_HT_Msk

#define RTC_ALRMBR_HT_Msk   (0x3U << RTC_ALRMBR_HT_Pos)

0x00300000

◆ RTC_ALRMBR_HT_Pos

#define RTC_ALRMBR_HT_Pos   (20U)

◆ RTC_ALRMBR_HU

#define RTC_ALRMBR_HU   RTC_ALRMBR_HU_Msk

◆ RTC_ALRMBR_HU_0

#define RTC_ALRMBR_HU_0   (0x1U << RTC_ALRMBR_HU_Pos)

0x00010000

◆ RTC_ALRMBR_HU_1

#define RTC_ALRMBR_HU_1   (0x2U << RTC_ALRMBR_HU_Pos)

0x00020000

◆ RTC_ALRMBR_HU_2

#define RTC_ALRMBR_HU_2   (0x4U << RTC_ALRMBR_HU_Pos)

0x00040000

◆ RTC_ALRMBR_HU_3

#define RTC_ALRMBR_HU_3   (0x8U << RTC_ALRMBR_HU_Pos)

0x00080000

◆ RTC_ALRMBR_HU_Msk

#define RTC_ALRMBR_HU_Msk   (0xFU << RTC_ALRMBR_HU_Pos)

0x000F0000

◆ RTC_ALRMBR_HU_Pos

#define RTC_ALRMBR_HU_Pos   (16U)

◆ RTC_ALRMBR_MNT

#define RTC_ALRMBR_MNT   RTC_ALRMBR_MNT_Msk

◆ RTC_ALRMBR_MNT_0

#define RTC_ALRMBR_MNT_0   (0x1U << RTC_ALRMBR_MNT_Pos)

0x00001000

◆ RTC_ALRMBR_MNT_1

#define RTC_ALRMBR_MNT_1   (0x2U << RTC_ALRMBR_MNT_Pos)

0x00002000

◆ RTC_ALRMBR_MNT_2

#define RTC_ALRMBR_MNT_2   (0x4U << RTC_ALRMBR_MNT_Pos)

0x00004000

◆ RTC_ALRMBR_MNT_Msk

#define RTC_ALRMBR_MNT_Msk   (0x7U << RTC_ALRMBR_MNT_Pos)

0x00007000

◆ RTC_ALRMBR_MNT_Pos

#define RTC_ALRMBR_MNT_Pos   (12U)

◆ RTC_ALRMBR_MNU

#define RTC_ALRMBR_MNU   RTC_ALRMBR_MNU_Msk

◆ RTC_ALRMBR_MNU_0

#define RTC_ALRMBR_MNU_0   (0x1U << RTC_ALRMBR_MNU_Pos)

0x00000100

◆ RTC_ALRMBR_MNU_1

#define RTC_ALRMBR_MNU_1   (0x2U << RTC_ALRMBR_MNU_Pos)

0x00000200

◆ RTC_ALRMBR_MNU_2

#define RTC_ALRMBR_MNU_2   (0x4U << RTC_ALRMBR_MNU_Pos)

0x00000400

◆ RTC_ALRMBR_MNU_3

#define RTC_ALRMBR_MNU_3   (0x8U << RTC_ALRMBR_MNU_Pos)

0x00000800

◆ RTC_ALRMBR_MNU_Msk

#define RTC_ALRMBR_MNU_Msk   (0xFU << RTC_ALRMBR_MNU_Pos)

0x00000F00

◆ RTC_ALRMBR_MNU_Pos

#define RTC_ALRMBR_MNU_Pos   (8U)

◆ RTC_ALRMBR_MSK1

#define RTC_ALRMBR_MSK1   RTC_ALRMBR_MSK1_Msk

◆ RTC_ALRMBR_MSK1_Msk

#define RTC_ALRMBR_MSK1_Msk   (0x1U << RTC_ALRMBR_MSK1_Pos)

0x00000080

◆ RTC_ALRMBR_MSK1_Pos

#define RTC_ALRMBR_MSK1_Pos   (7U)

◆ RTC_ALRMBR_MSK2

#define RTC_ALRMBR_MSK2   RTC_ALRMBR_MSK2_Msk

◆ RTC_ALRMBR_MSK2_Msk

#define RTC_ALRMBR_MSK2_Msk   (0x1U << RTC_ALRMBR_MSK2_Pos)

0x00008000

◆ RTC_ALRMBR_MSK2_Pos

#define RTC_ALRMBR_MSK2_Pos   (15U)

◆ RTC_ALRMBR_MSK3

#define RTC_ALRMBR_MSK3   RTC_ALRMBR_MSK3_Msk

◆ RTC_ALRMBR_MSK3_Msk

#define RTC_ALRMBR_MSK3_Msk   (0x1U << RTC_ALRMBR_MSK3_Pos)

0x00800000

◆ RTC_ALRMBR_MSK3_Pos

#define RTC_ALRMBR_MSK3_Pos   (23U)

◆ RTC_ALRMBR_MSK4

#define RTC_ALRMBR_MSK4   RTC_ALRMBR_MSK4_Msk

◆ RTC_ALRMBR_MSK4_Msk

#define RTC_ALRMBR_MSK4_Msk   (0x1U << RTC_ALRMBR_MSK4_Pos)

0x80000000

◆ RTC_ALRMBR_MSK4_Pos

#define RTC_ALRMBR_MSK4_Pos   (31U)

◆ RTC_ALRMBR_PM

#define RTC_ALRMBR_PM   RTC_ALRMBR_PM_Msk

◆ RTC_ALRMBR_PM_Msk

#define RTC_ALRMBR_PM_Msk   (0x1U << RTC_ALRMBR_PM_Pos)

0x00400000

◆ RTC_ALRMBR_PM_Pos

#define RTC_ALRMBR_PM_Pos   (22U)

◆ RTC_ALRMBR_ST

#define RTC_ALRMBR_ST   RTC_ALRMBR_ST_Msk

◆ RTC_ALRMBR_ST_0

#define RTC_ALRMBR_ST_0   (0x1U << RTC_ALRMBR_ST_Pos)

0x00000010

◆ RTC_ALRMBR_ST_1

#define RTC_ALRMBR_ST_1   (0x2U << RTC_ALRMBR_ST_Pos)

0x00000020

◆ RTC_ALRMBR_ST_2

#define RTC_ALRMBR_ST_2   (0x4U << RTC_ALRMBR_ST_Pos)

0x00000040

◆ RTC_ALRMBR_ST_Msk

#define RTC_ALRMBR_ST_Msk   (0x7U << RTC_ALRMBR_ST_Pos)

0x00000070

◆ RTC_ALRMBR_ST_Pos

#define RTC_ALRMBR_ST_Pos   (4U)

◆ RTC_ALRMBR_SU

#define RTC_ALRMBR_SU   RTC_ALRMBR_SU_Msk

◆ RTC_ALRMBR_SU_0

#define RTC_ALRMBR_SU_0   (0x1U << RTC_ALRMBR_SU_Pos)

0x00000001

◆ RTC_ALRMBR_SU_1

#define RTC_ALRMBR_SU_1   (0x2U << RTC_ALRMBR_SU_Pos)

0x00000002

◆ RTC_ALRMBR_SU_2

#define RTC_ALRMBR_SU_2   (0x4U << RTC_ALRMBR_SU_Pos)

0x00000004

◆ RTC_ALRMBR_SU_3

#define RTC_ALRMBR_SU_3   (0x8U << RTC_ALRMBR_SU_Pos)

0x00000008

◆ RTC_ALRMBR_SU_Msk

#define RTC_ALRMBR_SU_Msk   (0xFU << RTC_ALRMBR_SU_Pos)

0x0000000F

◆ RTC_ALRMBR_SU_Pos

#define RTC_ALRMBR_SU_Pos   (0U)

◆ RTC_ALRMBR_WDSEL

#define RTC_ALRMBR_WDSEL   RTC_ALRMBR_WDSEL_Msk

◆ RTC_ALRMBR_WDSEL_Msk

#define RTC_ALRMBR_WDSEL_Msk   (0x1U << RTC_ALRMBR_WDSEL_Pos)

0x40000000

◆ RTC_ALRMBR_WDSEL_Pos

#define RTC_ALRMBR_WDSEL_Pos   (30U)

◆ RTC_ALRMBSSR_MASKSS

#define RTC_ALRMBSSR_MASKSS   RTC_ALRMBSSR_MASKSS_Msk

◆ RTC_ALRMBSSR_MASKSS_0

#define RTC_ALRMBSSR_MASKSS_0   (0x1U << RTC_ALRMBSSR_MASKSS_Pos)

0x01000000

◆ RTC_ALRMBSSR_MASKSS_1

#define RTC_ALRMBSSR_MASKSS_1   (0x2U << RTC_ALRMBSSR_MASKSS_Pos)

0x02000000

◆ RTC_ALRMBSSR_MASKSS_2

#define RTC_ALRMBSSR_MASKSS_2   (0x4U << RTC_ALRMBSSR_MASKSS_Pos)

0x04000000

◆ RTC_ALRMBSSR_MASKSS_3

#define RTC_ALRMBSSR_MASKSS_3   (0x8U << RTC_ALRMBSSR_MASKSS_Pos)

0x08000000

◆ RTC_ALRMBSSR_MASKSS_Msk

#define RTC_ALRMBSSR_MASKSS_Msk   (0xFU << RTC_ALRMBSSR_MASKSS_Pos)

0x0F000000

◆ RTC_ALRMBSSR_MASKSS_Pos

#define RTC_ALRMBSSR_MASKSS_Pos   (24U)

◆ RTC_ALRMBSSR_SS

#define RTC_ALRMBSSR_SS   RTC_ALRMBSSR_SS_Msk

◆ RTC_ALRMBSSR_SS_Msk

#define RTC_ALRMBSSR_SS_Msk   (0x7FFFU << RTC_ALRMBSSR_SS_Pos)

0x00007FFF

◆ RTC_ALRMBSSR_SS_Pos

#define RTC_ALRMBSSR_SS_Pos   (0U)

◆ RTC_BACKUP_SUPPORT

#define RTC_BACKUP_SUPPORT

BACKUP register feature support

◆ RTC_BKP0R

#define RTC_BKP0R   RTC_BKP0R_Msk

◆ RTC_BKP0R_Msk

#define RTC_BKP0R_Msk   (0xFFFFFFFFU << RTC_BKP0R_Pos)

0xFFFFFFFF

◆ RTC_BKP0R_Pos

#define RTC_BKP0R_Pos   (0U)

◆ RTC_BKP10R

#define RTC_BKP10R   RTC_BKP10R_Msk

◆ RTC_BKP10R_Msk

#define RTC_BKP10R_Msk   (0xFFFFFFFFU << RTC_BKP10R_Pos)

0xFFFFFFFF

◆ RTC_BKP10R_Pos

#define RTC_BKP10R_Pos   (0U)

◆ RTC_BKP11R

#define RTC_BKP11R   RTC_BKP11R_Msk

◆ RTC_BKP11R_Msk

#define RTC_BKP11R_Msk   (0xFFFFFFFFU << RTC_BKP11R_Pos)

0xFFFFFFFF

◆ RTC_BKP11R_Pos

#define RTC_BKP11R_Pos   (0U)

◆ RTC_BKP12R

#define RTC_BKP12R   RTC_BKP12R_Msk

◆ RTC_BKP12R_Msk

#define RTC_BKP12R_Msk   (0xFFFFFFFFU << RTC_BKP12R_Pos)

0xFFFFFFFF

◆ RTC_BKP12R_Pos

#define RTC_BKP12R_Pos   (0U)

◆ RTC_BKP13R

#define RTC_BKP13R   RTC_BKP13R_Msk

◆ RTC_BKP13R_Msk

#define RTC_BKP13R_Msk   (0xFFFFFFFFU << RTC_BKP13R_Pos)

0xFFFFFFFF

◆ RTC_BKP13R_Pos

#define RTC_BKP13R_Pos   (0U)

◆ RTC_BKP14R

#define RTC_BKP14R   RTC_BKP14R_Msk

◆ RTC_BKP14R_Msk

#define RTC_BKP14R_Msk   (0xFFFFFFFFU << RTC_BKP14R_Pos)

0xFFFFFFFF

◆ RTC_BKP14R_Pos

#define RTC_BKP14R_Pos   (0U)

◆ RTC_BKP15R

#define RTC_BKP15R   RTC_BKP15R_Msk

◆ RTC_BKP15R_Msk

#define RTC_BKP15R_Msk   (0xFFFFFFFFU << RTC_BKP15R_Pos)

0xFFFFFFFF

◆ RTC_BKP15R_Pos

#define RTC_BKP15R_Pos   (0U)

◆ RTC_BKP16R

#define RTC_BKP16R   RTC_BKP16R_Msk

◆ RTC_BKP16R_Msk

#define RTC_BKP16R_Msk   (0xFFFFFFFFU << RTC_BKP16R_Pos)

0xFFFFFFFF

◆ RTC_BKP16R_Pos

#define RTC_BKP16R_Pos   (0U)

◆ RTC_BKP17R

#define RTC_BKP17R   RTC_BKP17R_Msk

◆ RTC_BKP17R_Msk

#define RTC_BKP17R_Msk   (0xFFFFFFFFU << RTC_BKP17R_Pos)

0xFFFFFFFF

◆ RTC_BKP17R_Pos

#define RTC_BKP17R_Pos   (0U)

◆ RTC_BKP18R

#define RTC_BKP18R   RTC_BKP18R_Msk

◆ RTC_BKP18R_Msk

#define RTC_BKP18R_Msk   (0xFFFFFFFFU << RTC_BKP18R_Pos)

0xFFFFFFFF

◆ RTC_BKP18R_Pos

#define RTC_BKP18R_Pos   (0U)

◆ RTC_BKP19R

#define RTC_BKP19R   RTC_BKP19R_Msk

◆ RTC_BKP19R_Msk

#define RTC_BKP19R_Msk   (0xFFFFFFFFU << RTC_BKP19R_Pos)

0xFFFFFFFF

◆ RTC_BKP19R_Pos

#define RTC_BKP19R_Pos   (0U)

◆ RTC_BKP1R

#define RTC_BKP1R   RTC_BKP1R_Msk

◆ RTC_BKP1R_Msk

#define RTC_BKP1R_Msk   (0xFFFFFFFFU << RTC_BKP1R_Pos)

0xFFFFFFFF

◆ RTC_BKP1R_Pos

#define RTC_BKP1R_Pos   (0U)

◆ RTC_BKP20R

#define RTC_BKP20R   RTC_BKP20R_Msk

◆ RTC_BKP20R_Msk

#define RTC_BKP20R_Msk   (0xFFFFFFFFU << RTC_BKP20R_Pos)

0xFFFFFFFF

◆ RTC_BKP20R_Pos

#define RTC_BKP20R_Pos   (0U)

◆ RTC_BKP21R

#define RTC_BKP21R   RTC_BKP21R_Msk

◆ RTC_BKP21R_Msk

#define RTC_BKP21R_Msk   (0xFFFFFFFFU << RTC_BKP21R_Pos)

0xFFFFFFFF

◆ RTC_BKP21R_Pos

#define RTC_BKP21R_Pos   (0U)

◆ RTC_BKP22R

#define RTC_BKP22R   RTC_BKP22R_Msk

◆ RTC_BKP22R_Msk

#define RTC_BKP22R_Msk   (0xFFFFFFFFU << RTC_BKP22R_Pos)

0xFFFFFFFF

◆ RTC_BKP22R_Pos

#define RTC_BKP22R_Pos   (0U)

◆ RTC_BKP23R

#define RTC_BKP23R   RTC_BKP23R_Msk

◆ RTC_BKP23R_Msk

#define RTC_BKP23R_Msk   (0xFFFFFFFFU << RTC_BKP23R_Pos)

0xFFFFFFFF

◆ RTC_BKP23R_Pos

#define RTC_BKP23R_Pos   (0U)

◆ RTC_BKP24R

#define RTC_BKP24R   RTC_BKP24R_Msk

◆ RTC_BKP24R_Msk

#define RTC_BKP24R_Msk   (0xFFFFFFFFU << RTC_BKP24R_Pos)

0xFFFFFFFF

◆ RTC_BKP24R_Pos

#define RTC_BKP24R_Pos   (0U)

◆ RTC_BKP25R

#define RTC_BKP25R   RTC_BKP25R_Msk

◆ RTC_BKP25R_Msk

#define RTC_BKP25R_Msk   (0xFFFFFFFFU << RTC_BKP25R_Pos)

0xFFFFFFFF

◆ RTC_BKP25R_Pos

#define RTC_BKP25R_Pos   (0U)

◆ RTC_BKP26R

#define RTC_BKP26R   RTC_BKP26R_Msk

◆ RTC_BKP26R_Msk

#define RTC_BKP26R_Msk   (0xFFFFFFFFU << RTC_BKP26R_Pos)

0xFFFFFFFF

◆ RTC_BKP26R_Pos

#define RTC_BKP26R_Pos   (0U)

◆ RTC_BKP27R

#define RTC_BKP27R   RTC_BKP27R_Msk

◆ RTC_BKP27R_Msk

#define RTC_BKP27R_Msk   (0xFFFFFFFFU << RTC_BKP27R_Pos)

0xFFFFFFFF

◆ RTC_BKP27R_Pos

#define RTC_BKP27R_Pos   (0U)

◆ RTC_BKP28R

#define RTC_BKP28R   RTC_BKP28R_Msk

◆ RTC_BKP28R_Msk

#define RTC_BKP28R_Msk   (0xFFFFFFFFU << RTC_BKP28R_Pos)

0xFFFFFFFF

◆ RTC_BKP28R_Pos

#define RTC_BKP28R_Pos   (0U)

◆ RTC_BKP29R

#define RTC_BKP29R   RTC_BKP29R_Msk

◆ RTC_BKP29R_Msk

#define RTC_BKP29R_Msk   (0xFFFFFFFFU << RTC_BKP29R_Pos)

0xFFFFFFFF

◆ RTC_BKP29R_Pos

#define RTC_BKP29R_Pos   (0U)

◆ RTC_BKP2R

#define RTC_BKP2R   RTC_BKP2R_Msk

◆ RTC_BKP2R_Msk

#define RTC_BKP2R_Msk   (0xFFFFFFFFU << RTC_BKP2R_Pos)

0xFFFFFFFF

◆ RTC_BKP2R_Pos

#define RTC_BKP2R_Pos   (0U)

◆ RTC_BKP30R

#define RTC_BKP30R   RTC_BKP30R_Msk

◆ RTC_BKP30R_Msk

#define RTC_BKP30R_Msk   (0xFFFFFFFFU << RTC_BKP30R_Pos)

0xFFFFFFFF

◆ RTC_BKP30R_Pos

#define RTC_BKP30R_Pos   (0U)

◆ RTC_BKP31R

#define RTC_BKP31R   RTC_BKP31R_Msk

◆ RTC_BKP31R_Msk

#define RTC_BKP31R_Msk   (0xFFFFFFFFU << RTC_BKP31R_Pos)

0xFFFFFFFF

◆ RTC_BKP31R_Pos

#define RTC_BKP31R_Pos   (0U)

◆ RTC_BKP3R

#define RTC_BKP3R   RTC_BKP3R_Msk

◆ RTC_BKP3R_Msk

#define RTC_BKP3R_Msk   (0xFFFFFFFFU << RTC_BKP3R_Pos)

0xFFFFFFFF

◆ RTC_BKP3R_Pos

#define RTC_BKP3R_Pos   (0U)

◆ RTC_BKP4R

#define RTC_BKP4R   RTC_BKP4R_Msk

◆ RTC_BKP4R_Msk

#define RTC_BKP4R_Msk   (0xFFFFFFFFU << RTC_BKP4R_Pos)

0xFFFFFFFF

◆ RTC_BKP4R_Pos

#define RTC_BKP4R_Pos   (0U)

◆ RTC_BKP5R

#define RTC_BKP5R   RTC_BKP5R_Msk

◆ RTC_BKP5R_Msk

#define RTC_BKP5R_Msk   (0xFFFFFFFFU << RTC_BKP5R_Pos)

0xFFFFFFFF

◆ RTC_BKP5R_Pos

#define RTC_BKP5R_Pos   (0U)

◆ RTC_BKP6R

#define RTC_BKP6R   RTC_BKP6R_Msk

◆ RTC_BKP6R_Msk

#define RTC_BKP6R_Msk   (0xFFFFFFFFU << RTC_BKP6R_Pos)

0xFFFFFFFF

◆ RTC_BKP6R_Pos

#define RTC_BKP6R_Pos   (0U)

◆ RTC_BKP7R

#define RTC_BKP7R   RTC_BKP7R_Msk

◆ RTC_BKP7R_Msk

#define RTC_BKP7R_Msk   (0xFFFFFFFFU << RTC_BKP7R_Pos)

0xFFFFFFFF

◆ RTC_BKP7R_Pos

#define RTC_BKP7R_Pos   (0U)

◆ RTC_BKP8R

#define RTC_BKP8R   RTC_BKP8R_Msk

◆ RTC_BKP8R_Msk

#define RTC_BKP8R_Msk   (0xFFFFFFFFU << RTC_BKP8R_Pos)

0xFFFFFFFF

◆ RTC_BKP8R_Pos

#define RTC_BKP8R_Pos   (0U)

◆ RTC_BKP9R

#define RTC_BKP9R   RTC_BKP9R_Msk

◆ RTC_BKP9R_Msk

#define RTC_BKP9R_Msk   (0xFFFFFFFFU << RTC_BKP9R_Pos)

0xFFFFFFFF

◆ RTC_BKP9R_Pos

#define RTC_BKP9R_Pos   (0U)

◆ RTC_BKP_NUMBER

#define RTC_BKP_NUMBER   32

◆ RTC_CALIBR_DC

#define RTC_CALIBR_DC   RTC_CALIBR_DC_Msk

◆ RTC_CALIBR_DC_Msk

#define RTC_CALIBR_DC_Msk   (0x1FU << RTC_CALIBR_DC_Pos)

0x0000001F

◆ RTC_CALIBR_DC_Pos

#define RTC_CALIBR_DC_Pos   (0U)

◆ RTC_CALIBR_DCS

#define RTC_CALIBR_DCS   RTC_CALIBR_DCS_Msk

◆ RTC_CALIBR_DCS_Msk

#define RTC_CALIBR_DCS_Msk   (0x1U << RTC_CALIBR_DCS_Pos)

0x00000080

◆ RTC_CALIBR_DCS_Pos

#define RTC_CALIBR_DCS_Pos   (7U)

◆ RTC_CALR_CALM

#define RTC_CALR_CALM   RTC_CALR_CALM_Msk

◆ RTC_CALR_CALM_0

#define RTC_CALR_CALM_0   (0x001U << RTC_CALR_CALM_Pos)

0x00000001

◆ RTC_CALR_CALM_1

#define RTC_CALR_CALM_1   (0x002U << RTC_CALR_CALM_Pos)

0x00000002

◆ RTC_CALR_CALM_2

#define RTC_CALR_CALM_2   (0x004U << RTC_CALR_CALM_Pos)

0x00000004

◆ RTC_CALR_CALM_3

#define RTC_CALR_CALM_3   (0x008U << RTC_CALR_CALM_Pos)

0x00000008

◆ RTC_CALR_CALM_4

#define RTC_CALR_CALM_4   (0x010U << RTC_CALR_CALM_Pos)

0x00000010

◆ RTC_CALR_CALM_5

#define RTC_CALR_CALM_5   (0x020U << RTC_CALR_CALM_Pos)

0x00000020

◆ RTC_CALR_CALM_6

#define RTC_CALR_CALM_6   (0x040U << RTC_CALR_CALM_Pos)

0x00000040

◆ RTC_CALR_CALM_7

#define RTC_CALR_CALM_7   (0x080U << RTC_CALR_CALM_Pos)

0x00000080

◆ RTC_CALR_CALM_8

#define RTC_CALR_CALM_8   (0x100U << RTC_CALR_CALM_Pos)

0x00000100

◆ RTC_CALR_CALM_Msk

#define RTC_CALR_CALM_Msk   (0x1FFU << RTC_CALR_CALM_Pos)

0x000001FF

◆ RTC_CALR_CALM_Pos

#define RTC_CALR_CALM_Pos   (0U)

◆ RTC_CALR_CALP

#define RTC_CALR_CALP   RTC_CALR_CALP_Msk

◆ RTC_CALR_CALP_Msk

#define RTC_CALR_CALP_Msk   (0x1U << RTC_CALR_CALP_Pos)

0x00008000

◆ RTC_CALR_CALP_Pos

#define RTC_CALR_CALP_Pos   (15U)

◆ RTC_CALR_CALW16

#define RTC_CALR_CALW16   RTC_CALR_CALW16_Msk

◆ RTC_CALR_CALW16_Msk

#define RTC_CALR_CALW16_Msk   (0x1U << RTC_CALR_CALW16_Pos)

0x00002000

◆ RTC_CALR_CALW16_Pos

#define RTC_CALR_CALW16_Pos   (13U)

◆ RTC_CALR_CALW8

#define RTC_CALR_CALW8   RTC_CALR_CALW8_Msk

◆ RTC_CALR_CALW8_Msk

#define RTC_CALR_CALW8_Msk   (0x1U << RTC_CALR_CALW8_Pos)

0x00004000

◆ RTC_CALR_CALW8_Pos

#define RTC_CALR_CALW8_Pos   (14U)

◆ RTC_CR_ADD1H

#define RTC_CR_ADD1H   RTC_CR_ADD1H_Msk

◆ RTC_CR_ADD1H_Msk

#define RTC_CR_ADD1H_Msk   (0x1U << RTC_CR_ADD1H_Pos)

0x00010000

◆ RTC_CR_ADD1H_Pos

#define RTC_CR_ADD1H_Pos   (16U)

◆ RTC_CR_ALRAE

#define RTC_CR_ALRAE   RTC_CR_ALRAE_Msk

◆ RTC_CR_ALRAE_Msk

#define RTC_CR_ALRAE_Msk   (0x1U << RTC_CR_ALRAE_Pos)

0x00000100

◆ RTC_CR_ALRAE_Pos

#define RTC_CR_ALRAE_Pos   (8U)

◆ RTC_CR_ALRAIE

#define RTC_CR_ALRAIE   RTC_CR_ALRAIE_Msk

◆ RTC_CR_ALRAIE_Msk

#define RTC_CR_ALRAIE_Msk   (0x1U << RTC_CR_ALRAIE_Pos)

0x00001000

◆ RTC_CR_ALRAIE_Pos

#define RTC_CR_ALRAIE_Pos   (12U)

◆ RTC_CR_ALRBE

#define RTC_CR_ALRBE   RTC_CR_ALRBE_Msk

◆ RTC_CR_ALRBE_Msk

#define RTC_CR_ALRBE_Msk   (0x1U << RTC_CR_ALRBE_Pos)

0x00000200

◆ RTC_CR_ALRBE_Pos

#define RTC_CR_ALRBE_Pos   (9U)

◆ RTC_CR_ALRBIE

#define RTC_CR_ALRBIE   RTC_CR_ALRBIE_Msk

◆ RTC_CR_ALRBIE_Msk

#define RTC_CR_ALRBIE_Msk   (0x1U << RTC_CR_ALRBIE_Pos)

0x00002000

◆ RTC_CR_ALRBIE_Pos

#define RTC_CR_ALRBIE_Pos   (13U)

◆ RTC_CR_BCK

#define RTC_CR_BCK   RTC_CR_BKP

◆ RTC_CR_BCK_Msk

#define RTC_CR_BCK_Msk   RTC_CR_BKP_Msk

◆ RTC_CR_BCK_Pos

#define RTC_CR_BCK_Pos   RTC_CR_BKP_Pos

◆ RTC_CR_BKP

#define RTC_CR_BKP   RTC_CR_BKP_Msk

◆ RTC_CR_BKP_Msk

#define RTC_CR_BKP_Msk   (0x1U << RTC_CR_BKP_Pos)

0x00040000

◆ RTC_CR_BKP_Pos

#define RTC_CR_BKP_Pos   (18U)

◆ RTC_CR_BYPSHAD

#define RTC_CR_BYPSHAD   RTC_CR_BYPSHAD_Msk

◆ RTC_CR_BYPSHAD_Msk

#define RTC_CR_BYPSHAD_Msk   (0x1U << RTC_CR_BYPSHAD_Pos)

0x00000020

◆ RTC_CR_BYPSHAD_Pos

#define RTC_CR_BYPSHAD_Pos   (5U)

◆ RTC_CR_COE

#define RTC_CR_COE   RTC_CR_COE_Msk

◆ RTC_CR_COE_Msk

#define RTC_CR_COE_Msk   (0x1U << RTC_CR_COE_Pos)

0x00800000

◆ RTC_CR_COE_Pos

#define RTC_CR_COE_Pos   (23U)

◆ RTC_CR_COSEL

#define RTC_CR_COSEL   RTC_CR_COSEL_Msk

◆ RTC_CR_COSEL_Msk

#define RTC_CR_COSEL_Msk   (0x1U << RTC_CR_COSEL_Pos)

0x00080000

◆ RTC_CR_COSEL_Pos

#define RTC_CR_COSEL_Pos   (19U)

◆ RTC_CR_DCE

#define RTC_CR_DCE   RTC_CR_DCE_Msk

◆ RTC_CR_DCE_Msk

#define RTC_CR_DCE_Msk   (0x1U << RTC_CR_DCE_Pos)

0x00000080

◆ RTC_CR_DCE_Pos

#define RTC_CR_DCE_Pos   (7U)

◆ RTC_CR_FMT

#define RTC_CR_FMT   RTC_CR_FMT_Msk

◆ RTC_CR_FMT_Msk

#define RTC_CR_FMT_Msk   (0x1U << RTC_CR_FMT_Pos)

0x00000040

◆ RTC_CR_FMT_Pos

#define RTC_CR_FMT_Pos   (6U)

◆ RTC_CR_OSEL

#define RTC_CR_OSEL   RTC_CR_OSEL_Msk

◆ RTC_CR_OSEL_0

#define RTC_CR_OSEL_0   (0x1U << RTC_CR_OSEL_Pos)

0x00200000

◆ RTC_CR_OSEL_1

#define RTC_CR_OSEL_1   (0x2U << RTC_CR_OSEL_Pos)

0x00400000

◆ RTC_CR_OSEL_Msk

#define RTC_CR_OSEL_Msk   (0x3U << RTC_CR_OSEL_Pos)

0x00600000

◆ RTC_CR_OSEL_Pos

#define RTC_CR_OSEL_Pos   (21U)

◆ RTC_CR_POL

#define RTC_CR_POL   RTC_CR_POL_Msk

◆ RTC_CR_POL_Msk

#define RTC_CR_POL_Msk   (0x1U << RTC_CR_POL_Pos)

0x00100000

◆ RTC_CR_POL_Pos

#define RTC_CR_POL_Pos   (20U)

◆ RTC_CR_REFCKON

#define RTC_CR_REFCKON   RTC_CR_REFCKON_Msk

◆ RTC_CR_REFCKON_Msk

#define RTC_CR_REFCKON_Msk   (0x1U << RTC_CR_REFCKON_Pos)

0x00000010

◆ RTC_CR_REFCKON_Pos

#define RTC_CR_REFCKON_Pos   (4U)

◆ RTC_CR_SUB1H

#define RTC_CR_SUB1H   RTC_CR_SUB1H_Msk

◆ RTC_CR_SUB1H_Msk

#define RTC_CR_SUB1H_Msk   (0x1U << RTC_CR_SUB1H_Pos)

0x00020000

◆ RTC_CR_SUB1H_Pos

#define RTC_CR_SUB1H_Pos   (17U)

◆ RTC_CR_TSE

#define RTC_CR_TSE   RTC_CR_TSE_Msk

◆ RTC_CR_TSE_Msk

#define RTC_CR_TSE_Msk   (0x1U << RTC_CR_TSE_Pos)

0x00000800

◆ RTC_CR_TSE_Pos

#define RTC_CR_TSE_Pos   (11U)

◆ RTC_CR_TSEDGE

#define RTC_CR_TSEDGE   RTC_CR_TSEDGE_Msk

◆ RTC_CR_TSEDGE_Msk

#define RTC_CR_TSEDGE_Msk   (0x1U << RTC_CR_TSEDGE_Pos)

0x00000008

◆ RTC_CR_TSEDGE_Pos

#define RTC_CR_TSEDGE_Pos   (3U)

◆ RTC_CR_TSIE

#define RTC_CR_TSIE   RTC_CR_TSIE_Msk

◆ RTC_CR_TSIE_Msk

#define RTC_CR_TSIE_Msk   (0x1U << RTC_CR_TSIE_Pos)

0x00008000

◆ RTC_CR_TSIE_Pos

#define RTC_CR_TSIE_Pos   (15U)

◆ RTC_CR_WUCKSEL

#define RTC_CR_WUCKSEL   RTC_CR_WUCKSEL_Msk

◆ RTC_CR_WUCKSEL_0

#define RTC_CR_WUCKSEL_0   (0x1U << RTC_CR_WUCKSEL_Pos)

0x00000001

◆ RTC_CR_WUCKSEL_1

#define RTC_CR_WUCKSEL_1   (0x2U << RTC_CR_WUCKSEL_Pos)

0x00000002

◆ RTC_CR_WUCKSEL_2

#define RTC_CR_WUCKSEL_2   (0x4U << RTC_CR_WUCKSEL_Pos)

0x00000004

◆ RTC_CR_WUCKSEL_Msk

#define RTC_CR_WUCKSEL_Msk   (0x7U << RTC_CR_WUCKSEL_Pos)

0x00000007

◆ RTC_CR_WUCKSEL_Pos

#define RTC_CR_WUCKSEL_Pos   (0U)

◆ RTC_CR_WUTE

#define RTC_CR_WUTE   RTC_CR_WUTE_Msk

◆ RTC_CR_WUTE_Msk

#define RTC_CR_WUTE_Msk   (0x1U << RTC_CR_WUTE_Pos)

0x00000400

◆ RTC_CR_WUTE_Pos

#define RTC_CR_WUTE_Pos   (10U)

◆ RTC_CR_WUTIE

#define RTC_CR_WUTIE   RTC_CR_WUTIE_Msk

◆ RTC_CR_WUTIE_Msk

#define RTC_CR_WUTIE_Msk   (0x1U << RTC_CR_WUTIE_Pos)

0x00004000

◆ RTC_CR_WUTIE_Pos

#define RTC_CR_WUTIE_Pos   (14U)

◆ RTC_DR_DT

#define RTC_DR_DT   RTC_DR_DT_Msk

◆ RTC_DR_DT_0

#define RTC_DR_DT_0   (0x1U << RTC_DR_DT_Pos)

0x00000010

◆ RTC_DR_DT_1

#define RTC_DR_DT_1   (0x2U << RTC_DR_DT_Pos)

0x00000020

◆ RTC_DR_DT_Msk

#define RTC_DR_DT_Msk   (0x3U << RTC_DR_DT_Pos)

0x00000030

◆ RTC_DR_DT_Pos

#define RTC_DR_DT_Pos   (4U)

◆ RTC_DR_DU

#define RTC_DR_DU   RTC_DR_DU_Msk

◆ RTC_DR_DU_0

#define RTC_DR_DU_0   (0x1U << RTC_DR_DU_Pos)

0x00000001

◆ RTC_DR_DU_1

#define RTC_DR_DU_1   (0x2U << RTC_DR_DU_Pos)

0x00000002

◆ RTC_DR_DU_2

#define RTC_DR_DU_2   (0x4U << RTC_DR_DU_Pos)

0x00000004

◆ RTC_DR_DU_3

#define RTC_DR_DU_3   (0x8U << RTC_DR_DU_Pos)

0x00000008

◆ RTC_DR_DU_Msk

#define RTC_DR_DU_Msk   (0xFU << RTC_DR_DU_Pos)

0x0000000F

◆ RTC_DR_DU_Pos

#define RTC_DR_DU_Pos   (0U)

◆ RTC_DR_MT

#define RTC_DR_MT   RTC_DR_MT_Msk

◆ RTC_DR_MT_Msk

#define RTC_DR_MT_Msk   (0x1U << RTC_DR_MT_Pos)

0x00001000

◆ RTC_DR_MT_Pos

#define RTC_DR_MT_Pos   (12U)

◆ RTC_DR_MU

#define RTC_DR_MU   RTC_DR_MU_Msk

◆ RTC_DR_MU_0

#define RTC_DR_MU_0   (0x1U << RTC_DR_MU_Pos)

0x00000100

◆ RTC_DR_MU_1

#define RTC_DR_MU_1   (0x2U << RTC_DR_MU_Pos)

0x00000200

◆ RTC_DR_MU_2

#define RTC_DR_MU_2   (0x4U << RTC_DR_MU_Pos)

0x00000400

◆ RTC_DR_MU_3

#define RTC_DR_MU_3   (0x8U << RTC_DR_MU_Pos)

0x00000800

◆ RTC_DR_MU_Msk

#define RTC_DR_MU_Msk   (0xFU << RTC_DR_MU_Pos)

0x00000F00

◆ RTC_DR_MU_Pos

#define RTC_DR_MU_Pos   (8U)

◆ RTC_DR_WDU

#define RTC_DR_WDU   RTC_DR_WDU_Msk

◆ RTC_DR_WDU_0

#define RTC_DR_WDU_0   (0x1U << RTC_DR_WDU_Pos)

0x00002000

◆ RTC_DR_WDU_1

#define RTC_DR_WDU_1   (0x2U << RTC_DR_WDU_Pos)

0x00004000

◆ RTC_DR_WDU_2

#define RTC_DR_WDU_2   (0x4U << RTC_DR_WDU_Pos)

0x00008000

◆ RTC_DR_WDU_Msk

#define RTC_DR_WDU_Msk   (0x7U << RTC_DR_WDU_Pos)

0x0000E000

◆ RTC_DR_WDU_Pos

#define RTC_DR_WDU_Pos   (13U)

◆ RTC_DR_YT

#define RTC_DR_YT   RTC_DR_YT_Msk

◆ RTC_DR_YT_0

#define RTC_DR_YT_0   (0x1U << RTC_DR_YT_Pos)

0x00100000

◆ RTC_DR_YT_1

#define RTC_DR_YT_1   (0x2U << RTC_DR_YT_Pos)

0x00200000

◆ RTC_DR_YT_2

#define RTC_DR_YT_2   (0x4U << RTC_DR_YT_Pos)

0x00400000

◆ RTC_DR_YT_3

#define RTC_DR_YT_3   (0x8U << RTC_DR_YT_Pos)

0x00800000

◆ RTC_DR_YT_Msk

#define RTC_DR_YT_Msk   (0xFU << RTC_DR_YT_Pos)

0x00F00000

◆ RTC_DR_YT_Pos

#define RTC_DR_YT_Pos   (20U)

◆ RTC_DR_YU

#define RTC_DR_YU   RTC_DR_YU_Msk

◆ RTC_DR_YU_0

#define RTC_DR_YU_0   (0x1U << RTC_DR_YU_Pos)

0x00010000

◆ RTC_DR_YU_1

#define RTC_DR_YU_1   (0x2U << RTC_DR_YU_Pos)

0x00020000

◆ RTC_DR_YU_2

#define RTC_DR_YU_2   (0x4U << RTC_DR_YU_Pos)

0x00040000

◆ RTC_DR_YU_3

#define RTC_DR_YU_3   (0x8U << RTC_DR_YU_Pos)

0x00080000

◆ RTC_DR_YU_Msk

#define RTC_DR_YU_Msk   (0xFU << RTC_DR_YU_Pos)

0x000F0000

◆ RTC_DR_YU_Pos

#define RTC_DR_YU_Pos   (16U)

◆ RTC_ISR_ALRAF

#define RTC_ISR_ALRAF   RTC_ISR_ALRAF_Msk

◆ RTC_ISR_ALRAF_Msk

#define RTC_ISR_ALRAF_Msk   (0x1U << RTC_ISR_ALRAF_Pos)

0x00000100

◆ RTC_ISR_ALRAF_Pos

#define RTC_ISR_ALRAF_Pos   (8U)

◆ RTC_ISR_ALRAWF

#define RTC_ISR_ALRAWF   RTC_ISR_ALRAWF_Msk

◆ RTC_ISR_ALRAWF_Msk

#define RTC_ISR_ALRAWF_Msk   (0x1U << RTC_ISR_ALRAWF_Pos)

0x00000001

◆ RTC_ISR_ALRAWF_Pos

#define RTC_ISR_ALRAWF_Pos   (0U)

◆ RTC_ISR_ALRBF

#define RTC_ISR_ALRBF   RTC_ISR_ALRBF_Msk

◆ RTC_ISR_ALRBF_Msk

#define RTC_ISR_ALRBF_Msk   (0x1U << RTC_ISR_ALRBF_Pos)

0x00000200

◆ RTC_ISR_ALRBF_Pos

#define RTC_ISR_ALRBF_Pos   (9U)

◆ RTC_ISR_ALRBWF

#define RTC_ISR_ALRBWF   RTC_ISR_ALRBWF_Msk

◆ RTC_ISR_ALRBWF_Msk

#define RTC_ISR_ALRBWF_Msk   (0x1U << RTC_ISR_ALRBWF_Pos)

0x00000002

◆ RTC_ISR_ALRBWF_Pos

#define RTC_ISR_ALRBWF_Pos   (1U)

◆ RTC_ISR_INIT

#define RTC_ISR_INIT   RTC_ISR_INIT_Msk

◆ RTC_ISR_INIT_Msk

#define RTC_ISR_INIT_Msk   (0x1U << RTC_ISR_INIT_Pos)

0x00000080

◆ RTC_ISR_INIT_Pos

#define RTC_ISR_INIT_Pos   (7U)

◆ RTC_ISR_INITF

#define RTC_ISR_INITF   RTC_ISR_INITF_Msk

◆ RTC_ISR_INITF_Msk

#define RTC_ISR_INITF_Msk   (0x1U << RTC_ISR_INITF_Pos)

0x00000040

◆ RTC_ISR_INITF_Pos

#define RTC_ISR_INITF_Pos   (6U)

◆ RTC_ISR_INITS

#define RTC_ISR_INITS   RTC_ISR_INITS_Msk

◆ RTC_ISR_INITS_Msk

#define RTC_ISR_INITS_Msk   (0x1U << RTC_ISR_INITS_Pos)

0x00000010

◆ RTC_ISR_INITS_Pos

#define RTC_ISR_INITS_Pos   (4U)

◆ RTC_ISR_RECALPF

#define RTC_ISR_RECALPF   RTC_ISR_RECALPF_Msk

◆ RTC_ISR_RECALPF_Msk

#define RTC_ISR_RECALPF_Msk   (0x1U << RTC_ISR_RECALPF_Pos)

0x00010000

◆ RTC_ISR_RECALPF_Pos

#define RTC_ISR_RECALPF_Pos   (16U)

◆ RTC_ISR_RSF

#define RTC_ISR_RSF   RTC_ISR_RSF_Msk

◆ RTC_ISR_RSF_Msk

#define RTC_ISR_RSF_Msk   (0x1U << RTC_ISR_RSF_Pos)

0x00000020

◆ RTC_ISR_RSF_Pos

#define RTC_ISR_RSF_Pos   (5U)

◆ RTC_ISR_SHPF

#define RTC_ISR_SHPF   RTC_ISR_SHPF_Msk

◆ RTC_ISR_SHPF_Msk

#define RTC_ISR_SHPF_Msk   (0x1U << RTC_ISR_SHPF_Pos)

0x00000008

◆ RTC_ISR_SHPF_Pos

#define RTC_ISR_SHPF_Pos   (3U)

◆ RTC_ISR_TAMP1F

#define RTC_ISR_TAMP1F   RTC_ISR_TAMP1F_Msk

◆ RTC_ISR_TAMP1F_Msk

#define RTC_ISR_TAMP1F_Msk   (0x1U << RTC_ISR_TAMP1F_Pos)

0x00002000

◆ RTC_ISR_TAMP1F_Pos

#define RTC_ISR_TAMP1F_Pos   (13U)

◆ RTC_ISR_TAMP2F

#define RTC_ISR_TAMP2F   RTC_ISR_TAMP2F_Msk

◆ RTC_ISR_TAMP2F_Msk

#define RTC_ISR_TAMP2F_Msk   (0x1U << RTC_ISR_TAMP2F_Pos)

0x00004000

◆ RTC_ISR_TAMP2F_Pos

#define RTC_ISR_TAMP2F_Pos   (14U)

◆ RTC_ISR_TAMP3F

#define RTC_ISR_TAMP3F   RTC_ISR_TAMP3F_Msk

◆ RTC_ISR_TAMP3F_Msk

#define RTC_ISR_TAMP3F_Msk   (0x1U << RTC_ISR_TAMP3F_Pos)

0x00008000

◆ RTC_ISR_TAMP3F_Pos

#define RTC_ISR_TAMP3F_Pos   (15U)

◆ RTC_ISR_TSF

#define RTC_ISR_TSF   RTC_ISR_TSF_Msk

◆ RTC_ISR_TSF_Msk

#define RTC_ISR_TSF_Msk   (0x1U << RTC_ISR_TSF_Pos)

0x00000800

◆ RTC_ISR_TSF_Pos

#define RTC_ISR_TSF_Pos   (11U)

◆ RTC_ISR_TSOVF

#define RTC_ISR_TSOVF   RTC_ISR_TSOVF_Msk

◆ RTC_ISR_TSOVF_Msk

#define RTC_ISR_TSOVF_Msk   (0x1U << RTC_ISR_TSOVF_Pos)

0x00001000

◆ RTC_ISR_TSOVF_Pos

#define RTC_ISR_TSOVF_Pos   (12U)

◆ RTC_ISR_WUTF

#define RTC_ISR_WUTF   RTC_ISR_WUTF_Msk

◆ RTC_ISR_WUTF_Msk

#define RTC_ISR_WUTF_Msk   (0x1U << RTC_ISR_WUTF_Pos)

0x00000400

◆ RTC_ISR_WUTF_Pos

#define RTC_ISR_WUTF_Pos   (10U)

◆ RTC_ISR_WUTWF

#define RTC_ISR_WUTWF   RTC_ISR_WUTWF_Msk

◆ RTC_ISR_WUTWF_Msk

#define RTC_ISR_WUTWF_Msk   (0x1U << RTC_ISR_WUTWF_Pos)

0x00000004

◆ RTC_ISR_WUTWF_Pos

#define RTC_ISR_WUTWF_Pos   (2U)

◆ RTC_PRER_PREDIV_A

#define RTC_PRER_PREDIV_A   RTC_PRER_PREDIV_A_Msk

◆ RTC_PRER_PREDIV_A_Msk

#define RTC_PRER_PREDIV_A_Msk   (0x7FU << RTC_PRER_PREDIV_A_Pos)

0x007F0000

◆ RTC_PRER_PREDIV_A_Pos

#define RTC_PRER_PREDIV_A_Pos   (16U)

◆ RTC_PRER_PREDIV_S

#define RTC_PRER_PREDIV_S   RTC_PRER_PREDIV_S_Msk

◆ RTC_PRER_PREDIV_S_Msk

#define RTC_PRER_PREDIV_S_Msk   (0x7FFFU << RTC_PRER_PREDIV_S_Pos)

0x00007FFF

◆ RTC_PRER_PREDIV_S_Pos

#define RTC_PRER_PREDIV_S_Pos   (0U)

◆ RTC_SHIFTR_ADD1S

#define RTC_SHIFTR_ADD1S   RTC_SHIFTR_ADD1S_Msk

◆ RTC_SHIFTR_ADD1S_Msk

#define RTC_SHIFTR_ADD1S_Msk   (0x1U << RTC_SHIFTR_ADD1S_Pos)

0x80000000

◆ RTC_SHIFTR_ADD1S_Pos

#define RTC_SHIFTR_ADD1S_Pos   (31U)

◆ RTC_SHIFTR_SUBFS

#define RTC_SHIFTR_SUBFS   RTC_SHIFTR_SUBFS_Msk

◆ RTC_SHIFTR_SUBFS_Msk

#define RTC_SHIFTR_SUBFS_Msk   (0x7FFFU << RTC_SHIFTR_SUBFS_Pos)

0x00007FFF

◆ RTC_SHIFTR_SUBFS_Pos

#define RTC_SHIFTR_SUBFS_Pos   (0U)

◆ RTC_SMOOTHCALIB_SUPPORT

#define RTC_SMOOTHCALIB_SUPPORT

Smooth digital calibration feature support

◆ RTC_SSR_SS

#define RTC_SSR_SS   RTC_SSR_SS_Msk

◆ RTC_SSR_SS_Msk

#define RTC_SSR_SS_Msk   (0xFFFFU << RTC_SSR_SS_Pos)

0x0000FFFF

◆ RTC_SSR_SS_Pos

#define RTC_SSR_SS_Pos   (0U)

◆ RTC_SUBSECOND_SUPPORT

#define RTC_SUBSECOND_SUPPORT

Sub-second feature support

◆ RTC_TAFCR_ALARMOUTTYPE

#define RTC_TAFCR_ALARMOUTTYPE   RTC_TAFCR_ALARMOUTTYPE_Msk

◆ RTC_TAFCR_ALARMOUTTYPE_Msk

#define RTC_TAFCR_ALARMOUTTYPE_Msk   (0x1U << RTC_TAFCR_ALARMOUTTYPE_Pos)

0x00040000

◆ RTC_TAFCR_ALARMOUTTYPE_Pos

#define RTC_TAFCR_ALARMOUTTYPE_Pos   (18U)

◆ RTC_TAFCR_TAMP1E

#define RTC_TAFCR_TAMP1E   RTC_TAFCR_TAMP1E_Msk

◆ RTC_TAFCR_TAMP1E_Msk

#define RTC_TAFCR_TAMP1E_Msk   (0x1U << RTC_TAFCR_TAMP1E_Pos)

0x00000001

◆ RTC_TAFCR_TAMP1E_Pos

#define RTC_TAFCR_TAMP1E_Pos   (0U)

◆ RTC_TAFCR_TAMP1TRG

#define RTC_TAFCR_TAMP1TRG   RTC_TAFCR_TAMP1TRG_Msk

◆ RTC_TAFCR_TAMP1TRG_Msk

#define RTC_TAFCR_TAMP1TRG_Msk   (0x1U << RTC_TAFCR_TAMP1TRG_Pos)

0x00000002

◆ RTC_TAFCR_TAMP1TRG_Pos

#define RTC_TAFCR_TAMP1TRG_Pos   (1U)

◆ RTC_TAFCR_TAMP2E

#define RTC_TAFCR_TAMP2E   RTC_TAFCR_TAMP2E_Msk

◆ RTC_TAFCR_TAMP2E_Msk

#define RTC_TAFCR_TAMP2E_Msk   (0x1U << RTC_TAFCR_TAMP2E_Pos)

0x00000008

◆ RTC_TAFCR_TAMP2E_Pos

#define RTC_TAFCR_TAMP2E_Pos   (3U)

◆ RTC_TAFCR_TAMP2TRG

#define RTC_TAFCR_TAMP2TRG   RTC_TAFCR_TAMP2TRG_Msk

◆ RTC_TAFCR_TAMP2TRG_Msk

#define RTC_TAFCR_TAMP2TRG_Msk   (0x1U << RTC_TAFCR_TAMP2TRG_Pos)

0x00000010

◆ RTC_TAFCR_TAMP2TRG_Pos

#define RTC_TAFCR_TAMP2TRG_Pos   (4U)

◆ RTC_TAFCR_TAMP3E

#define RTC_TAFCR_TAMP3E   RTC_TAFCR_TAMP3E_Msk

◆ RTC_TAFCR_TAMP3E_Msk

#define RTC_TAFCR_TAMP3E_Msk   (0x1U << RTC_TAFCR_TAMP3E_Pos)

0x00000020

◆ RTC_TAFCR_TAMP3E_Pos

#define RTC_TAFCR_TAMP3E_Pos   (5U)

◆ RTC_TAFCR_TAMP3TRG

#define RTC_TAFCR_TAMP3TRG   RTC_TAFCR_TAMP3TRG_Msk

◆ RTC_TAFCR_TAMP3TRG_Msk

#define RTC_TAFCR_TAMP3TRG_Msk   (0x1U << RTC_TAFCR_TAMP3TRG_Pos)

0x00000040

◆ RTC_TAFCR_TAMP3TRG_Pos

#define RTC_TAFCR_TAMP3TRG_Pos   (6U)

◆ RTC_TAFCR_TAMPFLT

#define RTC_TAFCR_TAMPFLT   RTC_TAFCR_TAMPFLT_Msk

◆ RTC_TAFCR_TAMPFLT_0

#define RTC_TAFCR_TAMPFLT_0   (0x1U << RTC_TAFCR_TAMPFLT_Pos)

0x00000800

◆ RTC_TAFCR_TAMPFLT_1

#define RTC_TAFCR_TAMPFLT_1   (0x2U << RTC_TAFCR_TAMPFLT_Pos)

0x00001000

◆ RTC_TAFCR_TAMPFLT_Msk

#define RTC_TAFCR_TAMPFLT_Msk   (0x3U << RTC_TAFCR_TAMPFLT_Pos)

0x00001800

◆ RTC_TAFCR_TAMPFLT_Pos

#define RTC_TAFCR_TAMPFLT_Pos   (11U)

◆ RTC_TAFCR_TAMPFREQ

#define RTC_TAFCR_TAMPFREQ   RTC_TAFCR_TAMPFREQ_Msk

◆ RTC_TAFCR_TAMPFREQ_0

#define RTC_TAFCR_TAMPFREQ_0   (0x1U << RTC_TAFCR_TAMPFREQ_Pos)

0x00000100

◆ RTC_TAFCR_TAMPFREQ_1

#define RTC_TAFCR_TAMPFREQ_1   (0x2U << RTC_TAFCR_TAMPFREQ_Pos)

0x00000200

◆ RTC_TAFCR_TAMPFREQ_2

#define RTC_TAFCR_TAMPFREQ_2   (0x4U << RTC_TAFCR_TAMPFREQ_Pos)

0x00000400

◆ RTC_TAFCR_TAMPFREQ_Msk

#define RTC_TAFCR_TAMPFREQ_Msk   (0x7U << RTC_TAFCR_TAMPFREQ_Pos)

0x00000700

◆ RTC_TAFCR_TAMPFREQ_Pos

#define RTC_TAFCR_TAMPFREQ_Pos   (8U)

◆ RTC_TAFCR_TAMPIE

#define RTC_TAFCR_TAMPIE   RTC_TAFCR_TAMPIE_Msk

◆ RTC_TAFCR_TAMPIE_Msk

#define RTC_TAFCR_TAMPIE_Msk   (0x1U << RTC_TAFCR_TAMPIE_Pos)

0x00000004

◆ RTC_TAFCR_TAMPIE_Pos

#define RTC_TAFCR_TAMPIE_Pos   (2U)

◆ RTC_TAFCR_TAMPPRCH

#define RTC_TAFCR_TAMPPRCH   RTC_TAFCR_TAMPPRCH_Msk

◆ RTC_TAFCR_TAMPPRCH_0

#define RTC_TAFCR_TAMPPRCH_0   (0x1U << RTC_TAFCR_TAMPPRCH_Pos)

0x00002000

◆ RTC_TAFCR_TAMPPRCH_1

#define RTC_TAFCR_TAMPPRCH_1   (0x2U << RTC_TAFCR_TAMPPRCH_Pos)

0x00004000

◆ RTC_TAFCR_TAMPPRCH_Msk

#define RTC_TAFCR_TAMPPRCH_Msk   (0x3U << RTC_TAFCR_TAMPPRCH_Pos)

0x00006000

◆ RTC_TAFCR_TAMPPRCH_Pos

#define RTC_TAFCR_TAMPPRCH_Pos   (13U)

◆ RTC_TAFCR_TAMPPUDIS

#define RTC_TAFCR_TAMPPUDIS   RTC_TAFCR_TAMPPUDIS_Msk

◆ RTC_TAFCR_TAMPPUDIS_Msk

#define RTC_TAFCR_TAMPPUDIS_Msk   (0x1U << RTC_TAFCR_TAMPPUDIS_Pos)

0x00008000

◆ RTC_TAFCR_TAMPPUDIS_Pos

#define RTC_TAFCR_TAMPPUDIS_Pos   (15U)

◆ RTC_TAFCR_TAMPTS

#define RTC_TAFCR_TAMPTS   RTC_TAFCR_TAMPTS_Msk

◆ RTC_TAFCR_TAMPTS_Msk

#define RTC_TAFCR_TAMPTS_Msk   (0x1U << RTC_TAFCR_TAMPTS_Pos)

0x00000080

◆ RTC_TAFCR_TAMPTS_Pos

#define RTC_TAFCR_TAMPTS_Pos   (7U)

◆ RTC_TAMPER1_SUPPORT

#define RTC_TAMPER1_SUPPORT

TAMPER 1 feature support

◆ RTC_TAMPER2_SUPPORT

#define RTC_TAMPER2_SUPPORT

TAMPER 2 feature support

◆ RTC_TAMPER3_SUPPORT

#define RTC_TAMPER3_SUPPORT

TAMPER 3 feature support

◆ RTC_TR_HT

#define RTC_TR_HT   RTC_TR_HT_Msk

◆ RTC_TR_HT_0

#define RTC_TR_HT_0   (0x1U << RTC_TR_HT_Pos)

0x00100000

◆ RTC_TR_HT_1

#define RTC_TR_HT_1   (0x2U << RTC_TR_HT_Pos)

0x00200000

◆ RTC_TR_HT_Msk

#define RTC_TR_HT_Msk   (0x3U << RTC_TR_HT_Pos)

0x00300000

◆ RTC_TR_HT_Pos

#define RTC_TR_HT_Pos   (20U)

◆ RTC_TR_HU

#define RTC_TR_HU   RTC_TR_HU_Msk

◆ RTC_TR_HU_0

#define RTC_TR_HU_0   (0x1U << RTC_TR_HU_Pos)

0x00010000

◆ RTC_TR_HU_1

#define RTC_TR_HU_1   (0x2U << RTC_TR_HU_Pos)

0x00020000

◆ RTC_TR_HU_2

#define RTC_TR_HU_2   (0x4U << RTC_TR_HU_Pos)

0x00040000

◆ RTC_TR_HU_3

#define RTC_TR_HU_3   (0x8U << RTC_TR_HU_Pos)

0x00080000

◆ RTC_TR_HU_Msk

#define RTC_TR_HU_Msk   (0xFU << RTC_TR_HU_Pos)

0x000F0000

◆ RTC_TR_HU_Pos

#define RTC_TR_HU_Pos   (16U)

◆ RTC_TR_MNT

#define RTC_TR_MNT   RTC_TR_MNT_Msk

◆ RTC_TR_MNT_0

#define RTC_TR_MNT_0   (0x1U << RTC_TR_MNT_Pos)

0x00001000

◆ RTC_TR_MNT_1

#define RTC_TR_MNT_1   (0x2U << RTC_TR_MNT_Pos)

0x00002000

◆ RTC_TR_MNT_2

#define RTC_TR_MNT_2   (0x4U << RTC_TR_MNT_Pos)

0x00004000

◆ RTC_TR_MNT_Msk

#define RTC_TR_MNT_Msk   (0x7U << RTC_TR_MNT_Pos)

0x00007000

◆ RTC_TR_MNT_Pos

#define RTC_TR_MNT_Pos   (12U)

◆ RTC_TR_MNU

#define RTC_TR_MNU   RTC_TR_MNU_Msk

◆ RTC_TR_MNU_0

#define RTC_TR_MNU_0   (0x1U << RTC_TR_MNU_Pos)

0x00000100

◆ RTC_TR_MNU_1

#define RTC_TR_MNU_1   (0x2U << RTC_TR_MNU_Pos)

0x00000200

◆ RTC_TR_MNU_2

#define RTC_TR_MNU_2   (0x4U << RTC_TR_MNU_Pos)

0x00000400

◆ RTC_TR_MNU_3

#define RTC_TR_MNU_3   (0x8U << RTC_TR_MNU_Pos)

0x00000800

◆ RTC_TR_MNU_Msk

#define RTC_TR_MNU_Msk   (0xFU << RTC_TR_MNU_Pos)

0x00000F00

◆ RTC_TR_MNU_Pos

#define RTC_TR_MNU_Pos   (8U)

◆ RTC_TR_PM

#define RTC_TR_PM   RTC_TR_PM_Msk

◆ RTC_TR_PM_Msk

#define RTC_TR_PM_Msk   (0x1U << RTC_TR_PM_Pos)

0x00400000

◆ RTC_TR_PM_Pos

#define RTC_TR_PM_Pos   (22U)

◆ RTC_TR_ST

#define RTC_TR_ST   RTC_TR_ST_Msk

◆ RTC_TR_ST_0

#define RTC_TR_ST_0   (0x1U << RTC_TR_ST_Pos)

0x00000010

◆ RTC_TR_ST_1

#define RTC_TR_ST_1   (0x2U << RTC_TR_ST_Pos)

0x00000020

◆ RTC_TR_ST_2

#define RTC_TR_ST_2   (0x4U << RTC_TR_ST_Pos)

0x00000040

◆ RTC_TR_ST_Msk

#define RTC_TR_ST_Msk   (0x7U << RTC_TR_ST_Pos)

0x00000070

◆ RTC_TR_ST_Pos

#define RTC_TR_ST_Pos   (4U)

◆ RTC_TR_SU

#define RTC_TR_SU   RTC_TR_SU_Msk

◆ RTC_TR_SU_0

#define RTC_TR_SU_0   (0x1U << RTC_TR_SU_Pos)

0x00000001

◆ RTC_TR_SU_1

#define RTC_TR_SU_1   (0x2U << RTC_TR_SU_Pos)

0x00000002

◆ RTC_TR_SU_2

#define RTC_TR_SU_2   (0x4U << RTC_TR_SU_Pos)

0x00000004

◆ RTC_TR_SU_3

#define RTC_TR_SU_3   (0x8U << RTC_TR_SU_Pos)

0x00000008

◆ RTC_TR_SU_Msk

#define RTC_TR_SU_Msk   (0xFU << RTC_TR_SU_Pos)

0x0000000F

◆ RTC_TR_SU_Pos

#define RTC_TR_SU_Pos   (0U)

◆ RTC_TSDR_DT

#define RTC_TSDR_DT   RTC_TSDR_DT_Msk

◆ RTC_TSDR_DT_0

#define RTC_TSDR_DT_0   (0x1U << RTC_TSDR_DT_Pos)

0x00000010

◆ RTC_TSDR_DT_1

#define RTC_TSDR_DT_1   (0x2U << RTC_TSDR_DT_Pos)

0x00000020

◆ RTC_TSDR_DT_Msk

#define RTC_TSDR_DT_Msk   (0x3U << RTC_TSDR_DT_Pos)

0x00000030

◆ RTC_TSDR_DT_Pos

#define RTC_TSDR_DT_Pos   (4U)

◆ RTC_TSDR_DU

#define RTC_TSDR_DU   RTC_TSDR_DU_Msk

◆ RTC_TSDR_DU_0

#define RTC_TSDR_DU_0   (0x1U << RTC_TSDR_DU_Pos)

0x00000001

◆ RTC_TSDR_DU_1

#define RTC_TSDR_DU_1   (0x2U << RTC_TSDR_DU_Pos)

0x00000002

◆ RTC_TSDR_DU_2

#define RTC_TSDR_DU_2   (0x4U << RTC_TSDR_DU_Pos)

0x00000004

◆ RTC_TSDR_DU_3

#define RTC_TSDR_DU_3   (0x8U << RTC_TSDR_DU_Pos)

0x00000008

◆ RTC_TSDR_DU_Msk

#define RTC_TSDR_DU_Msk   (0xFU << RTC_TSDR_DU_Pos)

0x0000000F

◆ RTC_TSDR_DU_Pos

#define RTC_TSDR_DU_Pos   (0U)

◆ RTC_TSDR_MT

#define RTC_TSDR_MT   RTC_TSDR_MT_Msk

◆ RTC_TSDR_MT_Msk

#define RTC_TSDR_MT_Msk   (0x1U << RTC_TSDR_MT_Pos)

0x00001000

◆ RTC_TSDR_MT_Pos

#define RTC_TSDR_MT_Pos   (12U)

◆ RTC_TSDR_MU

#define RTC_TSDR_MU   RTC_TSDR_MU_Msk

◆ RTC_TSDR_MU_0

#define RTC_TSDR_MU_0   (0x1U << RTC_TSDR_MU_Pos)

0x00000100

◆ RTC_TSDR_MU_1

#define RTC_TSDR_MU_1   (0x2U << RTC_TSDR_MU_Pos)

0x00000200

◆ RTC_TSDR_MU_2

#define RTC_TSDR_MU_2   (0x4U << RTC_TSDR_MU_Pos)

0x00000400

◆ RTC_TSDR_MU_3

#define RTC_TSDR_MU_3   (0x8U << RTC_TSDR_MU_Pos)

0x00000800

◆ RTC_TSDR_MU_Msk

#define RTC_TSDR_MU_Msk   (0xFU << RTC_TSDR_MU_Pos)

0x00000F00

◆ RTC_TSDR_MU_Pos

#define RTC_TSDR_MU_Pos   (8U)

◆ RTC_TSDR_WDU

#define RTC_TSDR_WDU   RTC_TSDR_WDU_Msk

◆ RTC_TSDR_WDU_0

#define RTC_TSDR_WDU_0   (0x1U << RTC_TSDR_WDU_Pos)

0x00002000

◆ RTC_TSDR_WDU_1

#define RTC_TSDR_WDU_1   (0x2U << RTC_TSDR_WDU_Pos)

0x00004000

◆ RTC_TSDR_WDU_2

#define RTC_TSDR_WDU_2   (0x4U << RTC_TSDR_WDU_Pos)

0x00008000

◆ RTC_TSDR_WDU_Msk

#define RTC_TSDR_WDU_Msk   (0x7U << RTC_TSDR_WDU_Pos)

0x0000E000

◆ RTC_TSDR_WDU_Pos

#define RTC_TSDR_WDU_Pos   (13U)

◆ RTC_TSSSR_SS

#define RTC_TSSSR_SS   RTC_TSSSR_SS_Msk

◆ RTC_TSSSR_SS_Msk

#define RTC_TSSSR_SS_Msk   (0xFFFFU << RTC_TSSSR_SS_Pos)

0x0000FFFF

◆ RTC_TSSSR_SS_Pos

#define RTC_TSSSR_SS_Pos   (0U)

◆ RTC_TSTR_HT

#define RTC_TSTR_HT   RTC_TSTR_HT_Msk

◆ RTC_TSTR_HT_0

#define RTC_TSTR_HT_0   (0x1U << RTC_TSTR_HT_Pos)

0x00100000

◆ RTC_TSTR_HT_1

#define RTC_TSTR_HT_1   (0x2U << RTC_TSTR_HT_Pos)

0x00200000

◆ RTC_TSTR_HT_Msk

#define RTC_TSTR_HT_Msk   (0x3U << RTC_TSTR_HT_Pos)

0x00300000

◆ RTC_TSTR_HT_Pos

#define RTC_TSTR_HT_Pos   (20U)

◆ RTC_TSTR_HU

#define RTC_TSTR_HU   RTC_TSTR_HU_Msk

◆ RTC_TSTR_HU_0

#define RTC_TSTR_HU_0   (0x1U << RTC_TSTR_HU_Pos)

0x00010000

◆ RTC_TSTR_HU_1

#define RTC_TSTR_HU_1   (0x2U << RTC_TSTR_HU_Pos)

0x00020000

◆ RTC_TSTR_HU_2

#define RTC_TSTR_HU_2   (0x4U << RTC_TSTR_HU_Pos)

0x00040000

◆ RTC_TSTR_HU_3

#define RTC_TSTR_HU_3   (0x8U << RTC_TSTR_HU_Pos)

0x00080000

◆ RTC_TSTR_HU_Msk

#define RTC_TSTR_HU_Msk   (0xFU << RTC_TSTR_HU_Pos)

0x000F0000

◆ RTC_TSTR_HU_Pos

#define RTC_TSTR_HU_Pos   (16U)

◆ RTC_TSTR_MNT

#define RTC_TSTR_MNT   RTC_TSTR_MNT_Msk

◆ RTC_TSTR_MNT_0

#define RTC_TSTR_MNT_0   (0x1U << RTC_TSTR_MNT_Pos)

0x00001000

◆ RTC_TSTR_MNT_1

#define RTC_TSTR_MNT_1   (0x2U << RTC_TSTR_MNT_Pos)

0x00002000

◆ RTC_TSTR_MNT_2

#define RTC_TSTR_MNT_2   (0x4U << RTC_TSTR_MNT_Pos)

0x00004000

◆ RTC_TSTR_MNT_Msk

#define RTC_TSTR_MNT_Msk   (0x7U << RTC_TSTR_MNT_Pos)

0x00007000

◆ RTC_TSTR_MNT_Pos

#define RTC_TSTR_MNT_Pos   (12U)

◆ RTC_TSTR_MNU

#define RTC_TSTR_MNU   RTC_TSTR_MNU_Msk

◆ RTC_TSTR_MNU_0

#define RTC_TSTR_MNU_0   (0x1U << RTC_TSTR_MNU_Pos)

0x00000100

◆ RTC_TSTR_MNU_1

#define RTC_TSTR_MNU_1   (0x2U << RTC_TSTR_MNU_Pos)

0x00000200

◆ RTC_TSTR_MNU_2

#define RTC_TSTR_MNU_2   (0x4U << RTC_TSTR_MNU_Pos)

0x00000400

◆ RTC_TSTR_MNU_3

#define RTC_TSTR_MNU_3   (0x8U << RTC_TSTR_MNU_Pos)

0x00000800

◆ RTC_TSTR_MNU_Msk

#define RTC_TSTR_MNU_Msk   (0xFU << RTC_TSTR_MNU_Pos)

0x00000F00

◆ RTC_TSTR_MNU_Pos

#define RTC_TSTR_MNU_Pos   (8U)

◆ RTC_TSTR_PM

#define RTC_TSTR_PM   RTC_TSTR_PM_Msk

◆ RTC_TSTR_PM_Msk

#define RTC_TSTR_PM_Msk   (0x1U << RTC_TSTR_PM_Pos)

0x00400000

◆ RTC_TSTR_PM_Pos

#define RTC_TSTR_PM_Pos   (22U)

◆ RTC_TSTR_ST

#define RTC_TSTR_ST   RTC_TSTR_ST_Msk

◆ RTC_TSTR_ST_0

#define RTC_TSTR_ST_0   (0x1U << RTC_TSTR_ST_Pos)

0x00000010

◆ RTC_TSTR_ST_1

#define RTC_TSTR_ST_1   (0x2U << RTC_TSTR_ST_Pos)

0x00000020

◆ RTC_TSTR_ST_2

#define RTC_TSTR_ST_2   (0x4U << RTC_TSTR_ST_Pos)

0x00000040

◆ RTC_TSTR_ST_Msk

#define RTC_TSTR_ST_Msk   (0x7U << RTC_TSTR_ST_Pos)

0x00000070

◆ RTC_TSTR_ST_Pos

#define RTC_TSTR_ST_Pos   (4U)

◆ RTC_TSTR_SU

#define RTC_TSTR_SU   RTC_TSTR_SU_Msk

◆ RTC_TSTR_SU_0

#define RTC_TSTR_SU_0   (0x1U << RTC_TSTR_SU_Pos)

0x00000001

◆ RTC_TSTR_SU_1

#define RTC_TSTR_SU_1   (0x2U << RTC_TSTR_SU_Pos)

0x00000002

◆ RTC_TSTR_SU_2

#define RTC_TSTR_SU_2   (0x4U << RTC_TSTR_SU_Pos)

0x00000004

◆ RTC_TSTR_SU_3

#define RTC_TSTR_SU_3   (0x8U << RTC_TSTR_SU_Pos)

0x00000008

◆ RTC_TSTR_SU_Msk

#define RTC_TSTR_SU_Msk   (0xFU << RTC_TSTR_SU_Pos)

0x0000000F

◆ RTC_TSTR_SU_Pos

#define RTC_TSTR_SU_Pos   (0U)

◆ RTC_WAKEUP_SUPPORT

#define RTC_WAKEUP_SUPPORT

WAKEUP feature support

◆ RTC_WPR_KEY

#define RTC_WPR_KEY   RTC_WPR_KEY_Msk

◆ RTC_WPR_KEY_Msk

#define RTC_WPR_KEY_Msk   (0xFFU << RTC_WPR_KEY_Pos)

0x000000FF

◆ RTC_WPR_KEY_Pos

#define RTC_WPR_KEY_Pos   (0U)

◆ RTC_WUTR_WUT

#define RTC_WUTR_WUT   RTC_WUTR_WUT_Msk

◆ RTC_WUTR_WUT_Msk

#define RTC_WUTR_WUT_Msk   (0xFFFFU << RTC_WUTR_WUT_Pos)

0x0000FFFF

◆ RTC_WUTR_WUT_Pos

#define RTC_WUTR_WUT_Pos   (0U)

◆ SCB_AFSR_IMPDEF

#define SCB_AFSR_IMPDEF   SCB_AFSR_IMPDEF_Msk

Implementation defined

◆ SCB_AFSR_IMPDEF_Msk

#define SCB_AFSR_IMPDEF_Msk   (0xFFFFFFFFU << SCB_AFSR_IMPDEF_Pos)

0xFFFFFFFF

◆ SCB_AFSR_IMPDEF_Pos

#define SCB_AFSR_IMPDEF_Pos   (0U)

◆ SCB_AIRCR_ENDIANESS

#define SCB_AIRCR_ENDIANESS   (0x00008000U)

Data endianness bit

◆ SCB_AIRCR_PRIGROUP

#define SCB_AIRCR_PRIGROUP   (0x00000700U)

PRIGROUP[2:0] bits (Priority group)

◆ SCB_AIRCR_PRIGROUP0

#define SCB_AIRCR_PRIGROUP0   (0x00000000U)

Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority)

◆ SCB_AIRCR_PRIGROUP1

#define SCB_AIRCR_PRIGROUP1   (0x00000100U)

Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority)

◆ SCB_AIRCR_PRIGROUP2

#define SCB_AIRCR_PRIGROUP2   (0x00000200U)

Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority)

◆ SCB_AIRCR_PRIGROUP3

#define SCB_AIRCR_PRIGROUP3   (0x00000300U)

Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority)

◆ SCB_AIRCR_PRIGROUP4

#define SCB_AIRCR_PRIGROUP4   (0x00000400U)

Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority)

◆ SCB_AIRCR_PRIGROUP5

#define SCB_AIRCR_PRIGROUP5   (0x00000500U)

Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority)

◆ SCB_AIRCR_PRIGROUP6

#define SCB_AIRCR_PRIGROUP6   (0x00000600U)

Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority)

◆ SCB_AIRCR_PRIGROUP7

#define SCB_AIRCR_PRIGROUP7   (0x00000700U)

Priority group=7 (no pre-emption priority, 8 bits of subpriority)

◆ SCB_AIRCR_PRIGROUP_0

#define SCB_AIRCR_PRIGROUP_0   (0x00000100U)

Bit 0

◆ SCB_AIRCR_PRIGROUP_1

#define SCB_AIRCR_PRIGROUP_1   (0x00000200U)

Bit 1

◆ SCB_AIRCR_PRIGROUP_2

#define SCB_AIRCR_PRIGROUP_2   (0x00000400U)

Bit 2

◆ SCB_AIRCR_SYSRESETREQ

#define SCB_AIRCR_SYSRESETREQ   (0x00000004U)

Requests chip control logic to generate a reset

◆ SCB_AIRCR_VECTCLRACTIVE

#define SCB_AIRCR_VECTCLRACTIVE   (0x00000002U)

Clear active vector bit

◆ SCB_AIRCR_VECTKEY

#define SCB_AIRCR_VECTKEY   (0xFFFF0000U)

Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT)

◆ SCB_AIRCR_VECTRESET

#define SCB_AIRCR_VECTRESET   (0x00000001U)

System Reset bit

◆ SCB_BFAR_ADDRESS

#define SCB_BFAR_ADDRESS   SCB_BFAR_ADDRESS_Msk

Bus fault address field

◆ SCB_BFAR_ADDRESS_Msk

#define SCB_BFAR_ADDRESS_Msk   (0xFFFFFFFFU << SCB_BFAR_ADDRESS_Pos)

0xFFFFFFFF

◆ SCB_BFAR_ADDRESS_Pos

#define SCB_BFAR_ADDRESS_Pos   (0U)

◆ SCB_CCR_BFHFNMIGN

#define SCB_CCR_BFHFNMIGN   (0x00000100U)

Handlers running at priority -1 and -2

◆ SCB_CCR_DIV_0_TRP

#define SCB_CCR_DIV_0_TRP   (0x00000010U)

Trap on Divide by 0

◆ SCB_CCR_NONBASETHRDENA

#define SCB_CCR_NONBASETHRDENA   (0x00000001U)

Thread mode can be entered from any level in Handler mode by controlled return value

◆ SCB_CCR_STKALIGN

#define SCB_CCR_STKALIGN   (0x00000200U)

On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned

◆ SCB_CCR_UNALIGN_TRP

#define SCB_CCR_UNALIGN_TRP   (0x00000008U)

Trap for unaligned access

◆ SCB_CCR_USERSETMPEND

#define SCB_CCR_USERSETMPEND   (0x00000002U)

Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception

◆ SCB_CFSR_BFARVALID

#define SCB_CFSR_BFARVALID   SCB_CFSR_BFARVALID_Msk

Bus Fault Address Register address valid flag UFSR

◆ SCB_CFSR_BFARVALID_Msk

#define SCB_CFSR_BFARVALID_Msk   (1UL << SCB_CFSR_BFARVALID_Pos)

SCB CFSR (BFSR): BFARVALID Mask

◆ SCB_CFSR_BFARVALID_Pos

#define SCB_CFSR_BFARVALID_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 7U)

SCB CFSR (BFSR): BFARVALID Position

◆ SCB_CFSR_DACCVIOL

#define SCB_CFSR_DACCVIOL   SCB_CFSR_DACCVIOL_Msk

Data access violation

◆ SCB_CFSR_DACCVIOL_Msk

#define SCB_CFSR_DACCVIOL_Msk   (1UL << SCB_CFSR_DACCVIOL_Pos)

SCB CFSR (MMFSR): DACCVIOL Mask

◆ SCB_CFSR_DACCVIOL_Pos

#define SCB_CFSR_DACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 1U)

SCB CFSR (MMFSR): DACCVIOL Position

◆ SCB_CFSR_DIVBYZERO

#define SCB_CFSR_DIVBYZERO   SCB_CFSR_DIVBYZERO_Msk

Fault occurs when SDIV or DIV instruction is used with a divisor of 0

◆ SCB_CFSR_DIVBYZERO_Msk

#define SCB_CFSR_DIVBYZERO_Msk   (1UL << SCB_CFSR_DIVBYZERO_Pos)

SCB CFSR (UFSR): DIVBYZERO Mask

◆ SCB_CFSR_DIVBYZERO_Pos

#define SCB_CFSR_DIVBYZERO_Pos   (SCB_CFSR_USGFAULTSR_Pos + 9U)

SCB CFSR (UFSR): DIVBYZERO Position

◆ SCB_CFSR_IACCVIOL

#define SCB_CFSR_IACCVIOL   SCB_CFSR_IACCVIOL_Msk

Instruction access violation

◆ SCB_CFSR_IACCVIOL_Msk

#define SCB_CFSR_IACCVIOL_Msk   (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/)

SCB CFSR (MMFSR): IACCVIOL Mask

◆ SCB_CFSR_IACCVIOL_Pos

#define SCB_CFSR_IACCVIOL_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 0U)

< MFSR SCB CFSR (MMFSR): IACCVIOL Position

◆ SCB_CFSR_IBUSERR

#define SCB_CFSR_IBUSERR   SCB_CFSR_IBUSERR_Msk

Instruction bus error flag

◆ SCB_CFSR_IBUSERR_Msk

#define SCB_CFSR_IBUSERR_Msk   (1UL << SCB_CFSR_IBUSERR_Pos)

SCB CFSR (BFSR): IBUSERR Mask

◆ SCB_CFSR_IBUSERR_Pos

#define SCB_CFSR_IBUSERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 0U)

SCB CFSR (BFSR): IBUSERR Position

◆ SCB_CFSR_IMPRECISERR

#define SCB_CFSR_IMPRECISERR   SCB_CFSR_IMPRECISERR_Msk

Imprecise data bus error

◆ SCB_CFSR_IMPRECISERR_Msk

#define SCB_CFSR_IMPRECISERR_Msk   (1UL << SCB_CFSR_IMPRECISERR_Pos)

SCB CFSR (BFSR): IMPRECISERR Mask

◆ SCB_CFSR_IMPRECISERR_Pos

#define SCB_CFSR_IMPRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 2U)

SCB CFSR (BFSR): IMPRECISERR Position

◆ SCB_CFSR_INVPC

#define SCB_CFSR_INVPC   SCB_CFSR_INVPC_Msk

Attempt to load EXC_RETURN into pc illegally

◆ SCB_CFSR_INVPC_Msk

#define SCB_CFSR_INVPC_Msk   (1UL << SCB_CFSR_INVPC_Pos)

SCB CFSR (UFSR): INVPC Mask

◆ SCB_CFSR_INVPC_Pos

#define SCB_CFSR_INVPC_Pos   (SCB_CFSR_USGFAULTSR_Pos + 2U)

SCB CFSR (UFSR): INVPC Position

◆ SCB_CFSR_INVSTATE

#define SCB_CFSR_INVSTATE   SCB_CFSR_INVSTATE_Msk

Invalid combination of EPSR and instruction

◆ SCB_CFSR_INVSTATE_Msk

#define SCB_CFSR_INVSTATE_Msk   (1UL << SCB_CFSR_INVSTATE_Pos)

SCB CFSR (UFSR): INVSTATE Mask

◆ SCB_CFSR_INVSTATE_Pos

#define SCB_CFSR_INVSTATE_Pos   (SCB_CFSR_USGFAULTSR_Pos + 1U)

SCB CFSR (UFSR): INVSTATE Position

◆ SCB_CFSR_MMARVALID

#define SCB_CFSR_MMARVALID   SCB_CFSR_MMARVALID_Msk

Memory Manage Address Register address valid flag BFSR

◆ SCB_CFSR_MMARVALID_Msk

#define SCB_CFSR_MMARVALID_Msk   (1UL << SCB_CFSR_MMARVALID_Pos)

SCB CFSR (MMFSR): MMARVALID Mask

◆ SCB_CFSR_MMARVALID_Pos

#define SCB_CFSR_MMARVALID_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 7U)

SCB CFSR (MMFSR): MMARVALID Position

◆ SCB_CFSR_MSTKERR

#define SCB_CFSR_MSTKERR   SCB_CFSR_MSTKERR_Msk

Stacking error

◆ SCB_CFSR_MSTKERR_Msk

#define SCB_CFSR_MSTKERR_Msk   (1UL << SCB_CFSR_MSTKERR_Pos)

SCB CFSR (MMFSR): MSTKERR Mask

◆ SCB_CFSR_MSTKERR_Pos

#define SCB_CFSR_MSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 4U)

SCB CFSR (MMFSR): MSTKERR Position

◆ SCB_CFSR_MUNSTKERR

#define SCB_CFSR_MUNSTKERR   SCB_CFSR_MUNSTKERR_Msk

Unstacking error

◆ SCB_CFSR_MUNSTKERR_Msk

#define SCB_CFSR_MUNSTKERR_Msk   (1UL << SCB_CFSR_MUNSTKERR_Pos)

SCB CFSR (MMFSR): MUNSTKERR Mask

◆ SCB_CFSR_MUNSTKERR_Pos

#define SCB_CFSR_MUNSTKERR_Pos   (SCB_SHCSR_MEMFAULTACT_Pos + 3U)

SCB CFSR (MMFSR): MUNSTKERR Position

◆ SCB_CFSR_NOCP

#define SCB_CFSR_NOCP   SCB_CFSR_NOCP_Msk

Attempt to use a coprocessor instruction

◆ SCB_CFSR_NOCP_Msk

#define SCB_CFSR_NOCP_Msk   (1UL << SCB_CFSR_NOCP_Pos)

SCB CFSR (UFSR): NOCP Mask

◆ SCB_CFSR_NOCP_Pos

#define SCB_CFSR_NOCP_Pos   (SCB_CFSR_USGFAULTSR_Pos + 3U)

SCB CFSR (UFSR): NOCP Position

◆ SCB_CFSR_PRECISERR

#define SCB_CFSR_PRECISERR   SCB_CFSR_PRECISERR_Msk

Precise data bus error

◆ SCB_CFSR_PRECISERR_Msk

#define SCB_CFSR_PRECISERR_Msk   (1UL << SCB_CFSR_PRECISERR_Pos)

SCB CFSR (BFSR): PRECISERR Mask

◆ SCB_CFSR_PRECISERR_Pos

#define SCB_CFSR_PRECISERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 1U)

SCB CFSR (BFSR): PRECISERR Position

◆ SCB_CFSR_STKERR

#define SCB_CFSR_STKERR   SCB_CFSR_STKERR_Msk

Stacking error

◆ SCB_CFSR_STKERR_Msk

#define SCB_CFSR_STKERR_Msk   (1UL << SCB_CFSR_STKERR_Pos)

SCB CFSR (BFSR): STKERR Mask

◆ SCB_CFSR_STKERR_Pos

#define SCB_CFSR_STKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 4U)

SCB CFSR (BFSR): STKERR Position

◆ SCB_CFSR_UNALIGNED

#define SCB_CFSR_UNALIGNED   SCB_CFSR_UNALIGNED_Msk

Fault occurs when there is an attempt to make an unaligned memory access

◆ SCB_CFSR_UNALIGNED_Msk

#define SCB_CFSR_UNALIGNED_Msk   (1UL << SCB_CFSR_UNALIGNED_Pos)

SCB CFSR (UFSR): UNALIGNED Mask

◆ SCB_CFSR_UNALIGNED_Pos

#define SCB_CFSR_UNALIGNED_Pos   (SCB_CFSR_USGFAULTSR_Pos + 8U)

SCB CFSR (UFSR): UNALIGNED Position

◆ SCB_CFSR_UNDEFINSTR

#define SCB_CFSR_UNDEFINSTR   SCB_CFSR_UNDEFINSTR_Msk

The processor attempt to excecute an undefined instruction

◆ SCB_CFSR_UNDEFINSTR_Msk

#define SCB_CFSR_UNDEFINSTR_Msk   (1UL << SCB_CFSR_UNDEFINSTR_Pos)

SCB CFSR (UFSR): UNDEFINSTR Mask

◆ SCB_CFSR_UNDEFINSTR_Pos

#define SCB_CFSR_UNDEFINSTR_Pos   (SCB_CFSR_USGFAULTSR_Pos + 0U)

SCB CFSR (UFSR): UNDEFINSTR Position

◆ SCB_CFSR_UNSTKERR

#define SCB_CFSR_UNSTKERR   SCB_CFSR_UNSTKERR_Msk

Unstacking error

◆ SCB_CFSR_UNSTKERR_Msk

#define SCB_CFSR_UNSTKERR_Msk   (1UL << SCB_CFSR_UNSTKERR_Pos)

SCB CFSR (BFSR): UNSTKERR Mask

◆ SCB_CFSR_UNSTKERR_Pos

#define SCB_CFSR_UNSTKERR_Pos   (SCB_CFSR_BUSFAULTSR_Pos + 3U)

SCB CFSR (BFSR): UNSTKERR Position

◆ SCB_CPUID_Constant

#define SCB_CPUID_Constant   (0x000F0000U)

Reads as 0x0F

◆ SCB_CPUID_IMPLEMENTER

#define SCB_CPUID_IMPLEMENTER   (0xFF000000U)

Implementer code. ARM is 0x41

◆ SCB_CPUID_PARTNO

#define SCB_CPUID_PARTNO   (0x0000FFF0U)

Number of processor within serie

◆ SCB_CPUID_REVISION

#define SCB_CPUID_REVISION   (0x0000000FU)

Implementation defined revision number

◆ SCB_CPUID_VARIANT

#define SCB_CPUID_VARIANT   (0x00F00000U)

Implementation defined variant number

◆ SCB_DFSR_BKPT

#define SCB_DFSR_BKPT   (0x00000002U)

BKPT flag

◆ SCB_DFSR_DWTTRAP

#define SCB_DFSR_DWTTRAP   (0x00000004U)

Data Watchpoint and Trace (DWT) flag

◆ SCB_DFSR_EXTERNAL

#define SCB_DFSR_EXTERNAL   (0x00000010U)

External debug request flag

◆ SCB_DFSR_HALTED

#define SCB_DFSR_HALTED   (0x00000001U)

Halt request flag

◆ SCB_DFSR_VCATCH

#define SCB_DFSR_VCATCH   (0x00000008U)

Vector catch flag

◆ SCB_HFSR_DEBUGEVT

#define SCB_HFSR_DEBUGEVT   (0x80000000U)

Fault related to debug

◆ SCB_HFSR_FORCED

#define SCB_HFSR_FORCED   (0x40000000U)

Hard Fault activated when a configurable Fault was received and cannot activate

◆ SCB_HFSR_VECTTBL

#define SCB_HFSR_VECTTBL   (0x00000002U)

Fault occures because of vector table read on exception processing

◆ SCB_ICSR_ISRPENDING

#define SCB_ICSR_ISRPENDING   (0x00400000U)

Interrupt pending flag

◆ SCB_ICSR_ISRPREEMPT

#define SCB_ICSR_ISRPREEMPT   (0x00800000U)

It indicates that a pending interrupt becomes active in the next running cycle

◆ SCB_ICSR_NMIPENDSET

#define SCB_ICSR_NMIPENDSET   (0x80000000U)

Set pending NMI bit

◆ SCB_ICSR_PENDSTCLR

#define SCB_ICSR_PENDSTCLR   (0x02000000U)

Clear pending SysTick bit

◆ SCB_ICSR_PENDSTSET

#define SCB_ICSR_PENDSTSET   (0x04000000U)

Set pending SysTick bit

◆ SCB_ICSR_PENDSVCLR

#define SCB_ICSR_PENDSVCLR   (0x08000000U)

Clear pending pendSV bit

◆ SCB_ICSR_PENDSVSET

#define SCB_ICSR_PENDSVSET   (0x10000000U)

Set pending pendSV bit

◆ SCB_ICSR_RETTOBASE

#define SCB_ICSR_RETTOBASE   (0x00000800U)

All active exceptions minus the IPSR_current_exception yields the empty set

◆ SCB_ICSR_VECTACTIVE

#define SCB_ICSR_VECTACTIVE   (0x000001FFU)

Active ISR number field

◆ SCB_ICSR_VECTPENDING

#define SCB_ICSR_VECTPENDING   (0x003FF000U)

Pending ISR number field

◆ SCB_MMFAR_ADDRESS

#define SCB_MMFAR_ADDRESS   SCB_MMFAR_ADDRESS_Msk

Mem Manage fault address field

◆ SCB_MMFAR_ADDRESS_Msk

#define SCB_MMFAR_ADDRESS_Msk   (0xFFFFFFFFU << SCB_MMFAR_ADDRESS_Pos)

0xFFFFFFFF

◆ SCB_MMFAR_ADDRESS_Pos

#define SCB_MMFAR_ADDRESS_Pos   (0U)

◆ SCB_SCR_SEVONPEND

#define SCB_SCR_SEVONPEND   (0x00000010U)

Wake up from WFE

◆ SCB_SCR_SLEEPDEEP

#define SCB_SCR_SLEEPDEEP   (0x00000004U)

Sleep deep bit

◆ SCB_SCR_SLEEPONEXIT

#define SCB_SCR_SLEEPONEXIT   (0x00000002U)

Sleep on exit bit

◆ SCB_SHCSR_BUSFAULTACT

#define SCB_SHCSR_BUSFAULTACT   (0x00000002U)

BusFault is active

◆ SCB_SHCSR_BUSFAULTENA

#define SCB_SHCSR_BUSFAULTENA   (0x00020000U)

Bus Fault enable

◆ SCB_SHCSR_BUSFAULTPENDED

#define SCB_SHCSR_BUSFAULTPENDED   (0x00004000U)

Bus Fault is pended

◆ SCB_SHCSR_MEMFAULTACT

#define SCB_SHCSR_MEMFAULTACT   (0x00000001U)

MemManage is active

◆ SCB_SHCSR_MEMFAULTENA

#define SCB_SHCSR_MEMFAULTENA   (0x00010000U)

MemManage enable

◆ SCB_SHCSR_MEMFAULTPENDED

#define SCB_SHCSR_MEMFAULTPENDED   (0x00002000U)

MemManage is pended

◆ SCB_SHCSR_MONITORACT

#define SCB_SHCSR_MONITORACT   (0x00000100U)

Monitor is active

◆ SCB_SHCSR_PENDSVACT

#define SCB_SHCSR_PENDSVACT   (0x00000400U)

PendSV is active

◆ SCB_SHCSR_SVCALLACT

#define SCB_SHCSR_SVCALLACT   (0x00000080U)

SVCall is active

◆ SCB_SHCSR_SVCALLPENDED

#define SCB_SHCSR_SVCALLPENDED   (0x00008000U)

SVCall is pended

◆ SCB_SHCSR_SYSTICKACT

#define SCB_SHCSR_SYSTICKACT   (0x00000800U)

SysTick is active

◆ SCB_SHCSR_USGFAULTACT

#define SCB_SHCSR_USGFAULTACT   (0x00000008U)

UsageFault is active

◆ SCB_SHCSR_USGFAULTENA

#define SCB_SHCSR_USGFAULTENA   (0x00040000U)

UsageFault enable

◆ SCB_SHCSR_USGFAULTPENDED

#define SCB_SHCSR_USGFAULTPENDED   (0x00001000U)

Usage Fault is pended

◆ SCB_SHPR_PRI_N

#define SCB_SHPR_PRI_N   SCB_SHPR_PRI_N_Msk

Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor

◆ SCB_SHPR_PRI_N1

#define SCB_SHPR_PRI_N1   SCB_SHPR_PRI_N1_Msk

Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved

◆ SCB_SHPR_PRI_N1_Msk

#define SCB_SHPR_PRI_N1_Msk   (0xFFU << SCB_SHPR_PRI_N1_Pos)

0x0000FF00

◆ SCB_SHPR_PRI_N1_Pos

#define SCB_SHPR_PRI_N1_Pos   (8U)

◆ SCB_SHPR_PRI_N2

#define SCB_SHPR_PRI_N2   SCB_SHPR_PRI_N2_Msk

Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV

◆ SCB_SHPR_PRI_N2_Msk

#define SCB_SHPR_PRI_N2_Msk   (0xFFU << SCB_SHPR_PRI_N2_Pos)

0x00FF0000

◆ SCB_SHPR_PRI_N2_Pos

#define SCB_SHPR_PRI_N2_Pos   (16U)

◆ SCB_SHPR_PRI_N3

#define SCB_SHPR_PRI_N3   SCB_SHPR_PRI_N3_Msk

Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick

◆ SCB_SHPR_PRI_N3_Msk

#define SCB_SHPR_PRI_N3_Msk   (0xFFU << SCB_SHPR_PRI_N3_Pos)

0xFF000000

◆ SCB_SHPR_PRI_N3_Pos

#define SCB_SHPR_PRI_N3_Pos   (24U)

◆ SCB_SHPR_PRI_N_Msk

#define SCB_SHPR_PRI_N_Msk   (0xFFU << SCB_SHPR_PRI_N_Pos)

0x000000FF

◆ SCB_SHPR_PRI_N_Pos

#define SCB_SHPR_PRI_N_Pos   (0U)

◆ SCB_VTOR_TBLBASE

#define SCB_VTOR_TBLBASE   (0x20000000U)

Table base in code(0) or RAM(1) ***************** Bit definition for SCB_AIRCR register

◆ SCB_VTOR_TBLOFF

#define SCB_VTOR_TBLOFF   (0x1FFFFF80U)

Vector table base offset field

◆ SPI_CR1_BIDIMODE

#define SPI_CR1_BIDIMODE   SPI_CR1_BIDIMODE_Msk

Bidirectional data mode enable

◆ SPI_CR1_BIDIMODE_Msk

#define SPI_CR1_BIDIMODE_Msk   (0x1U << SPI_CR1_BIDIMODE_Pos)

0x00008000

◆ SPI_CR1_BIDIMODE_Pos

#define SPI_CR1_BIDIMODE_Pos   (15U)

◆ SPI_CR1_BIDIOE

#define SPI_CR1_BIDIOE   SPI_CR1_BIDIOE_Msk

Output enable in bidirectional mode

◆ SPI_CR1_BIDIOE_Msk

#define SPI_CR1_BIDIOE_Msk   (0x1U << SPI_CR1_BIDIOE_Pos)

0x00004000

◆ SPI_CR1_BIDIOE_Pos

#define SPI_CR1_BIDIOE_Pos   (14U)

◆ SPI_CR1_BR

#define SPI_CR1_BR   SPI_CR1_BR_Msk

BR[2:0] bits (Baud Rate Control)

◆ SPI_CR1_BR_0

#define SPI_CR1_BR_0   (0x1U << SPI_CR1_BR_Pos)

0x00000008

◆ SPI_CR1_BR_1

#define SPI_CR1_BR_1   (0x2U << SPI_CR1_BR_Pos)

0x00000010

◆ SPI_CR1_BR_2

#define SPI_CR1_BR_2   (0x4U << SPI_CR1_BR_Pos)

0x00000020

◆ SPI_CR1_BR_Msk

#define SPI_CR1_BR_Msk   (0x7U << SPI_CR1_BR_Pos)

0x00000038

◆ SPI_CR1_BR_Pos

#define SPI_CR1_BR_Pos   (3U)

◆ SPI_CR1_CPHA

#define SPI_CR1_CPHA   SPI_CR1_CPHA_Msk

Clock Phase

◆ SPI_CR1_CPHA_Msk

#define SPI_CR1_CPHA_Msk   (0x1U << SPI_CR1_CPHA_Pos)

0x00000001

◆ SPI_CR1_CPHA_Pos

#define SPI_CR1_CPHA_Pos   (0U)

◆ SPI_CR1_CPOL

#define SPI_CR1_CPOL   SPI_CR1_CPOL_Msk

Clock Polarity

◆ SPI_CR1_CPOL_Msk

#define SPI_CR1_CPOL_Msk   (0x1U << SPI_CR1_CPOL_Pos)

0x00000002

◆ SPI_CR1_CPOL_Pos

#define SPI_CR1_CPOL_Pos   (1U)

◆ SPI_CR1_CRCEN

#define SPI_CR1_CRCEN   SPI_CR1_CRCEN_Msk

Hardware CRC calculation enable

◆ SPI_CR1_CRCEN_Msk

#define SPI_CR1_CRCEN_Msk   (0x1U << SPI_CR1_CRCEN_Pos)

0x00002000

◆ SPI_CR1_CRCEN_Pos

#define SPI_CR1_CRCEN_Pos   (13U)

◆ SPI_CR1_CRCNEXT

#define SPI_CR1_CRCNEXT   SPI_CR1_CRCNEXT_Msk

Transmit CRC next

◆ SPI_CR1_CRCNEXT_Msk

#define SPI_CR1_CRCNEXT_Msk   (0x1U << SPI_CR1_CRCNEXT_Pos)

0x00001000

◆ SPI_CR1_CRCNEXT_Pos

#define SPI_CR1_CRCNEXT_Pos   (12U)

◆ SPI_CR1_DFF

#define SPI_CR1_DFF   SPI_CR1_DFF_Msk

Data Frame Format

◆ SPI_CR1_DFF_Msk

#define SPI_CR1_DFF_Msk   (0x1U << SPI_CR1_DFF_Pos)

0x00000800

◆ SPI_CR1_DFF_Pos

#define SPI_CR1_DFF_Pos   (11U)

◆ SPI_CR1_LSBFIRST

#define SPI_CR1_LSBFIRST   SPI_CR1_LSBFIRST_Msk

Frame Format

◆ SPI_CR1_LSBFIRST_Msk

#define SPI_CR1_LSBFIRST_Msk   (0x1U << SPI_CR1_LSBFIRST_Pos)

0x00000080

◆ SPI_CR1_LSBFIRST_Pos

#define SPI_CR1_LSBFIRST_Pos   (7U)

◆ SPI_CR1_MSTR

#define SPI_CR1_MSTR   SPI_CR1_MSTR_Msk

Master Selection

◆ SPI_CR1_MSTR_Msk

#define SPI_CR1_MSTR_Msk   (0x1U << SPI_CR1_MSTR_Pos)

0x00000004

◆ SPI_CR1_MSTR_Pos

#define SPI_CR1_MSTR_Pos   (2U)

◆ SPI_CR1_RXONLY

#define SPI_CR1_RXONLY   SPI_CR1_RXONLY_Msk

Receive only

◆ SPI_CR1_RXONLY_Msk

#define SPI_CR1_RXONLY_Msk   (0x1U << SPI_CR1_RXONLY_Pos)

0x00000400

◆ SPI_CR1_RXONLY_Pos

#define SPI_CR1_RXONLY_Pos   (10U)

◆ SPI_CR1_SPE

#define SPI_CR1_SPE   SPI_CR1_SPE_Msk

SPI Enable

◆ SPI_CR1_SPE_Msk

#define SPI_CR1_SPE_Msk   (0x1U << SPI_CR1_SPE_Pos)

0x00000040

◆ SPI_CR1_SPE_Pos

#define SPI_CR1_SPE_Pos   (6U)

◆ SPI_CR1_SSI

#define SPI_CR1_SSI   SPI_CR1_SSI_Msk

Internal slave select

◆ SPI_CR1_SSI_Msk

#define SPI_CR1_SSI_Msk   (0x1U << SPI_CR1_SSI_Pos)

0x00000100

◆ SPI_CR1_SSI_Pos

#define SPI_CR1_SSI_Pos   (8U)

◆ SPI_CR1_SSM

#define SPI_CR1_SSM   SPI_CR1_SSM_Msk

Software slave management

◆ SPI_CR1_SSM_Msk

#define SPI_CR1_SSM_Msk   (0x1U << SPI_CR1_SSM_Pos)

0x00000200

◆ SPI_CR1_SSM_Pos

#define SPI_CR1_SSM_Pos   (9U)

◆ SPI_CR2_ERRIE

#define SPI_CR2_ERRIE   SPI_CR2_ERRIE_Msk

Error Interrupt Enable

◆ SPI_CR2_ERRIE_Msk

#define SPI_CR2_ERRIE_Msk   (0x1U << SPI_CR2_ERRIE_Pos)

0x00000020

◆ SPI_CR2_ERRIE_Pos

#define SPI_CR2_ERRIE_Pos   (5U)

◆ SPI_CR2_FRF

#define SPI_CR2_FRF   SPI_CR2_FRF_Msk

Frame format

◆ SPI_CR2_FRF_Msk

#define SPI_CR2_FRF_Msk   (0x1U << SPI_CR2_FRF_Pos)

0x00000010

◆ SPI_CR2_FRF_Pos

#define SPI_CR2_FRF_Pos   (4U)

◆ SPI_CR2_RXDMAEN

#define SPI_CR2_RXDMAEN   SPI_CR2_RXDMAEN_Msk

Rx Buffer DMA Enable

◆ SPI_CR2_RXDMAEN_Msk

#define SPI_CR2_RXDMAEN_Msk   (0x1U << SPI_CR2_RXDMAEN_Pos)

0x00000001

◆ SPI_CR2_RXDMAEN_Pos

#define SPI_CR2_RXDMAEN_Pos   (0U)

◆ SPI_CR2_RXNEIE

#define SPI_CR2_RXNEIE   SPI_CR2_RXNEIE_Msk

RX buffer Not Empty Interrupt Enable

◆ SPI_CR2_RXNEIE_Msk

#define SPI_CR2_RXNEIE_Msk   (0x1U << SPI_CR2_RXNEIE_Pos)

0x00000040

◆ SPI_CR2_RXNEIE_Pos

#define SPI_CR2_RXNEIE_Pos   (6U)

◆ SPI_CR2_SSOE

#define SPI_CR2_SSOE   SPI_CR2_SSOE_Msk

SS Output Enable

◆ SPI_CR2_SSOE_Msk

#define SPI_CR2_SSOE_Msk   (0x1U << SPI_CR2_SSOE_Pos)

0x00000004

◆ SPI_CR2_SSOE_Pos

#define SPI_CR2_SSOE_Pos   (2U)

◆ SPI_CR2_TXDMAEN

#define SPI_CR2_TXDMAEN   SPI_CR2_TXDMAEN_Msk

Tx Buffer DMA Enable

◆ SPI_CR2_TXDMAEN_Msk

#define SPI_CR2_TXDMAEN_Msk   (0x1U << SPI_CR2_TXDMAEN_Pos)

0x00000002

◆ SPI_CR2_TXDMAEN_Pos

#define SPI_CR2_TXDMAEN_Pos   (1U)

◆ SPI_CR2_TXEIE

#define SPI_CR2_TXEIE   SPI_CR2_TXEIE_Msk

Tx buffer Empty Interrupt Enable

◆ SPI_CR2_TXEIE_Msk

#define SPI_CR2_TXEIE_Msk   (0x1U << SPI_CR2_TXEIE_Pos)

0x00000080

◆ SPI_CR2_TXEIE_Pos

#define SPI_CR2_TXEIE_Pos   (7U)

◆ SPI_CRCPR_CRCPOLY

#define SPI_CRCPR_CRCPOLY   SPI_CRCPR_CRCPOLY_Msk

CRC polynomial register

◆ SPI_CRCPR_CRCPOLY_Msk

#define SPI_CRCPR_CRCPOLY_Msk   (0xFFFFU << SPI_CRCPR_CRCPOLY_Pos)

0x0000FFFF

◆ SPI_CRCPR_CRCPOLY_Pos

#define SPI_CRCPR_CRCPOLY_Pos   (0U)

◆ SPI_DR_DR

#define SPI_DR_DR   SPI_DR_DR_Msk

Data Register

◆ SPI_DR_DR_Msk

#define SPI_DR_DR_Msk   (0xFFFFU << SPI_DR_DR_Pos)

0x0000FFFF

◆ SPI_DR_DR_Pos

#define SPI_DR_DR_Pos   (0U)

◆ SPI_I2S_SUPPORT

#define SPI_I2S_SUPPORT

◆ SPI_I2SCFGR_CHLEN

#define SPI_I2SCFGR_CHLEN   SPI_I2SCFGR_CHLEN_Msk

Channel length (number of bits per audio channel)

◆ SPI_I2SCFGR_CHLEN_Msk

#define SPI_I2SCFGR_CHLEN_Msk   (0x1U << SPI_I2SCFGR_CHLEN_Pos)

0x00000001

◆ SPI_I2SCFGR_CHLEN_Pos

#define SPI_I2SCFGR_CHLEN_Pos   (0U)

◆ SPI_I2SCFGR_CKPOL

#define SPI_I2SCFGR_CKPOL   SPI_I2SCFGR_CKPOL_Msk

steady state clock polarity

◆ SPI_I2SCFGR_CKPOL_Msk

#define SPI_I2SCFGR_CKPOL_Msk   (0x1U << SPI_I2SCFGR_CKPOL_Pos)

0x00000008

◆ SPI_I2SCFGR_CKPOL_Pos

#define SPI_I2SCFGR_CKPOL_Pos   (3U)

◆ SPI_I2SCFGR_DATLEN

#define SPI_I2SCFGR_DATLEN   SPI_I2SCFGR_DATLEN_Msk

DATLEN[1:0] bits (Data length to be transferred)

◆ SPI_I2SCFGR_DATLEN_0

#define SPI_I2SCFGR_DATLEN_0   (0x1U << SPI_I2SCFGR_DATLEN_Pos)

0x00000002

◆ SPI_I2SCFGR_DATLEN_1

#define SPI_I2SCFGR_DATLEN_1   (0x2U << SPI_I2SCFGR_DATLEN_Pos)

0x00000004

◆ SPI_I2SCFGR_DATLEN_Msk

#define SPI_I2SCFGR_DATLEN_Msk   (0x3U << SPI_I2SCFGR_DATLEN_Pos)

0x00000006

◆ SPI_I2SCFGR_DATLEN_Pos

#define SPI_I2SCFGR_DATLEN_Pos   (1U)

◆ SPI_I2SCFGR_I2SCFG

#define SPI_I2SCFGR_I2SCFG   SPI_I2SCFGR_I2SCFG_Msk

I2SCFG[1:0] bits (I2S configuration mode)

◆ SPI_I2SCFGR_I2SCFG_0

#define SPI_I2SCFGR_I2SCFG_0   (0x1U << SPI_I2SCFGR_I2SCFG_Pos)

0x00000100

◆ SPI_I2SCFGR_I2SCFG_1

#define SPI_I2SCFGR_I2SCFG_1   (0x2U << SPI_I2SCFGR_I2SCFG_Pos)

0x00000200

◆ SPI_I2SCFGR_I2SCFG_Msk

#define SPI_I2SCFGR_I2SCFG_Msk   (0x3U << SPI_I2SCFGR_I2SCFG_Pos)

0x00000300

◆ SPI_I2SCFGR_I2SCFG_Pos

#define SPI_I2SCFGR_I2SCFG_Pos   (8U)

◆ SPI_I2SCFGR_I2SE

#define SPI_I2SCFGR_I2SE   SPI_I2SCFGR_I2SE_Msk

I2S Enable

◆ SPI_I2SCFGR_I2SE_Msk

#define SPI_I2SCFGR_I2SE_Msk   (0x1U << SPI_I2SCFGR_I2SE_Pos)

0x00000400

◆ SPI_I2SCFGR_I2SE_Pos

#define SPI_I2SCFGR_I2SE_Pos   (10U)

◆ SPI_I2SCFGR_I2SMOD

#define SPI_I2SCFGR_I2SMOD   SPI_I2SCFGR_I2SMOD_Msk

I2S mode selection

◆ SPI_I2SCFGR_I2SMOD_Msk

#define SPI_I2SCFGR_I2SMOD_Msk   (0x1U << SPI_I2SCFGR_I2SMOD_Pos)

0x00000800

◆ SPI_I2SCFGR_I2SMOD_Pos

#define SPI_I2SCFGR_I2SMOD_Pos   (11U)

◆ SPI_I2SCFGR_I2SSTD

#define SPI_I2SCFGR_I2SSTD   SPI_I2SCFGR_I2SSTD_Msk

I2SSTD[1:0] bits (I2S standard selection)

◆ SPI_I2SCFGR_I2SSTD_0

#define SPI_I2SCFGR_I2SSTD_0   (0x1U << SPI_I2SCFGR_I2SSTD_Pos)

0x00000010

◆ SPI_I2SCFGR_I2SSTD_1

#define SPI_I2SCFGR_I2SSTD_1   (0x2U << SPI_I2SCFGR_I2SSTD_Pos)

0x00000020

◆ SPI_I2SCFGR_I2SSTD_Msk

#define SPI_I2SCFGR_I2SSTD_Msk   (0x3U << SPI_I2SCFGR_I2SSTD_Pos)

0x00000030

◆ SPI_I2SCFGR_I2SSTD_Pos

#define SPI_I2SCFGR_I2SSTD_Pos   (4U)

◆ SPI_I2SCFGR_PCMSYNC

#define SPI_I2SCFGR_PCMSYNC   SPI_I2SCFGR_PCMSYNC_Msk

PCM frame synchronization

◆ SPI_I2SCFGR_PCMSYNC_Msk

#define SPI_I2SCFGR_PCMSYNC_Msk   (0x1U << SPI_I2SCFGR_PCMSYNC_Pos)

0x00000080

◆ SPI_I2SCFGR_PCMSYNC_Pos

#define SPI_I2SCFGR_PCMSYNC_Pos   (7U)

◆ SPI_I2SPR_I2SDIV

#define SPI_I2SPR_I2SDIV   SPI_I2SPR_I2SDIV_Msk

I2S Linear prescaler

◆ SPI_I2SPR_I2SDIV_Msk

#define SPI_I2SPR_I2SDIV_Msk   (0xFFU << SPI_I2SPR_I2SDIV_Pos)

0x000000FF

◆ SPI_I2SPR_I2SDIV_Pos

#define SPI_I2SPR_I2SDIV_Pos   (0U)

◆ SPI_I2SPR_MCKOE

#define SPI_I2SPR_MCKOE   SPI_I2SPR_MCKOE_Msk

Master Clock Output Enable

◆ SPI_I2SPR_MCKOE_Msk

#define SPI_I2SPR_MCKOE_Msk   (0x1U << SPI_I2SPR_MCKOE_Pos)

0x00000200

◆ SPI_I2SPR_MCKOE_Pos

#define SPI_I2SPR_MCKOE_Pos   (9U)

◆ SPI_I2SPR_ODD

#define SPI_I2SPR_ODD   SPI_I2SPR_ODD_Msk

Odd factor for the prescaler

◆ SPI_I2SPR_ODD_Msk

#define SPI_I2SPR_ODD_Msk   (0x1U << SPI_I2SPR_ODD_Pos)

0x00000100

◆ SPI_I2SPR_ODD_Pos

#define SPI_I2SPR_ODD_Pos   (8U)

◆ SPI_RXCRCR_RXCRC

#define SPI_RXCRCR_RXCRC   SPI_RXCRCR_RXCRC_Msk

Rx CRC Register

◆ SPI_RXCRCR_RXCRC_Msk

#define SPI_RXCRCR_RXCRC_Msk   (0xFFFFU << SPI_RXCRCR_RXCRC_Pos)

0x0000FFFF

◆ SPI_RXCRCR_RXCRC_Pos

#define SPI_RXCRCR_RXCRC_Pos   (0U)

◆ SPI_SR_BSY

#define SPI_SR_BSY   SPI_SR_BSY_Msk

Busy flag

◆ SPI_SR_BSY_Msk

#define SPI_SR_BSY_Msk   (0x1U << SPI_SR_BSY_Pos)

0x00000080

◆ SPI_SR_BSY_Pos

#define SPI_SR_BSY_Pos   (7U)

◆ SPI_SR_CHSIDE

#define SPI_SR_CHSIDE   SPI_SR_CHSIDE_Msk

Channel side

◆ SPI_SR_CHSIDE_Msk

#define SPI_SR_CHSIDE_Msk   (0x1U << SPI_SR_CHSIDE_Pos)

0x00000004

◆ SPI_SR_CHSIDE_Pos

#define SPI_SR_CHSIDE_Pos   (2U)

◆ SPI_SR_CRCERR

#define SPI_SR_CRCERR   SPI_SR_CRCERR_Msk

CRC Error flag

◆ SPI_SR_CRCERR_Msk

#define SPI_SR_CRCERR_Msk   (0x1U << SPI_SR_CRCERR_Pos)

0x00000010

◆ SPI_SR_CRCERR_Pos

#define SPI_SR_CRCERR_Pos   (4U)

◆ SPI_SR_FRE

#define SPI_SR_FRE   SPI_SR_FRE_Msk

Frame format error flag

◆ SPI_SR_FRE_Msk

#define SPI_SR_FRE_Msk   (0x1U << SPI_SR_FRE_Pos)

0x00000100

◆ SPI_SR_FRE_Pos

#define SPI_SR_FRE_Pos   (8U)

◆ SPI_SR_MODF

#define SPI_SR_MODF   SPI_SR_MODF_Msk

Mode fault

◆ SPI_SR_MODF_Msk

#define SPI_SR_MODF_Msk   (0x1U << SPI_SR_MODF_Pos)

0x00000020

◆ SPI_SR_MODF_Pos

#define SPI_SR_MODF_Pos   (5U)

◆ SPI_SR_OVR

#define SPI_SR_OVR   SPI_SR_OVR_Msk

Overrun flag

◆ SPI_SR_OVR_Msk

#define SPI_SR_OVR_Msk   (0x1U << SPI_SR_OVR_Pos)

0x00000040

◆ SPI_SR_OVR_Pos

#define SPI_SR_OVR_Pos   (6U)

◆ SPI_SR_RXNE

#define SPI_SR_RXNE   SPI_SR_RXNE_Msk

Receive buffer Not Empty

◆ SPI_SR_RXNE_Msk

#define SPI_SR_RXNE_Msk   (0x1U << SPI_SR_RXNE_Pos)

0x00000001

◆ SPI_SR_RXNE_Pos

#define SPI_SR_RXNE_Pos   (0U)

◆ SPI_SR_TXE

#define SPI_SR_TXE   SPI_SR_TXE_Msk

Transmit buffer Empty

◆ SPI_SR_TXE_Msk

#define SPI_SR_TXE_Msk   (0x1U << SPI_SR_TXE_Pos)

0x00000002

◆ SPI_SR_TXE_Pos

#define SPI_SR_TXE_Pos   (1U)

◆ SPI_SR_UDR

#define SPI_SR_UDR   SPI_SR_UDR_Msk

Underrun flag

◆ SPI_SR_UDR_Msk

#define SPI_SR_UDR_Msk   (0x1U << SPI_SR_UDR_Pos)

0x00000008

◆ SPI_SR_UDR_Pos

#define SPI_SR_UDR_Pos   (3U)

◆ SPI_TXCRCR_TXCRC

#define SPI_TXCRCR_TXCRC   SPI_TXCRCR_TXCRC_Msk

Tx CRC Register

◆ SPI_TXCRCR_TXCRC_Msk

#define SPI_TXCRCR_TXCRC_Msk   (0xFFFFU << SPI_TXCRCR_TXCRC_Pos)

0x0000FFFF

◆ SPI_TXCRCR_TXCRC_Pos

#define SPI_TXCRCR_TXCRC_Pos   (0U)

◆ SYSCFG_EXTICR1_EXTI0

#define SYSCFG_EXTICR1_EXTI0   SYSCFG_EXTICR1_EXTI0_Msk

EXTI 0 configuration

◆ SYSCFG_EXTICR1_EXTI0_Msk

#define SYSCFG_EXTICR1_EXTI0_Msk   (0xFU << SYSCFG_EXTICR1_EXTI0_Pos)

0x0000000F

◆ SYSCFG_EXTICR1_EXTI0_PA

#define SYSCFG_EXTICR1_EXTI0_PA   (0x00000000U)

EXTI0 configuration

PA[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PB

#define SYSCFG_EXTICR1_EXTI0_PB   (0x00000001U)

PB[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PC

#define SYSCFG_EXTICR1_EXTI0_PC   (0x00000002U)

PC[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PD

#define SYSCFG_EXTICR1_EXTI0_PD   (0x00000003U)

PD[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PE

#define SYSCFG_EXTICR1_EXTI0_PE   (0x00000004U)

PE[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PF

#define SYSCFG_EXTICR1_EXTI0_PF   (0x00000006U)

PF[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PG

#define SYSCFG_EXTICR1_EXTI0_PG   (0x00000007U)

PG[0] pin

◆ SYSCFG_EXTICR1_EXTI0_PH

#define SYSCFG_EXTICR1_EXTI0_PH   (0x00000005U)

PH[0] pin

◆ SYSCFG_EXTICR1_EXTI0_Pos

#define SYSCFG_EXTICR1_EXTI0_Pos   (0U)

◆ SYSCFG_EXTICR1_EXTI1

#define SYSCFG_EXTICR1_EXTI1   SYSCFG_EXTICR1_EXTI1_Msk

EXTI 1 configuration

◆ SYSCFG_EXTICR1_EXTI1_Msk

#define SYSCFG_EXTICR1_EXTI1_Msk   (0xFU << SYSCFG_EXTICR1_EXTI1_Pos)

0x000000F0

◆ SYSCFG_EXTICR1_EXTI1_PA

#define SYSCFG_EXTICR1_EXTI1_PA   (0x00000000U)

EXTI1 configuration

PA[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PB

#define SYSCFG_EXTICR1_EXTI1_PB   (0x00000010U)

PB[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PC

#define SYSCFG_EXTICR1_EXTI1_PC   (0x00000020U)

PC[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PD

#define SYSCFG_EXTICR1_EXTI1_PD   (0x00000030U)

PD[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PE

#define SYSCFG_EXTICR1_EXTI1_PE   (0x00000040U)

PE[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PF

#define SYSCFG_EXTICR1_EXTI1_PF   (0x00000060U)

PF[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PG

#define SYSCFG_EXTICR1_EXTI1_PG   (0x00000070U)

PG[1] pin

◆ SYSCFG_EXTICR1_EXTI1_PH

#define SYSCFG_EXTICR1_EXTI1_PH   (0x00000050U)

PH[1] pin

◆ SYSCFG_EXTICR1_EXTI1_Pos

#define SYSCFG_EXTICR1_EXTI1_Pos   (4U)

◆ SYSCFG_EXTICR1_EXTI2

#define SYSCFG_EXTICR1_EXTI2   SYSCFG_EXTICR1_EXTI2_Msk

EXTI 2 configuration

◆ SYSCFG_EXTICR1_EXTI2_Msk

#define SYSCFG_EXTICR1_EXTI2_Msk   (0xFU << SYSCFG_EXTICR1_EXTI2_Pos)

0x00000F00

◆ SYSCFG_EXTICR1_EXTI2_PA

#define SYSCFG_EXTICR1_EXTI2_PA   (0x00000000U)

EXTI2 configuration

PA[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PB

#define SYSCFG_EXTICR1_EXTI2_PB   (0x00000100U)

PB[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PC

#define SYSCFG_EXTICR1_EXTI2_PC   (0x00000200U)

PC[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PD

#define SYSCFG_EXTICR1_EXTI2_PD   (0x00000300U)

PD[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PE

#define SYSCFG_EXTICR1_EXTI2_PE   (0x00000400U)

PE[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PF

#define SYSCFG_EXTICR1_EXTI2_PF   (0x00000600U)

PF[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PG

#define SYSCFG_EXTICR1_EXTI2_PG   (0x00000700U)

PG[2] pin

◆ SYSCFG_EXTICR1_EXTI2_PH

#define SYSCFG_EXTICR1_EXTI2_PH   (0x00000500U)

PH[2] pin

◆ SYSCFG_EXTICR1_EXTI2_Pos

#define SYSCFG_EXTICR1_EXTI2_Pos   (8U)

◆ SYSCFG_EXTICR1_EXTI3

#define SYSCFG_EXTICR1_EXTI3   SYSCFG_EXTICR1_EXTI3_Msk

EXTI 3 configuration

◆ SYSCFG_EXTICR1_EXTI3_Msk

#define SYSCFG_EXTICR1_EXTI3_Msk   (0xFU << SYSCFG_EXTICR1_EXTI3_Pos)

0x0000F000

◆ SYSCFG_EXTICR1_EXTI3_PA

#define SYSCFG_EXTICR1_EXTI3_PA   (0x00000000U)

EXTI3 configuration

PA[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PB

#define SYSCFG_EXTICR1_EXTI3_PB   (0x00001000U)

PB[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PC

#define SYSCFG_EXTICR1_EXTI3_PC   (0x00002000U)

PC[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PD

#define SYSCFG_EXTICR1_EXTI3_PD   (0x00003000U)

PD[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PE

#define SYSCFG_EXTICR1_EXTI3_PE   (0x00004000U)

PE[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PF

#define SYSCFG_EXTICR1_EXTI3_PF   (0x00003000U)

PF[3] pin

◆ SYSCFG_EXTICR1_EXTI3_PG

#define SYSCFG_EXTICR1_EXTI3_PG   (0x00004000U)

PG[3] pin

◆ SYSCFG_EXTICR1_EXTI3_Pos

#define SYSCFG_EXTICR1_EXTI3_Pos   (12U)

◆ SYSCFG_EXTICR2_EXTI4

#define SYSCFG_EXTICR2_EXTI4   SYSCFG_EXTICR2_EXTI4_Msk

EXTI 4 configuration

◆ SYSCFG_EXTICR2_EXTI4_Msk

#define SYSCFG_EXTICR2_EXTI4_Msk   (0xFU << SYSCFG_EXTICR2_EXTI4_Pos)

0x0000000F

◆ SYSCFG_EXTICR2_EXTI4_PA

#define SYSCFG_EXTICR2_EXTI4_PA   (0x00000000U)

EXTI4 configuration

PA[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PB

#define SYSCFG_EXTICR2_EXTI4_PB   (0x00000001U)

PB[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PC

#define SYSCFG_EXTICR2_EXTI4_PC   (0x00000002U)

PC[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PD

#define SYSCFG_EXTICR2_EXTI4_PD   (0x00000003U)

PD[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PE

#define SYSCFG_EXTICR2_EXTI4_PE   (0x00000004U)

PE[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PF

#define SYSCFG_EXTICR2_EXTI4_PF   (0x00000006U)

PF[4] pin

◆ SYSCFG_EXTICR2_EXTI4_PG

#define SYSCFG_EXTICR2_EXTI4_PG   (0x00000007U)

PG[4] pin

◆ SYSCFG_EXTICR2_EXTI4_Pos

#define SYSCFG_EXTICR2_EXTI4_Pos   (0U)

◆ SYSCFG_EXTICR2_EXTI5

#define SYSCFG_EXTICR2_EXTI5   SYSCFG_EXTICR2_EXTI5_Msk

EXTI 5 configuration

◆ SYSCFG_EXTICR2_EXTI5_Msk

#define SYSCFG_EXTICR2_EXTI5_Msk   (0xFU << SYSCFG_EXTICR2_EXTI5_Pos)

0x000000F0

◆ SYSCFG_EXTICR2_EXTI5_PA

#define SYSCFG_EXTICR2_EXTI5_PA   (0x00000000U)

EXTI5 configuration

PA[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PB

#define SYSCFG_EXTICR2_EXTI5_PB   (0x00000010U)

PB[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PC

#define SYSCFG_EXTICR2_EXTI5_PC   (0x00000020U)

PC[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PD

#define SYSCFG_EXTICR2_EXTI5_PD   (0x00000030U)

PD[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PE

#define SYSCFG_EXTICR2_EXTI5_PE   (0x00000040U)

PE[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PF

#define SYSCFG_EXTICR2_EXTI5_PF   (0x00000060U)

PF[5] pin

◆ SYSCFG_EXTICR2_EXTI5_PG

#define SYSCFG_EXTICR2_EXTI5_PG   (0x00000070U)

PG[5] pin

◆ SYSCFG_EXTICR2_EXTI5_Pos

#define SYSCFG_EXTICR2_EXTI5_Pos   (4U)

◆ SYSCFG_EXTICR2_EXTI6

#define SYSCFG_EXTICR2_EXTI6   SYSCFG_EXTICR2_EXTI6_Msk

EXTI 6 configuration

◆ SYSCFG_EXTICR2_EXTI6_Msk

#define SYSCFG_EXTICR2_EXTI6_Msk   (0xFU << SYSCFG_EXTICR2_EXTI6_Pos)

0x00000F00

◆ SYSCFG_EXTICR2_EXTI6_PA

#define SYSCFG_EXTICR2_EXTI6_PA   (0x00000000U)

EXTI6 configuration

PA[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PB

#define SYSCFG_EXTICR2_EXTI6_PB   (0x00000100U)

PB[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PC

#define SYSCFG_EXTICR2_EXTI6_PC   (0x00000200U)

PC[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PD

#define SYSCFG_EXTICR2_EXTI6_PD   (0x00000300U)

PD[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PE

#define SYSCFG_EXTICR2_EXTI6_PE   (0x00000400U)

PE[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PF

#define SYSCFG_EXTICR2_EXTI6_PF   (0x00000600U)

PF[6] pin

◆ SYSCFG_EXTICR2_EXTI6_PG

#define SYSCFG_EXTICR2_EXTI6_PG   (0x00000700U)

PG[6] pin

◆ SYSCFG_EXTICR2_EXTI6_Pos

#define SYSCFG_EXTICR2_EXTI6_Pos   (8U)

◆ SYSCFG_EXTICR2_EXTI7

#define SYSCFG_EXTICR2_EXTI7   SYSCFG_EXTICR2_EXTI7_Msk

EXTI 7 configuration

◆ SYSCFG_EXTICR2_EXTI7_Msk

#define SYSCFG_EXTICR2_EXTI7_Msk   (0xFU << SYSCFG_EXTICR2_EXTI7_Pos)

0x0000F000

◆ SYSCFG_EXTICR2_EXTI7_PA

#define SYSCFG_EXTICR2_EXTI7_PA   (0x00000000U)

EXTI7 configuration

PA[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PB

#define SYSCFG_EXTICR2_EXTI7_PB   (0x00001000U)

PB[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PC

#define SYSCFG_EXTICR2_EXTI7_PC   (0x00002000U)

PC[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PD

#define SYSCFG_EXTICR2_EXTI7_PD   (0x00003000U)

PD[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PE

#define SYSCFG_EXTICR2_EXTI7_PE   (0x00004000U)

PE[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PF

#define SYSCFG_EXTICR2_EXTI7_PF   (0x00006000U)

PF[7] pin

◆ SYSCFG_EXTICR2_EXTI7_PG

#define SYSCFG_EXTICR2_EXTI7_PG   (0x00007000U)

PG[7] pin

◆ SYSCFG_EXTICR2_EXTI7_Pos

#define SYSCFG_EXTICR2_EXTI7_Pos   (12U)

◆ SYSCFG_EXTICR3_EXTI10

#define SYSCFG_EXTICR3_EXTI10   SYSCFG_EXTICR3_EXTI10_Msk

EXTI 10 configuration

◆ SYSCFG_EXTICR3_EXTI10_Msk

#define SYSCFG_EXTICR3_EXTI10_Msk   (0xFU << SYSCFG_EXTICR3_EXTI10_Pos)

0x00000F00

◆ SYSCFG_EXTICR3_EXTI10_PA

#define SYSCFG_EXTICR3_EXTI10_PA   (0x00000000U)

EXTI10 configuration

PA[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PB

#define SYSCFG_EXTICR3_EXTI10_PB   (0x00000100U)

PB[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PC

#define SYSCFG_EXTICR3_EXTI10_PC   (0x00000200U)

PC[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PD

#define SYSCFG_EXTICR3_EXTI10_PD   (0x00000300U)

PD[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PE

#define SYSCFG_EXTICR3_EXTI10_PE   (0x00000400U)

PE[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PF

#define SYSCFG_EXTICR3_EXTI10_PF   (0x00000600U)

PF[10] pin

◆ SYSCFG_EXTICR3_EXTI10_PG

#define SYSCFG_EXTICR3_EXTI10_PG   (0x00000700U)

PG[10] pin

◆ SYSCFG_EXTICR3_EXTI10_Pos

#define SYSCFG_EXTICR3_EXTI10_Pos   (8U)

◆ SYSCFG_EXTICR3_EXTI11

#define SYSCFG_EXTICR3_EXTI11   SYSCFG_EXTICR3_EXTI11_Msk

EXTI 11 configuration

◆ SYSCFG_EXTICR3_EXTI11_Msk

#define SYSCFG_EXTICR3_EXTI11_Msk   (0xFU << SYSCFG_EXTICR3_EXTI11_Pos)

0x0000F000

◆ SYSCFG_EXTICR3_EXTI11_PA

#define SYSCFG_EXTICR3_EXTI11_PA   (0x00000000U)

EXTI11 configuration

PA[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PB

#define SYSCFG_EXTICR3_EXTI11_PB   (0x00001000U)

PB[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PC

#define SYSCFG_EXTICR3_EXTI11_PC   (0x00002000U)

PC[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PD

#define SYSCFG_EXTICR3_EXTI11_PD   (0x00003000U)

PD[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PE

#define SYSCFG_EXTICR3_EXTI11_PE   (0x00004000U)

PE[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PF

#define SYSCFG_EXTICR3_EXTI11_PF   (0x00006000U)

PF[11] pin

◆ SYSCFG_EXTICR3_EXTI11_PG

#define SYSCFG_EXTICR3_EXTI11_PG   (0x00007000U)

PG[11] pin

◆ SYSCFG_EXTICR3_EXTI11_Pos

#define SYSCFG_EXTICR3_EXTI11_Pos   (12U)

◆ SYSCFG_EXTICR3_EXTI8

#define SYSCFG_EXTICR3_EXTI8   SYSCFG_EXTICR3_EXTI8_Msk

EXTI 8 configuration

◆ SYSCFG_EXTICR3_EXTI8_Msk

#define SYSCFG_EXTICR3_EXTI8_Msk   (0xFU << SYSCFG_EXTICR3_EXTI8_Pos)

0x0000000F

◆ SYSCFG_EXTICR3_EXTI8_PA

#define SYSCFG_EXTICR3_EXTI8_PA   (0x00000000U)

EXTI8 configuration

PA[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PB

#define SYSCFG_EXTICR3_EXTI8_PB   (0x00000001U)

PB[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PC

#define SYSCFG_EXTICR3_EXTI8_PC   (0x00000002U)

PC[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PD

#define SYSCFG_EXTICR3_EXTI8_PD   (0x00000003U)

PD[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PE

#define SYSCFG_EXTICR3_EXTI8_PE   (0x00000004U)

PE[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PF

#define SYSCFG_EXTICR3_EXTI8_PF   (0x00000006U)

PF[8] pin

◆ SYSCFG_EXTICR3_EXTI8_PG

#define SYSCFG_EXTICR3_EXTI8_PG   (0x00000007U)

PG[8] pin

◆ SYSCFG_EXTICR3_EXTI8_Pos

#define SYSCFG_EXTICR3_EXTI8_Pos   (0U)

◆ SYSCFG_EXTICR3_EXTI9

#define SYSCFG_EXTICR3_EXTI9   SYSCFG_EXTICR3_EXTI9_Msk

EXTI 9 configuration

◆ SYSCFG_EXTICR3_EXTI9_Msk

#define SYSCFG_EXTICR3_EXTI9_Msk   (0xFU << SYSCFG_EXTICR3_EXTI9_Pos)

0x000000F0

◆ SYSCFG_EXTICR3_EXTI9_PA

#define SYSCFG_EXTICR3_EXTI9_PA   (0x00000000U)

EXTI9 configuration

PA[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PB

#define SYSCFG_EXTICR3_EXTI9_PB   (0x00000010U)

PB[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PC

#define SYSCFG_EXTICR3_EXTI9_PC   (0x00000020U)

PC[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PD

#define SYSCFG_EXTICR3_EXTI9_PD   (0x00000030U)

PD[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PE

#define SYSCFG_EXTICR3_EXTI9_PE   (0x00000040U)

PE[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PF

#define SYSCFG_EXTICR3_EXTI9_PF   (0x00000060U)

PF[9] pin

◆ SYSCFG_EXTICR3_EXTI9_PG

#define SYSCFG_EXTICR3_EXTI9_PG   (0x00000070U)

PG[9] pin

◆ SYSCFG_EXTICR3_EXTI9_Pos

#define SYSCFG_EXTICR3_EXTI9_Pos   (4U)

◆ SYSCFG_EXTICR4_EXTI12

#define SYSCFG_EXTICR4_EXTI12   SYSCFG_EXTICR4_EXTI12_Msk

EXTI 12 configuration

◆ SYSCFG_EXTICR4_EXTI12_Msk

#define SYSCFG_EXTICR4_EXTI12_Msk   (0xFU << SYSCFG_EXTICR4_EXTI12_Pos)

0x0000000F

◆ SYSCFG_EXTICR4_EXTI12_PA

#define SYSCFG_EXTICR4_EXTI12_PA   (0x00000000U)

EXTI12 configuration

PA[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PB

#define SYSCFG_EXTICR4_EXTI12_PB   (0x00000001U)

PB[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PC

#define SYSCFG_EXTICR4_EXTI12_PC   (0x00000002U)

PC[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PD

#define SYSCFG_EXTICR4_EXTI12_PD   (0x00000003U)

PD[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PE

#define SYSCFG_EXTICR4_EXTI12_PE   (0x00000004U)

PE[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PF

#define SYSCFG_EXTICR4_EXTI12_PF   (0x00000006U)

PF[12] pin

◆ SYSCFG_EXTICR4_EXTI12_PG

#define SYSCFG_EXTICR4_EXTI12_PG   (0x00000007U)

PG[12] pin

◆ SYSCFG_EXTICR4_EXTI12_Pos

#define SYSCFG_EXTICR4_EXTI12_Pos   (0U)

◆ SYSCFG_EXTICR4_EXTI13

#define SYSCFG_EXTICR4_EXTI13   SYSCFG_EXTICR4_EXTI13_Msk

EXTI 13 configuration

◆ SYSCFG_EXTICR4_EXTI13_Msk

#define SYSCFG_EXTICR4_EXTI13_Msk   (0xFU << SYSCFG_EXTICR4_EXTI13_Pos)

0x000000F0

◆ SYSCFG_EXTICR4_EXTI13_PA

#define SYSCFG_EXTICR4_EXTI13_PA   (0x00000000U)

EXTI13 configuration

PA[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PB

#define SYSCFG_EXTICR4_EXTI13_PB   (0x00000010U)

PB[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PC

#define SYSCFG_EXTICR4_EXTI13_PC   (0x00000020U)

PC[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PD

#define SYSCFG_EXTICR4_EXTI13_PD   (0x00000030U)

PD[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PE

#define SYSCFG_EXTICR4_EXTI13_PE   (0x00000040U)

PE[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PF

#define SYSCFG_EXTICR4_EXTI13_PF   (0x00000060U)

PF[13] pin

◆ SYSCFG_EXTICR4_EXTI13_PG

#define SYSCFG_EXTICR4_EXTI13_PG   (0x00000070U)

PG[13] pin

◆ SYSCFG_EXTICR4_EXTI13_Pos

#define SYSCFG_EXTICR4_EXTI13_Pos   (4U)

◆ SYSCFG_EXTICR4_EXTI14

#define SYSCFG_EXTICR4_EXTI14   SYSCFG_EXTICR4_EXTI14_Msk

EXTI 14 configuration

◆ SYSCFG_EXTICR4_EXTI14_Msk

#define SYSCFG_EXTICR4_EXTI14_Msk   (0xFU << SYSCFG_EXTICR4_EXTI14_Pos)

0x00000F00

◆ SYSCFG_EXTICR4_EXTI14_PA

#define SYSCFG_EXTICR4_EXTI14_PA   (0x00000000U)

EXTI14 configuration

PA[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PB

#define SYSCFG_EXTICR4_EXTI14_PB   (0x00000100U)

PB[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PC

#define SYSCFG_EXTICR4_EXTI14_PC   (0x00000200U)

PC[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PD

#define SYSCFG_EXTICR4_EXTI14_PD   (0x00000300U)

PD[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PE

#define SYSCFG_EXTICR4_EXTI14_PE   (0x00000400U)

PE[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PF

#define SYSCFG_EXTICR4_EXTI14_PF   (0x00000600U)

PF[14] pin

◆ SYSCFG_EXTICR4_EXTI14_PG

#define SYSCFG_EXTICR4_EXTI14_PG   (0x00000700U)

PG[14] pin

◆ SYSCFG_EXTICR4_EXTI14_Pos

#define SYSCFG_EXTICR4_EXTI14_Pos   (8U)

◆ SYSCFG_EXTICR4_EXTI15

#define SYSCFG_EXTICR4_EXTI15   SYSCFG_EXTICR4_EXTI15_Msk

EXTI 15 configuration

◆ SYSCFG_EXTICR4_EXTI15_Msk

#define SYSCFG_EXTICR4_EXTI15_Msk   (0xFU << SYSCFG_EXTICR4_EXTI15_Pos)

0x0000F000

◆ SYSCFG_EXTICR4_EXTI15_PA

#define SYSCFG_EXTICR4_EXTI15_PA   (0x00000000U)

EXTI15 configuration

PA[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PB

#define SYSCFG_EXTICR4_EXTI15_PB   (0x00001000U)

PB[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PC

#define SYSCFG_EXTICR4_EXTI15_PC   (0x00002000U)

PC[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PD

#define SYSCFG_EXTICR4_EXTI15_PD   (0x00003000U)

PD[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PE

#define SYSCFG_EXTICR4_EXTI15_PE   (0x00004000U)

PE[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PF

#define SYSCFG_EXTICR4_EXTI15_PF   (0x00006000U)

PF[15] pin

◆ SYSCFG_EXTICR4_EXTI15_PG

#define SYSCFG_EXTICR4_EXTI15_PG   (0x00007000U)

PG[15] pin

◆ SYSCFG_EXTICR4_EXTI15_Pos

#define SYSCFG_EXTICR4_EXTI15_Pos   (12U)

◆ SYSCFG_MEMRMP_BOOT_MODE

#define SYSCFG_MEMRMP_BOOT_MODE   SYSCFG_MEMRMP_BOOT_MODE_Msk

Boot mode Config

◆ SYSCFG_MEMRMP_BOOT_MODE_0

#define SYSCFG_MEMRMP_BOOT_MODE_0   (0x1U << SYSCFG_MEMRMP_BOOT_MODE_Pos)

0x00000100

◆ SYSCFG_MEMRMP_BOOT_MODE_1

#define SYSCFG_MEMRMP_BOOT_MODE_1   (0x2U << SYSCFG_MEMRMP_BOOT_MODE_Pos)

0x00000200

◆ SYSCFG_MEMRMP_BOOT_MODE_Msk

#define SYSCFG_MEMRMP_BOOT_MODE_Msk   (0x3U << SYSCFG_MEMRMP_BOOT_MODE_Pos)

0x00000300

◆ SYSCFG_MEMRMP_BOOT_MODE_Pos

#define SYSCFG_MEMRMP_BOOT_MODE_Pos   (8U)

◆ SYSCFG_MEMRMP_MEM_MODE

#define SYSCFG_MEMRMP_MEM_MODE   SYSCFG_MEMRMP_MEM_MODE_Msk

SYSCFG_Memory Remap Config

◆ SYSCFG_MEMRMP_MEM_MODE_0

#define SYSCFG_MEMRMP_MEM_MODE_0   (0x1U << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000001

◆ SYSCFG_MEMRMP_MEM_MODE_1

#define SYSCFG_MEMRMP_MEM_MODE_1   (0x2U << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000002

◆ SYSCFG_MEMRMP_MEM_MODE_Msk

#define SYSCFG_MEMRMP_MEM_MODE_Msk   (0x3U << SYSCFG_MEMRMP_MEM_MODE_Pos)

0x00000003

◆ SYSCFG_MEMRMP_MEM_MODE_Pos

#define SYSCFG_MEMRMP_MEM_MODE_Pos   (0U)

◆ SYSCFG_PMC_LCD_CAPA

#define SYSCFG_PMC_LCD_CAPA   SYSCFG_PMC_LCD_CAPA_Msk

LCD_CAPA decoupling capacitance connection

◆ SYSCFG_PMC_LCD_CAPA_0

#define SYSCFG_PMC_LCD_CAPA_0   (0x01U << SYSCFG_PMC_LCD_CAPA_Pos)

0x00000002

◆ SYSCFG_PMC_LCD_CAPA_1

#define SYSCFG_PMC_LCD_CAPA_1   (0x02U << SYSCFG_PMC_LCD_CAPA_Pos)

0x00000004

◆ SYSCFG_PMC_LCD_CAPA_2

#define SYSCFG_PMC_LCD_CAPA_2   (0x04U << SYSCFG_PMC_LCD_CAPA_Pos)

0x00000008

◆ SYSCFG_PMC_LCD_CAPA_3

#define SYSCFG_PMC_LCD_CAPA_3   (0x08U << SYSCFG_PMC_LCD_CAPA_Pos)

0x00000010

◆ SYSCFG_PMC_LCD_CAPA_4

#define SYSCFG_PMC_LCD_CAPA_4   (0x10U << SYSCFG_PMC_LCD_CAPA_Pos)

0x00000020

◆ SYSCFG_PMC_LCD_CAPA_Msk

#define SYSCFG_PMC_LCD_CAPA_Msk   (0x1FU << SYSCFG_PMC_LCD_CAPA_Pos)

0x0000003E

◆ SYSCFG_PMC_LCD_CAPA_Pos

#define SYSCFG_PMC_LCD_CAPA_Pos   (1U)

◆ SYSCFG_PMC_USB_PU

#define SYSCFG_PMC_USB_PU   SYSCFG_PMC_USB_PU_Msk

SYSCFG PMC

◆ SYSCFG_PMC_USB_PU_Msk

#define SYSCFG_PMC_USB_PU_Msk   (0x1U << SYSCFG_PMC_USB_PU_Pos)

0x00000001

◆ SYSCFG_PMC_USB_PU_Pos

#define SYSCFG_PMC_USB_PU_Pos   (0U)

◆ SysTick_CALIB_NOREF

#define SysTick_CALIB_NOREF   (0x80000000U)

The reference clock is not provided

◆ SysTick_CALIB_SKEW

#define SysTick_CALIB_SKEW   (0x40000000U)

Calibration value is not exactly 10 ms

◆ SysTick_CALIB_TENMS

#define SysTick_CALIB_TENMS   (0x00FFFFFFU)

Reload value to use for 10ms timing

◆ SysTick_CTRL_CLKSOURCE

#define SysTick_CTRL_CLKSOURCE   (0x00000004U)

Clock source

◆ SysTick_CTRL_COUNTFLAG

#define SysTick_CTRL_COUNTFLAG   (0x00010000U)

Count Flag

◆ SysTick_CTRL_ENABLE

#define SysTick_CTRL_ENABLE   (0x00000001U)

Counter enable

◆ SysTick_CTRL_TICKINT

#define SysTick_CTRL_TICKINT   (0x00000002U)

Counting down to 0 pends the SysTick handler

◆ SysTick_LOAD_RELOAD

#define SysTick_LOAD_RELOAD   (0x00FFFFFFU)

Value to load into the SysTick Current Value Register when the counter reaches 0

◆ SysTick_VAL_CURRENT

#define SysTick_VAL_CURRENT   (0x00FFFFFFU)

Current value at the time the register is accessed

◆ TIM2_OR_ITR1_RMP

#define TIM2_OR_ITR1_RMP   TIM2_OR_ITR1_RMP_Msk

ITR1_RMP bit (TIM2 Internal trigger 1 remap)

◆ TIM2_OR_ITR1_RMP_Msk

#define TIM2_OR_ITR1_RMP_Msk   (0x1U << TIM2_OR_ITR1_RMP_Pos)

0x00000001

◆ TIM2_OR_ITR1_RMP_Pos

#define TIM2_OR_ITR1_RMP_Pos   (0U)

◆ TIM3_OR_ITR2_RMP

#define TIM3_OR_ITR2_RMP   TIM3_OR_ITR2_RMP_Msk

ITR2_RMP bit (TIM3 Internal trigger 2 remap)

◆ TIM3_OR_ITR2_RMP_Msk

#define TIM3_OR_ITR2_RMP_Msk   (0x1U << TIM3_OR_ITR2_RMP_Pos)

0x00000001

◆ TIM3_OR_ITR2_RMP_Pos

#define TIM3_OR_ITR2_RMP_Pos   (0U)

◆ TIM9_OR_ITR1_RMP

#define TIM9_OR_ITR1_RMP   TIM9_OR_ITR1_RMP_Msk

ITR1_RMP bit (TIM9 Internal trigger 1 remap)

◆ TIM9_OR_ITR1_RMP_Msk

#define TIM9_OR_ITR1_RMP_Msk   (0x1U << TIM9_OR_ITR1_RMP_Pos)

0x00000004

◆ TIM9_OR_ITR1_RMP_Pos

#define TIM9_OR_ITR1_RMP_Pos   (2U)

◆ TIM_ARR_ARR

#define TIM_ARR_ARR   TIM_ARR_ARR_Msk

actual auto-reload Value

◆ TIM_ARR_ARR_Msk

#define TIM_ARR_ARR_Msk   (0xFFFFFFFFU << TIM_ARR_ARR_Pos)

0xFFFFFFFF

◆ TIM_ARR_ARR_Pos

#define TIM_ARR_ARR_Pos   (0U)

◆ TIM_CCER_CC1E

#define TIM_CCER_CC1E   TIM_CCER_CC1E_Msk

Capture/Compare 1 output enable

◆ TIM_CCER_CC1E_Msk

#define TIM_CCER_CC1E_Msk   (0x1U << TIM_CCER_CC1E_Pos)

0x00000001

◆ TIM_CCER_CC1E_Pos

#define TIM_CCER_CC1E_Pos   (0U)

◆ TIM_CCER_CC1NP

#define TIM_CCER_CC1NP   TIM_CCER_CC1NP_Msk

Capture/Compare 1 Complementary output Polarity

◆ TIM_CCER_CC1NP_Msk

#define TIM_CCER_CC1NP_Msk   (0x1U << TIM_CCER_CC1NP_Pos)

0x00000008

◆ TIM_CCER_CC1NP_Pos

#define TIM_CCER_CC1NP_Pos   (3U)

◆ TIM_CCER_CC1P

#define TIM_CCER_CC1P   TIM_CCER_CC1P_Msk

Capture/Compare 1 output Polarity

◆ TIM_CCER_CC1P_Msk

#define TIM_CCER_CC1P_Msk   (0x1U << TIM_CCER_CC1P_Pos)

0x00000002

◆ TIM_CCER_CC1P_Pos

#define TIM_CCER_CC1P_Pos   (1U)

◆ TIM_CCER_CC2E

#define TIM_CCER_CC2E   TIM_CCER_CC2E_Msk

Capture/Compare 2 output enable

◆ TIM_CCER_CC2E_Msk

#define TIM_CCER_CC2E_Msk   (0x1U << TIM_CCER_CC2E_Pos)

0x00000010

◆ TIM_CCER_CC2E_Pos

#define TIM_CCER_CC2E_Pos   (4U)

◆ TIM_CCER_CC2NP

#define TIM_CCER_CC2NP   TIM_CCER_CC2NP_Msk

Capture/Compare 2 Complementary output Polarity

◆ TIM_CCER_CC2NP_Msk

#define TIM_CCER_CC2NP_Msk   (0x1U << TIM_CCER_CC2NP_Pos)

0x00000080

◆ TIM_CCER_CC2NP_Pos

#define TIM_CCER_CC2NP_Pos   (7U)

◆ TIM_CCER_CC2P

#define TIM_CCER_CC2P   TIM_CCER_CC2P_Msk

Capture/Compare 2 output Polarity

◆ TIM_CCER_CC2P_Msk

#define TIM_CCER_CC2P_Msk   (0x1U << TIM_CCER_CC2P_Pos)

0x00000020

◆ TIM_CCER_CC2P_Pos

#define TIM_CCER_CC2P_Pos   (5U)

◆ TIM_CCER_CC3E

#define TIM_CCER_CC3E   TIM_CCER_CC3E_Msk

Capture/Compare 3 output enable

◆ TIM_CCER_CC3E_Msk

#define TIM_CCER_CC3E_Msk   (0x1U << TIM_CCER_CC3E_Pos)

0x00000100

◆ TIM_CCER_CC3E_Pos

#define TIM_CCER_CC3E_Pos   (8U)

◆ TIM_CCER_CC3NP

#define TIM_CCER_CC3NP   TIM_CCER_CC3NP_Msk

Capture/Compare 3 Complementary output Polarity

◆ TIM_CCER_CC3NP_Msk

#define TIM_CCER_CC3NP_Msk   (0x1U << TIM_CCER_CC3NP_Pos)

0x00000800

◆ TIM_CCER_CC3NP_Pos

#define TIM_CCER_CC3NP_Pos   (11U)

◆ TIM_CCER_CC3P

#define TIM_CCER_CC3P   TIM_CCER_CC3P_Msk

Capture/Compare 3 output Polarity

◆ TIM_CCER_CC3P_Msk

#define TIM_CCER_CC3P_Msk   (0x1U << TIM_CCER_CC3P_Pos)

0x00000200

◆ TIM_CCER_CC3P_Pos

#define TIM_CCER_CC3P_Pos   (9U)

◆ TIM_CCER_CC4E

#define TIM_CCER_CC4E   TIM_CCER_CC4E_Msk

Capture/Compare 4 output enable

◆ TIM_CCER_CC4E_Msk

#define TIM_CCER_CC4E_Msk   (0x1U << TIM_CCER_CC4E_Pos)

0x00001000

◆ TIM_CCER_CC4E_Pos

#define TIM_CCER_CC4E_Pos   (12U)

◆ TIM_CCER_CC4NP

#define TIM_CCER_CC4NP   TIM_CCER_CC4NP_Msk

Capture/Compare 4 Complementary output Polarity

◆ TIM_CCER_CC4NP_Msk

#define TIM_CCER_CC4NP_Msk   (0x1U << TIM_CCER_CC4NP_Pos)

0x00008000

◆ TIM_CCER_CC4NP_Pos

#define TIM_CCER_CC4NP_Pos   (15U)

◆ TIM_CCER_CC4P

#define TIM_CCER_CC4P   TIM_CCER_CC4P_Msk

Capture/Compare 4 output Polarity

◆ TIM_CCER_CC4P_Msk

#define TIM_CCER_CC4P_Msk   (0x1U << TIM_CCER_CC4P_Pos)

0x00002000

◆ TIM_CCER_CC4P_Pos

#define TIM_CCER_CC4P_Pos   (13U)

◆ TIM_CCMR1_CC1S

#define TIM_CCMR1_CC1S   TIM_CCMR1_CC1S_Msk

CC1S[1:0] bits (Capture/Compare 1 Selection)

◆ TIM_CCMR1_CC1S_0

#define TIM_CCMR1_CC1S_0   (0x1U << TIM_CCMR1_CC1S_Pos)

0x00000001

◆ TIM_CCMR1_CC1S_1

#define TIM_CCMR1_CC1S_1   (0x2U << TIM_CCMR1_CC1S_Pos)

0x00000002

◆ TIM_CCMR1_CC1S_Msk

#define TIM_CCMR1_CC1S_Msk   (0x3U << TIM_CCMR1_CC1S_Pos)

0x00000003

◆ TIM_CCMR1_CC1S_Pos

#define TIM_CCMR1_CC1S_Pos   (0U)

◆ TIM_CCMR1_CC2S

#define TIM_CCMR1_CC2S   TIM_CCMR1_CC2S_Msk

CC2S[1:0] bits (Capture/Compare 2 Selection)

◆ TIM_CCMR1_CC2S_0

#define TIM_CCMR1_CC2S_0   (0x1U << TIM_CCMR1_CC2S_Pos)

0x00000100

◆ TIM_CCMR1_CC2S_1

#define TIM_CCMR1_CC2S_1   (0x2U << TIM_CCMR1_CC2S_Pos)

0x00000200

◆ TIM_CCMR1_CC2S_Msk

#define TIM_CCMR1_CC2S_Msk   (0x3U << TIM_CCMR1_CC2S_Pos)

0x00000300

◆ TIM_CCMR1_CC2S_Pos

#define TIM_CCMR1_CC2S_Pos   (8U)

◆ TIM_CCMR1_IC1F

#define TIM_CCMR1_IC1F   TIM_CCMR1_IC1F_Msk

IC1F[3:0] bits (Input Capture 1 Filter)

◆ TIM_CCMR1_IC1F_0

#define TIM_CCMR1_IC1F_0   (0x1U << TIM_CCMR1_IC1F_Pos)

0x00000010

◆ TIM_CCMR1_IC1F_1

#define TIM_CCMR1_IC1F_1   (0x2U << TIM_CCMR1_IC1F_Pos)

0x00000020

◆ TIM_CCMR1_IC1F_2

#define TIM_CCMR1_IC1F_2   (0x4U << TIM_CCMR1_IC1F_Pos)

0x00000040

◆ TIM_CCMR1_IC1F_3

#define TIM_CCMR1_IC1F_3   (0x8U << TIM_CCMR1_IC1F_Pos)

0x00000080

◆ TIM_CCMR1_IC1F_Msk

#define TIM_CCMR1_IC1F_Msk   (0xFU << TIM_CCMR1_IC1F_Pos)

0x000000F0

◆ TIM_CCMR1_IC1F_Pos

#define TIM_CCMR1_IC1F_Pos   (4U)

◆ TIM_CCMR1_IC1PSC

#define TIM_CCMR1_IC1PSC   TIM_CCMR1_IC1PSC_Msk

IC1PSC[1:0] bits (Input Capture 1 Prescaler)

◆ TIM_CCMR1_IC1PSC_0

#define TIM_CCMR1_IC1PSC_0   (0x1U << TIM_CCMR1_IC1PSC_Pos)

0x00000004

◆ TIM_CCMR1_IC1PSC_1

#define TIM_CCMR1_IC1PSC_1   (0x2U << TIM_CCMR1_IC1PSC_Pos)

0x00000008

◆ TIM_CCMR1_IC1PSC_Msk

#define TIM_CCMR1_IC1PSC_Msk   (0x3U << TIM_CCMR1_IC1PSC_Pos)

0x0000000C

◆ TIM_CCMR1_IC1PSC_Pos

#define TIM_CCMR1_IC1PSC_Pos   (2U)

◆ TIM_CCMR1_IC2F

#define TIM_CCMR1_IC2F   TIM_CCMR1_IC2F_Msk

IC2F[3:0] bits (Input Capture 2 Filter)

◆ TIM_CCMR1_IC2F_0

#define TIM_CCMR1_IC2F_0   (0x1U << TIM_CCMR1_IC2F_Pos)

0x00001000

◆ TIM_CCMR1_IC2F_1

#define TIM_CCMR1_IC2F_1   (0x2U << TIM_CCMR1_IC2F_Pos)

0x00002000

◆ TIM_CCMR1_IC2F_2

#define TIM_CCMR1_IC2F_2   (0x4U << TIM_CCMR1_IC2F_Pos)

0x00004000

◆ TIM_CCMR1_IC2F_3

#define TIM_CCMR1_IC2F_3   (0x8U << TIM_CCMR1_IC2F_Pos)

0x00008000

◆ TIM_CCMR1_IC2F_Msk

#define TIM_CCMR1_IC2F_Msk   (0xFU << TIM_CCMR1_IC2F_Pos)

0x0000F000

◆ TIM_CCMR1_IC2F_Pos

#define TIM_CCMR1_IC2F_Pos   (12U)

◆ TIM_CCMR1_IC2PSC

#define TIM_CCMR1_IC2PSC   TIM_CCMR1_IC2PSC_Msk

IC2PSC[1:0] bits (Input Capture 2 Prescaler)

◆ TIM_CCMR1_IC2PSC_0

#define TIM_CCMR1_IC2PSC_0   (0x1U << TIM_CCMR1_IC2PSC_Pos)

0x00000400

◆ TIM_CCMR1_IC2PSC_1

#define TIM_CCMR1_IC2PSC_1   (0x2U << TIM_CCMR1_IC2PSC_Pos)

0x00000800

◆ TIM_CCMR1_IC2PSC_Msk

#define TIM_CCMR1_IC2PSC_Msk   (0x3U << TIM_CCMR1_IC2PSC_Pos)

0x00000C00

◆ TIM_CCMR1_IC2PSC_Pos

#define TIM_CCMR1_IC2PSC_Pos   (10U)

◆ TIM_CCMR1_OC1CE

#define TIM_CCMR1_OC1CE   TIM_CCMR1_OC1CE_Msk

Output Compare 1Clear Enable

◆ TIM_CCMR1_OC1CE_Msk

#define TIM_CCMR1_OC1CE_Msk   (0x1U << TIM_CCMR1_OC1CE_Pos)

0x00000080

◆ TIM_CCMR1_OC1CE_Pos

#define TIM_CCMR1_OC1CE_Pos   (7U)

◆ TIM_CCMR1_OC1FE

#define TIM_CCMR1_OC1FE   TIM_CCMR1_OC1FE_Msk

Output Compare 1 Fast enable

◆ TIM_CCMR1_OC1FE_Msk

#define TIM_CCMR1_OC1FE_Msk   (0x1U << TIM_CCMR1_OC1FE_Pos)

0x00000004

◆ TIM_CCMR1_OC1FE_Pos

#define TIM_CCMR1_OC1FE_Pos   (2U)

◆ TIM_CCMR1_OC1M

#define TIM_CCMR1_OC1M   TIM_CCMR1_OC1M_Msk

OC1M[2:0] bits (Output Compare 1 Mode)

◆ TIM_CCMR1_OC1M_0

#define TIM_CCMR1_OC1M_0   (0x1U << TIM_CCMR1_OC1M_Pos)

0x00000010

◆ TIM_CCMR1_OC1M_1

#define TIM_CCMR1_OC1M_1   (0x2U << TIM_CCMR1_OC1M_Pos)

0x00000020

◆ TIM_CCMR1_OC1M_2

#define TIM_CCMR1_OC1M_2   (0x4U << TIM_CCMR1_OC1M_Pos)

0x00000040

◆ TIM_CCMR1_OC1M_Msk

#define TIM_CCMR1_OC1M_Msk   (0x7U << TIM_CCMR1_OC1M_Pos)

0x00000070

◆ TIM_CCMR1_OC1M_Pos

#define TIM_CCMR1_OC1M_Pos   (4U)

◆ TIM_CCMR1_OC1PE

#define TIM_CCMR1_OC1PE   TIM_CCMR1_OC1PE_Msk

Output Compare 1 Preload enable

◆ TIM_CCMR1_OC1PE_Msk

#define TIM_CCMR1_OC1PE_Msk   (0x1U << TIM_CCMR1_OC1PE_Pos)

0x00000008

◆ TIM_CCMR1_OC1PE_Pos

#define TIM_CCMR1_OC1PE_Pos   (3U)

◆ TIM_CCMR1_OC2CE

#define TIM_CCMR1_OC2CE   TIM_CCMR1_OC2CE_Msk

Output Compare 2 Clear Enable

◆ TIM_CCMR1_OC2CE_Msk

#define TIM_CCMR1_OC2CE_Msk   (0x1U << TIM_CCMR1_OC2CE_Pos)

0x00008000

◆ TIM_CCMR1_OC2CE_Pos

#define TIM_CCMR1_OC2CE_Pos   (15U)

◆ TIM_CCMR1_OC2FE

#define TIM_CCMR1_OC2FE   TIM_CCMR1_OC2FE_Msk

Output Compare 2 Fast enable

◆ TIM_CCMR1_OC2FE_Msk

#define TIM_CCMR1_OC2FE_Msk   (0x1U << TIM_CCMR1_OC2FE_Pos)

0x00000400

◆ TIM_CCMR1_OC2FE_Pos

#define TIM_CCMR1_OC2FE_Pos   (10U)

◆ TIM_CCMR1_OC2M

#define TIM_CCMR1_OC2M   TIM_CCMR1_OC2M_Msk

OC2M[2:0] bits (Output Compare 2 Mode)

◆ TIM_CCMR1_OC2M_0

#define TIM_CCMR1_OC2M_0   (0x1U << TIM_CCMR1_OC2M_Pos)

0x00001000

◆ TIM_CCMR1_OC2M_1

#define TIM_CCMR1_OC2M_1   (0x2U << TIM_CCMR1_OC2M_Pos)

0x00002000

◆ TIM_CCMR1_OC2M_2

#define TIM_CCMR1_OC2M_2   (0x4U << TIM_CCMR1_OC2M_Pos)

0x00004000

◆ TIM_CCMR1_OC2M_Msk

#define TIM_CCMR1_OC2M_Msk   (0x7U << TIM_CCMR1_OC2M_Pos)

0x00007000

◆ TIM_CCMR1_OC2M_Pos

#define TIM_CCMR1_OC2M_Pos   (12U)

◆ TIM_CCMR1_OC2PE

#define TIM_CCMR1_OC2PE   TIM_CCMR1_OC2PE_Msk

Output Compare 2 Preload enable

◆ TIM_CCMR1_OC2PE_Msk

#define TIM_CCMR1_OC2PE_Msk   (0x1U << TIM_CCMR1_OC2PE_Pos)

0x00000800

◆ TIM_CCMR1_OC2PE_Pos

#define TIM_CCMR1_OC2PE_Pos   (11U)

◆ TIM_CCMR2_CC3S

#define TIM_CCMR2_CC3S   TIM_CCMR2_CC3S_Msk

CC3S[1:0] bits (Capture/Compare 3 Selection)

◆ TIM_CCMR2_CC3S_0

#define TIM_CCMR2_CC3S_0   (0x1U << TIM_CCMR2_CC3S_Pos)

0x00000001

◆ TIM_CCMR2_CC3S_1

#define TIM_CCMR2_CC3S_1   (0x2U << TIM_CCMR2_CC3S_Pos)

0x00000002

◆ TIM_CCMR2_CC3S_Msk

#define TIM_CCMR2_CC3S_Msk   (0x3U << TIM_CCMR2_CC3S_Pos)

0x00000003

◆ TIM_CCMR2_CC3S_Pos

#define TIM_CCMR2_CC3S_Pos   (0U)

◆ TIM_CCMR2_CC4S

#define TIM_CCMR2_CC4S   TIM_CCMR2_CC4S_Msk

CC4S[1:0] bits (Capture/Compare 4 Selection)

◆ TIM_CCMR2_CC4S_0

#define TIM_CCMR2_CC4S_0   (0x1U << TIM_CCMR2_CC4S_Pos)

0x00000100

◆ TIM_CCMR2_CC4S_1

#define TIM_CCMR2_CC4S_1   (0x2U << TIM_CCMR2_CC4S_Pos)

0x00000200

◆ TIM_CCMR2_CC4S_Msk

#define TIM_CCMR2_CC4S_Msk   (0x3U << TIM_CCMR2_CC4S_Pos)

0x00000300

◆ TIM_CCMR2_CC4S_Pos

#define TIM_CCMR2_CC4S_Pos   (8U)

◆ TIM_CCMR2_IC3F

#define TIM_CCMR2_IC3F   TIM_CCMR2_IC3F_Msk

IC3F[3:0] bits (Input Capture 3 Filter)

◆ TIM_CCMR2_IC3F_0

#define TIM_CCMR2_IC3F_0   (0x1U << TIM_CCMR2_IC3F_Pos)

0x00000010

◆ TIM_CCMR2_IC3F_1

#define TIM_CCMR2_IC3F_1   (0x2U << TIM_CCMR2_IC3F_Pos)

0x00000020

◆ TIM_CCMR2_IC3F_2

#define TIM_CCMR2_IC3F_2   (0x4U << TIM_CCMR2_IC3F_Pos)

0x00000040

◆ TIM_CCMR2_IC3F_3

#define TIM_CCMR2_IC3F_3   (0x8U << TIM_CCMR2_IC3F_Pos)

0x00000080

◆ TIM_CCMR2_IC3F_Msk

#define TIM_CCMR2_IC3F_Msk   (0xFU << TIM_CCMR2_IC3F_Pos)

0x000000F0

◆ TIM_CCMR2_IC3F_Pos

#define TIM_CCMR2_IC3F_Pos   (4U)

◆ TIM_CCMR2_IC3PSC

#define TIM_CCMR2_IC3PSC   TIM_CCMR2_IC3PSC_Msk

IC3PSC[1:0] bits (Input Capture 3 Prescaler)

◆ TIM_CCMR2_IC3PSC_0

#define TIM_CCMR2_IC3PSC_0   (0x1U << TIM_CCMR2_IC3PSC_Pos)

0x00000004

◆ TIM_CCMR2_IC3PSC_1

#define TIM_CCMR2_IC3PSC_1   (0x2U << TIM_CCMR2_IC3PSC_Pos)

0x00000008

◆ TIM_CCMR2_IC3PSC_Msk

#define TIM_CCMR2_IC3PSC_Msk   (0x3U << TIM_CCMR2_IC3PSC_Pos)

0x0000000C

◆ TIM_CCMR2_IC3PSC_Pos

#define TIM_CCMR2_IC3PSC_Pos   (2U)

◆ TIM_CCMR2_IC4F

#define TIM_CCMR2_IC4F   TIM_CCMR2_IC4F_Msk

IC4F[3:0] bits (Input Capture 4 Filter)

◆ TIM_CCMR2_IC4F_0

#define TIM_CCMR2_IC4F_0   (0x1U << TIM_CCMR2_IC4F_Pos)

0x00001000

◆ TIM_CCMR2_IC4F_1

#define TIM_CCMR2_IC4F_1   (0x2U << TIM_CCMR2_IC4F_Pos)

0x00002000

◆ TIM_CCMR2_IC4F_2

#define TIM_CCMR2_IC4F_2   (0x4U << TIM_CCMR2_IC4F_Pos)

0x00004000

◆ TIM_CCMR2_IC4F_3

#define TIM_CCMR2_IC4F_3   (0x8U << TIM_CCMR2_IC4F_Pos)

0x00008000

◆ TIM_CCMR2_IC4F_Msk

#define TIM_CCMR2_IC4F_Msk   (0xFU << TIM_CCMR2_IC4F_Pos)

0x0000F000

◆ TIM_CCMR2_IC4F_Pos

#define TIM_CCMR2_IC4F_Pos   (12U)

◆ TIM_CCMR2_IC4PSC

#define TIM_CCMR2_IC4PSC   TIM_CCMR2_IC4PSC_Msk

IC4PSC[1:0] bits (Input Capture 4 Prescaler)

◆ TIM_CCMR2_IC4PSC_0

#define TIM_CCMR2_IC4PSC_0   (0x1U << TIM_CCMR2_IC4PSC_Pos)

0x00000400

◆ TIM_CCMR2_IC4PSC_1

#define TIM_CCMR2_IC4PSC_1   (0x2U << TIM_CCMR2_IC4PSC_Pos)

0x00000800

◆ TIM_CCMR2_IC4PSC_Msk

#define TIM_CCMR2_IC4PSC_Msk   (0x3U << TIM_CCMR2_IC4PSC_Pos)

0x00000C00

◆ TIM_CCMR2_IC4PSC_Pos

#define TIM_CCMR2_IC4PSC_Pos   (10U)

◆ TIM_CCMR2_OC3CE

#define TIM_CCMR2_OC3CE   TIM_CCMR2_OC3CE_Msk

Output Compare 3 Clear Enable

◆ TIM_CCMR2_OC3CE_Msk

#define TIM_CCMR2_OC3CE_Msk   (0x1U << TIM_CCMR2_OC3CE_Pos)

0x00000080

◆ TIM_CCMR2_OC3CE_Pos

#define TIM_CCMR2_OC3CE_Pos   (7U)

◆ TIM_CCMR2_OC3FE

#define TIM_CCMR2_OC3FE   TIM_CCMR2_OC3FE_Msk

Output Compare 3 Fast enable

◆ TIM_CCMR2_OC3FE_Msk

#define TIM_CCMR2_OC3FE_Msk   (0x1U << TIM_CCMR2_OC3FE_Pos)

0x00000004

◆ TIM_CCMR2_OC3FE_Pos

#define TIM_CCMR2_OC3FE_Pos   (2U)

◆ TIM_CCMR2_OC3M

#define TIM_CCMR2_OC3M   TIM_CCMR2_OC3M_Msk

OC3M[2:0] bits (Output Compare 3 Mode)

◆ TIM_CCMR2_OC3M_0

#define TIM_CCMR2_OC3M_0   (0x1U << TIM_CCMR2_OC3M_Pos)

0x00000010

◆ TIM_CCMR2_OC3M_1

#define TIM_CCMR2_OC3M_1   (0x2U << TIM_CCMR2_OC3M_Pos)

0x00000020

◆ TIM_CCMR2_OC3M_2

#define TIM_CCMR2_OC3M_2   (0x4U << TIM_CCMR2_OC3M_Pos)

0x00000040

◆ TIM_CCMR2_OC3M_Msk

#define TIM_CCMR2_OC3M_Msk   (0x7U << TIM_CCMR2_OC3M_Pos)

0x00000070

◆ TIM_CCMR2_OC3M_Pos

#define TIM_CCMR2_OC3M_Pos   (4U)

◆ TIM_CCMR2_OC3PE

#define TIM_CCMR2_OC3PE   TIM_CCMR2_OC3PE_Msk

Output Compare 3 Preload enable

◆ TIM_CCMR2_OC3PE_Msk

#define TIM_CCMR2_OC3PE_Msk   (0x1U << TIM_CCMR2_OC3PE_Pos)

0x00000008

◆ TIM_CCMR2_OC3PE_Pos

#define TIM_CCMR2_OC3PE_Pos   (3U)

◆ TIM_CCMR2_OC4CE

#define TIM_CCMR2_OC4CE   TIM_CCMR2_OC4CE_Msk

Output Compare 4 Clear Enable

◆ TIM_CCMR2_OC4CE_Msk

#define TIM_CCMR2_OC4CE_Msk   (0x1U << TIM_CCMR2_OC4CE_Pos)

0x00008000

◆ TIM_CCMR2_OC4CE_Pos

#define TIM_CCMR2_OC4CE_Pos   (15U)

◆ TIM_CCMR2_OC4FE

#define TIM_CCMR2_OC4FE   TIM_CCMR2_OC4FE_Msk

Output Compare 4 Fast enable

◆ TIM_CCMR2_OC4FE_Msk

#define TIM_CCMR2_OC4FE_Msk   (0x1U << TIM_CCMR2_OC4FE_Pos)

0x00000400

◆ TIM_CCMR2_OC4FE_Pos

#define TIM_CCMR2_OC4FE_Pos   (10U)

◆ TIM_CCMR2_OC4M

#define TIM_CCMR2_OC4M   TIM_CCMR2_OC4M_Msk

OC4M[2:0] bits (Output Compare 4 Mode)

◆ TIM_CCMR2_OC4M_0

#define TIM_CCMR2_OC4M_0   (0x1U << TIM_CCMR2_OC4M_Pos)

0x00001000

◆ TIM_CCMR2_OC4M_1

#define TIM_CCMR2_OC4M_1   (0x2U << TIM_CCMR2_OC4M_Pos)

0x00002000

◆ TIM_CCMR2_OC4M_2

#define TIM_CCMR2_OC4M_2   (0x4U << TIM_CCMR2_OC4M_Pos)

0x00004000

◆ TIM_CCMR2_OC4M_Msk

#define TIM_CCMR2_OC4M_Msk   (0x7U << TIM_CCMR2_OC4M_Pos)

0x00007000

◆ TIM_CCMR2_OC4M_Pos

#define TIM_CCMR2_OC4M_Pos   (12U)

◆ TIM_CCMR2_OC4PE

#define TIM_CCMR2_OC4PE   TIM_CCMR2_OC4PE_Msk

Output Compare 4 Preload enable

◆ TIM_CCMR2_OC4PE_Msk

#define TIM_CCMR2_OC4PE_Msk   (0x1U << TIM_CCMR2_OC4PE_Pos)

0x00000800

◆ TIM_CCMR2_OC4PE_Pos

#define TIM_CCMR2_OC4PE_Pos   (11U)

◆ TIM_CCR1_CCR1

#define TIM_CCR1_CCR1   TIM_CCR1_CCR1_Msk

Capture/Compare 1 Value

◆ TIM_CCR1_CCR1_Msk

#define TIM_CCR1_CCR1_Msk   (0xFFFFU << TIM_CCR1_CCR1_Pos)

0x0000FFFF

◆ TIM_CCR1_CCR1_Pos

#define TIM_CCR1_CCR1_Pos   (0U)

◆ TIM_CCR2_CCR2

#define TIM_CCR2_CCR2   TIM_CCR2_CCR2_Msk

Capture/Compare 2 Value

◆ TIM_CCR2_CCR2_Msk

#define TIM_CCR2_CCR2_Msk   (0xFFFFU << TIM_CCR2_CCR2_Pos)

0x0000FFFF

◆ TIM_CCR2_CCR2_Pos

#define TIM_CCR2_CCR2_Pos   (0U)

◆ TIM_CCR3_CCR3

#define TIM_CCR3_CCR3   TIM_CCR3_CCR3_Msk

Capture/Compare 3 Value

◆ TIM_CCR3_CCR3_Msk

#define TIM_CCR3_CCR3_Msk   (0xFFFFU << TIM_CCR3_CCR3_Pos)

0x0000FFFF

◆ TIM_CCR3_CCR3_Pos

#define TIM_CCR3_CCR3_Pos   (0U)

◆ TIM_CCR4_CCR4

#define TIM_CCR4_CCR4   TIM_CCR4_CCR4_Msk

Capture/Compare 4 Value

◆ TIM_CCR4_CCR4_Msk

#define TIM_CCR4_CCR4_Msk   (0xFFFFU << TIM_CCR4_CCR4_Pos)

0x0000FFFF

◆ TIM_CCR4_CCR4_Pos

#define TIM_CCR4_CCR4_Pos   (0U)

◆ TIM_CNT_CNT

#define TIM_CNT_CNT   TIM_CNT_CNT_Msk

Counter Value

◆ TIM_CNT_CNT_Msk

#define TIM_CNT_CNT_Msk   (0xFFFFFFFFU << TIM_CNT_CNT_Pos)

0xFFFFFFFF

◆ TIM_CNT_CNT_Pos

#define TIM_CNT_CNT_Pos   (0U)

◆ TIM_CR1_ARPE

#define TIM_CR1_ARPE   TIM_CR1_ARPE_Msk

Auto-reload preload enable

◆ TIM_CR1_ARPE_Msk

#define TIM_CR1_ARPE_Msk   (0x1U << TIM_CR1_ARPE_Pos)

0x00000080

◆ TIM_CR1_ARPE_Pos

#define TIM_CR1_ARPE_Pos   (7U)

◆ TIM_CR1_CEN

#define TIM_CR1_CEN   TIM_CR1_CEN_Msk

Counter enable

◆ TIM_CR1_CEN_Msk

#define TIM_CR1_CEN_Msk   (0x1U << TIM_CR1_CEN_Pos)

0x00000001

◆ TIM_CR1_CEN_Pos

#define TIM_CR1_CEN_Pos   (0U)

◆ TIM_CR1_CKD

#define TIM_CR1_CKD   TIM_CR1_CKD_Msk

CKD[1:0] bits (clock division)

◆ TIM_CR1_CKD_0

#define TIM_CR1_CKD_0   (0x1U << TIM_CR1_CKD_Pos)

0x00000100

◆ TIM_CR1_CKD_1

#define TIM_CR1_CKD_1   (0x2U << TIM_CR1_CKD_Pos)

0x00000200

◆ TIM_CR1_CKD_Msk

#define TIM_CR1_CKD_Msk   (0x3U << TIM_CR1_CKD_Pos)

0x00000300

◆ TIM_CR1_CKD_Pos

#define TIM_CR1_CKD_Pos   (8U)

◆ TIM_CR1_CMS

#define TIM_CR1_CMS   TIM_CR1_CMS_Msk

CMS[1:0] bits (Center-aligned mode selection)

◆ TIM_CR1_CMS_0

#define TIM_CR1_CMS_0   (0x1U << TIM_CR1_CMS_Pos)

0x00000020

◆ TIM_CR1_CMS_1

#define TIM_CR1_CMS_1   (0x2U << TIM_CR1_CMS_Pos)

0x00000040

◆ TIM_CR1_CMS_Msk

#define TIM_CR1_CMS_Msk   (0x3U << TIM_CR1_CMS_Pos)

0x00000060

◆ TIM_CR1_CMS_Pos

#define TIM_CR1_CMS_Pos   (5U)

◆ TIM_CR1_DIR

#define TIM_CR1_DIR   TIM_CR1_DIR_Msk

Direction

◆ TIM_CR1_DIR_Msk

#define TIM_CR1_DIR_Msk   (0x1U << TIM_CR1_DIR_Pos)

0x00000010

◆ TIM_CR1_DIR_Pos

#define TIM_CR1_DIR_Pos   (4U)

◆ TIM_CR1_OPM

#define TIM_CR1_OPM   TIM_CR1_OPM_Msk

One pulse mode

◆ TIM_CR1_OPM_Msk

#define TIM_CR1_OPM_Msk   (0x1U << TIM_CR1_OPM_Pos)

0x00000008

◆ TIM_CR1_OPM_Pos

#define TIM_CR1_OPM_Pos   (3U)

◆ TIM_CR1_UDIS

#define TIM_CR1_UDIS   TIM_CR1_UDIS_Msk

Update disable

◆ TIM_CR1_UDIS_Msk

#define TIM_CR1_UDIS_Msk   (0x1U << TIM_CR1_UDIS_Pos)

0x00000002

◆ TIM_CR1_UDIS_Pos

#define TIM_CR1_UDIS_Pos   (1U)

◆ TIM_CR1_URS

#define TIM_CR1_URS   TIM_CR1_URS_Msk

Update request source

◆ TIM_CR1_URS_Msk

#define TIM_CR1_URS_Msk   (0x1U << TIM_CR1_URS_Pos)

0x00000004

◆ TIM_CR1_URS_Pos

#define TIM_CR1_URS_Pos   (2U)

◆ TIM_CR2_CCDS

#define TIM_CR2_CCDS   TIM_CR2_CCDS_Msk

Capture/Compare DMA Selection

◆ TIM_CR2_CCDS_Msk

#define TIM_CR2_CCDS_Msk   (0x1U << TIM_CR2_CCDS_Pos)

0x00000008

◆ TIM_CR2_CCDS_Pos

#define TIM_CR2_CCDS_Pos   (3U)

◆ TIM_CR2_MMS

#define TIM_CR2_MMS   TIM_CR2_MMS_Msk

MMS[2:0] bits (Master Mode Selection)

◆ TIM_CR2_MMS_0

#define TIM_CR2_MMS_0   (0x1U << TIM_CR2_MMS_Pos)

0x00000010

◆ TIM_CR2_MMS_1

#define TIM_CR2_MMS_1   (0x2U << TIM_CR2_MMS_Pos)

0x00000020

◆ TIM_CR2_MMS_2

#define TIM_CR2_MMS_2   (0x4U << TIM_CR2_MMS_Pos)

0x00000040

◆ TIM_CR2_MMS_Msk

#define TIM_CR2_MMS_Msk   (0x7U << TIM_CR2_MMS_Pos)

0x00000070

◆ TIM_CR2_MMS_Pos

#define TIM_CR2_MMS_Pos   (4U)

◆ TIM_CR2_TI1S

#define TIM_CR2_TI1S   TIM_CR2_TI1S_Msk

TI1 Selection

◆ TIM_CR2_TI1S_Msk

#define TIM_CR2_TI1S_Msk   (0x1U << TIM_CR2_TI1S_Pos)

0x00000080

◆ TIM_CR2_TI1S_Pos

#define TIM_CR2_TI1S_Pos   (7U)

◆ TIM_DCR_DBA

#define TIM_DCR_DBA   TIM_DCR_DBA_Msk

DBA[4:0] bits (DMA Base Address)

◆ TIM_DCR_DBA_0

#define TIM_DCR_DBA_0   (0x01U << TIM_DCR_DBA_Pos)

0x00000001

◆ TIM_DCR_DBA_1

#define TIM_DCR_DBA_1   (0x02U << TIM_DCR_DBA_Pos)

0x00000002

◆ TIM_DCR_DBA_2

#define TIM_DCR_DBA_2   (0x04U << TIM_DCR_DBA_Pos)

0x00000004

◆ TIM_DCR_DBA_3

#define TIM_DCR_DBA_3   (0x08U << TIM_DCR_DBA_Pos)

0x00000008

◆ TIM_DCR_DBA_4

#define TIM_DCR_DBA_4   (0x10U << TIM_DCR_DBA_Pos)

0x00000010

◆ TIM_DCR_DBA_Msk

#define TIM_DCR_DBA_Msk   (0x1FU << TIM_DCR_DBA_Pos)

0x0000001F

◆ TIM_DCR_DBA_Pos

#define TIM_DCR_DBA_Pos   (0U)

◆ TIM_DCR_DBL

#define TIM_DCR_DBL   TIM_DCR_DBL_Msk

DBL[4:0] bits (DMA Burst Length)

◆ TIM_DCR_DBL_0

#define TIM_DCR_DBL_0   (0x01U << TIM_DCR_DBL_Pos)

0x00000100

◆ TIM_DCR_DBL_1

#define TIM_DCR_DBL_1   (0x02U << TIM_DCR_DBL_Pos)

0x00000200

◆ TIM_DCR_DBL_2

#define TIM_DCR_DBL_2   (0x04U << TIM_DCR_DBL_Pos)

0x00000400

◆ TIM_DCR_DBL_3

#define TIM_DCR_DBL_3   (0x08U << TIM_DCR_DBL_Pos)

0x00000800

◆ TIM_DCR_DBL_4

#define TIM_DCR_DBL_4   (0x10U << TIM_DCR_DBL_Pos)

0x00001000

◆ TIM_DCR_DBL_Msk

#define TIM_DCR_DBL_Msk   (0x1FU << TIM_DCR_DBL_Pos)

0x00001F00

◆ TIM_DCR_DBL_Pos

#define TIM_DCR_DBL_Pos   (8U)

◆ TIM_DIER_CC1DE

#define TIM_DIER_CC1DE   TIM_DIER_CC1DE_Msk

Capture/Compare 1 DMA request enable

◆ TIM_DIER_CC1DE_Msk

#define TIM_DIER_CC1DE_Msk   (0x1U << TIM_DIER_CC1DE_Pos)

0x00000200

◆ TIM_DIER_CC1DE_Pos

#define TIM_DIER_CC1DE_Pos   (9U)

◆ TIM_DIER_CC1IE

#define TIM_DIER_CC1IE   TIM_DIER_CC1IE_Msk

Capture/Compare 1 interrupt enable

◆ TIM_DIER_CC1IE_Msk

#define TIM_DIER_CC1IE_Msk   (0x1U << TIM_DIER_CC1IE_Pos)

0x00000002

◆ TIM_DIER_CC1IE_Pos

#define TIM_DIER_CC1IE_Pos   (1U)

◆ TIM_DIER_CC2DE

#define TIM_DIER_CC2DE   TIM_DIER_CC2DE_Msk

Capture/Compare 2 DMA request enable

◆ TIM_DIER_CC2DE_Msk

#define TIM_DIER_CC2DE_Msk   (0x1U << TIM_DIER_CC2DE_Pos)

0x00000400

◆ TIM_DIER_CC2DE_Pos

#define TIM_DIER_CC2DE_Pos   (10U)

◆ TIM_DIER_CC2IE

#define TIM_DIER_CC2IE   TIM_DIER_CC2IE_Msk

Capture/Compare 2 interrupt enable

◆ TIM_DIER_CC2IE_Msk

#define TIM_DIER_CC2IE_Msk   (0x1U << TIM_DIER_CC2IE_Pos)

0x00000004

◆ TIM_DIER_CC2IE_Pos

#define TIM_DIER_CC2IE_Pos   (2U)

◆ TIM_DIER_CC3DE

#define TIM_DIER_CC3DE   TIM_DIER_CC3DE_Msk

Capture/Compare 3 DMA request enable

◆ TIM_DIER_CC3DE_Msk

#define TIM_DIER_CC3DE_Msk   (0x1U << TIM_DIER_CC3DE_Pos)

0x00000800

◆ TIM_DIER_CC3DE_Pos

#define TIM_DIER_CC3DE_Pos   (11U)

◆ TIM_DIER_CC3IE

#define TIM_DIER_CC3IE   TIM_DIER_CC3IE_Msk

Capture/Compare 3 interrupt enable

◆ TIM_DIER_CC3IE_Msk

#define TIM_DIER_CC3IE_Msk   (0x1U << TIM_DIER_CC3IE_Pos)

0x00000008

◆ TIM_DIER_CC3IE_Pos

#define TIM_DIER_CC3IE_Pos   (3U)

◆ TIM_DIER_CC4DE

#define TIM_DIER_CC4DE   TIM_DIER_CC4DE_Msk

Capture/Compare 4 DMA request enable

◆ TIM_DIER_CC4DE_Msk

#define TIM_DIER_CC4DE_Msk   (0x1U << TIM_DIER_CC4DE_Pos)

0x00001000

◆ TIM_DIER_CC4DE_Pos

#define TIM_DIER_CC4DE_Pos   (12U)

◆ TIM_DIER_CC4IE

#define TIM_DIER_CC4IE   TIM_DIER_CC4IE_Msk

Capture/Compare 4 interrupt enable

◆ TIM_DIER_CC4IE_Msk

#define TIM_DIER_CC4IE_Msk   (0x1U << TIM_DIER_CC4IE_Pos)

0x00000010

◆ TIM_DIER_CC4IE_Pos

#define TIM_DIER_CC4IE_Pos   (4U)

◆ TIM_DIER_COMDE

#define TIM_DIER_COMDE   ((uint16_t)0x2000U)

COM DMA request enable

◆ TIM_DIER_TDE

#define TIM_DIER_TDE   TIM_DIER_TDE_Msk

Trigger DMA request enable

◆ TIM_DIER_TDE_Msk

#define TIM_DIER_TDE_Msk   (0x1U << TIM_DIER_TDE_Pos)

0x00004000

◆ TIM_DIER_TDE_Pos

#define TIM_DIER_TDE_Pos   (14U)

◆ TIM_DIER_TIE

#define TIM_DIER_TIE   TIM_DIER_TIE_Msk

Trigger interrupt enable

◆ TIM_DIER_TIE_Msk

#define TIM_DIER_TIE_Msk   (0x1U << TIM_DIER_TIE_Pos)

0x00000040

◆ TIM_DIER_TIE_Pos

#define TIM_DIER_TIE_Pos   (6U)

◆ TIM_DIER_UDE

#define TIM_DIER_UDE   TIM_DIER_UDE_Msk

Update DMA request enable

◆ TIM_DIER_UDE_Msk

#define TIM_DIER_UDE_Msk   (0x1U << TIM_DIER_UDE_Pos)

0x00000100

◆ TIM_DIER_UDE_Pos

#define TIM_DIER_UDE_Pos   (8U)

◆ TIM_DIER_UIE

#define TIM_DIER_UIE   TIM_DIER_UIE_Msk

Update interrupt enable

◆ TIM_DIER_UIE_Msk

#define TIM_DIER_UIE_Msk   (0x1U << TIM_DIER_UIE_Pos)

0x00000001

◆ TIM_DIER_UIE_Pos

#define TIM_DIER_UIE_Pos   (0U)

◆ TIM_DMAR_DMAB

#define TIM_DMAR_DMAB   TIM_DMAR_DMAB_Msk

DMA register for burst accesses

◆ TIM_DMAR_DMAB_Msk

#define TIM_DMAR_DMAB_Msk   (0xFFFFU << TIM_DMAR_DMAB_Pos)

0x0000FFFF

◆ TIM_DMAR_DMAB_Pos

#define TIM_DMAR_DMAB_Pos   (0U)

◆ TIM_EGR_CC1G

#define TIM_EGR_CC1G   TIM_EGR_CC1G_Msk

Capture/Compare 1 Generation

◆ TIM_EGR_CC1G_Msk

#define TIM_EGR_CC1G_Msk   (0x1U << TIM_EGR_CC1G_Pos)

0x00000002

◆ TIM_EGR_CC1G_Pos

#define TIM_EGR_CC1G_Pos   (1U)

◆ TIM_EGR_CC2G

#define TIM_EGR_CC2G   TIM_EGR_CC2G_Msk

Capture/Compare 2 Generation

◆ TIM_EGR_CC2G_Msk

#define TIM_EGR_CC2G_Msk   (0x1U << TIM_EGR_CC2G_Pos)

0x00000004

◆ TIM_EGR_CC2G_Pos

#define TIM_EGR_CC2G_Pos   (2U)

◆ TIM_EGR_CC3G

#define TIM_EGR_CC3G   TIM_EGR_CC3G_Msk

Capture/Compare 3 Generation

◆ TIM_EGR_CC3G_Msk

#define TIM_EGR_CC3G_Msk   (0x1U << TIM_EGR_CC3G_Pos)

0x00000008

◆ TIM_EGR_CC3G_Pos

#define TIM_EGR_CC3G_Pos   (3U)

◆ TIM_EGR_CC4G

#define TIM_EGR_CC4G   TIM_EGR_CC4G_Msk

Capture/Compare 4 Generation

◆ TIM_EGR_CC4G_Msk

#define TIM_EGR_CC4G_Msk   (0x1U << TIM_EGR_CC4G_Pos)

0x00000010

◆ TIM_EGR_CC4G_Pos

#define TIM_EGR_CC4G_Pos   (4U)

◆ TIM_EGR_TG

#define TIM_EGR_TG   TIM_EGR_TG_Msk

Trigger Generation

◆ TIM_EGR_TG_Msk

#define TIM_EGR_TG_Msk   (0x1U << TIM_EGR_TG_Pos)

0x00000040

◆ TIM_EGR_TG_Pos

#define TIM_EGR_TG_Pos   (6U)

◆ TIM_EGR_UG

#define TIM_EGR_UG   TIM_EGR_UG_Msk

Update Generation

◆ TIM_EGR_UG_Msk

#define TIM_EGR_UG_Msk   (0x1U << TIM_EGR_UG_Pos)

0x00000001

◆ TIM_EGR_UG_Pos

#define TIM_EGR_UG_Pos   (0U)

◆ TIM_OR_ETR_RMP

#define TIM_OR_ETR_RMP   TIM_OR_ETR_RMP_Msk

ETR_RMP bit (TIM10/11 ETR remap)

◆ TIM_OR_ETR_RMP_Msk

#define TIM_OR_ETR_RMP_Msk   (0x1U << TIM_OR_ETR_RMP_Pos)

0x00000004

◆ TIM_OR_ETR_RMP_Pos

#define TIM_OR_ETR_RMP_Pos   (2U)

◆ TIM_OR_TI1_RMP_RI

#define TIM_OR_TI1_RMP_RI   TIM_OR_TI1_RMP_RI_Msk

TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface)

◆ TIM_OR_TI1_RMP_RI_Msk

#define TIM_OR_TI1_RMP_RI_Msk   (0x1U << TIM_OR_TI1_RMP_RI_Pos)

0x00000008

◆ TIM_OR_TI1_RMP_RI_Pos

#define TIM_OR_TI1_RMP_RI_Pos   (3U)

◆ TIM_OR_TI1RMP

#define TIM_OR_TI1RMP   TIM_OR_TI1RMP_Msk

TI1_RMP[1:0] bits (TIM Input 1 remap)

◆ TIM_OR_TI1RMP_0

#define TIM_OR_TI1RMP_0   (0x1U << TIM_OR_TI1RMP_Pos)

0x00000001

◆ TIM_OR_TI1RMP_1

#define TIM_OR_TI1RMP_1   (0x2U << TIM_OR_TI1RMP_Pos)

0x00000002

◆ TIM_OR_TI1RMP_Msk

#define TIM_OR_TI1RMP_Msk   (0x3U << TIM_OR_TI1RMP_Pos)

0x00000003

◆ TIM_OR_TI1RMP_Pos

#define TIM_OR_TI1RMP_Pos   (0U)

◆ TIM_PSC_PSC

#define TIM_PSC_PSC   TIM_PSC_PSC_Msk

Prescaler Value

◆ TIM_PSC_PSC_Msk

#define TIM_PSC_PSC_Msk   (0xFFFFU << TIM_PSC_PSC_Pos)

0x0000FFFF

◆ TIM_PSC_PSC_Pos

#define TIM_PSC_PSC_Pos   (0U)

◆ TIM_SMCR_ECE

#define TIM_SMCR_ECE   TIM_SMCR_ECE_Msk

External clock enable

◆ TIM_SMCR_ECE_Msk

#define TIM_SMCR_ECE_Msk   (0x1U << TIM_SMCR_ECE_Pos)

0x00004000

◆ TIM_SMCR_ECE_Pos

#define TIM_SMCR_ECE_Pos   (14U)

◆ TIM_SMCR_ETF

#define TIM_SMCR_ETF   TIM_SMCR_ETF_Msk

ETF[3:0] bits (External trigger filter)

◆ TIM_SMCR_ETF_0

#define TIM_SMCR_ETF_0   (0x1U << TIM_SMCR_ETF_Pos)

0x00000100

◆ TIM_SMCR_ETF_1

#define TIM_SMCR_ETF_1   (0x2U << TIM_SMCR_ETF_Pos)

0x00000200

◆ TIM_SMCR_ETF_2

#define TIM_SMCR_ETF_2   (0x4U << TIM_SMCR_ETF_Pos)

0x00000400

◆ TIM_SMCR_ETF_3

#define TIM_SMCR_ETF_3   (0x8U << TIM_SMCR_ETF_Pos)

0x00000800

◆ TIM_SMCR_ETF_Msk

#define TIM_SMCR_ETF_Msk   (0xFU << TIM_SMCR_ETF_Pos)

0x00000F00

◆ TIM_SMCR_ETF_Pos

#define TIM_SMCR_ETF_Pos   (8U)

◆ TIM_SMCR_ETP

#define TIM_SMCR_ETP   TIM_SMCR_ETP_Msk

External trigger polarity

◆ TIM_SMCR_ETP_Msk

#define TIM_SMCR_ETP_Msk   (0x1U << TIM_SMCR_ETP_Pos)

0x00008000

◆ TIM_SMCR_ETP_Pos

#define TIM_SMCR_ETP_Pos   (15U)

◆ TIM_SMCR_ETPS

#define TIM_SMCR_ETPS   TIM_SMCR_ETPS_Msk

ETPS[1:0] bits (External trigger prescaler)

◆ TIM_SMCR_ETPS_0

#define TIM_SMCR_ETPS_0   (0x1U << TIM_SMCR_ETPS_Pos)

0x00001000

◆ TIM_SMCR_ETPS_1

#define TIM_SMCR_ETPS_1   (0x2U << TIM_SMCR_ETPS_Pos)

0x00002000

◆ TIM_SMCR_ETPS_Msk

#define TIM_SMCR_ETPS_Msk   (0x3U << TIM_SMCR_ETPS_Pos)

0x00003000

◆ TIM_SMCR_ETPS_Pos

#define TIM_SMCR_ETPS_Pos   (12U)

◆ TIM_SMCR_MSM

#define TIM_SMCR_MSM   TIM_SMCR_MSM_Msk

Master/slave mode

◆ TIM_SMCR_MSM_Msk

#define TIM_SMCR_MSM_Msk   (0x1U << TIM_SMCR_MSM_Pos)

0x00000080

◆ TIM_SMCR_MSM_Pos

#define TIM_SMCR_MSM_Pos   (7U)

◆ TIM_SMCR_OCCS

#define TIM_SMCR_OCCS   TIM_SMCR_OCCS_Msk

OCREF clear selection

◆ TIM_SMCR_OCCS_Msk

#define TIM_SMCR_OCCS_Msk   (0x1U << TIM_SMCR_OCCS_Pos)

0x00000008

◆ TIM_SMCR_OCCS_Pos

#define TIM_SMCR_OCCS_Pos   (3U)

◆ TIM_SMCR_SMS

#define TIM_SMCR_SMS   TIM_SMCR_SMS_Msk

SMS[2:0] bits (Slave mode selection)

◆ TIM_SMCR_SMS_0

#define TIM_SMCR_SMS_0   (0x1U << TIM_SMCR_SMS_Pos)

0x00000001

◆ TIM_SMCR_SMS_1

#define TIM_SMCR_SMS_1   (0x2U << TIM_SMCR_SMS_Pos)

0x00000002

◆ TIM_SMCR_SMS_2

#define TIM_SMCR_SMS_2   (0x4U << TIM_SMCR_SMS_Pos)

0x00000004

◆ TIM_SMCR_SMS_Msk

#define TIM_SMCR_SMS_Msk   (0x7U << TIM_SMCR_SMS_Pos)

0x00000007

◆ TIM_SMCR_SMS_Pos

#define TIM_SMCR_SMS_Pos   (0U)

◆ TIM_SMCR_TS

#define TIM_SMCR_TS   TIM_SMCR_TS_Msk

TS[2:0] bits (Trigger selection)

◆ TIM_SMCR_TS_0

#define TIM_SMCR_TS_0   (0x1U << TIM_SMCR_TS_Pos)

0x00000010

◆ TIM_SMCR_TS_1

#define TIM_SMCR_TS_1   (0x2U << TIM_SMCR_TS_Pos)

0x00000020

◆ TIM_SMCR_TS_2

#define TIM_SMCR_TS_2   (0x4U << TIM_SMCR_TS_Pos)

0x00000040

◆ TIM_SMCR_TS_Msk

#define TIM_SMCR_TS_Msk   (0x7U << TIM_SMCR_TS_Pos)

0x00000070

◆ TIM_SMCR_TS_Pos

#define TIM_SMCR_TS_Pos   (4U)

◆ TIM_SR_CC1IF

#define TIM_SR_CC1IF   TIM_SR_CC1IF_Msk

Capture/Compare 1 interrupt Flag

◆ TIM_SR_CC1IF_Msk

#define TIM_SR_CC1IF_Msk   (0x1U << TIM_SR_CC1IF_Pos)

0x00000002

◆ TIM_SR_CC1IF_Pos

#define TIM_SR_CC1IF_Pos   (1U)

◆ TIM_SR_CC1OF

#define TIM_SR_CC1OF   TIM_SR_CC1OF_Msk

Capture/Compare 1 Overcapture Flag

◆ TIM_SR_CC1OF_Msk

#define TIM_SR_CC1OF_Msk   (0x1U << TIM_SR_CC1OF_Pos)

0x00000200

◆ TIM_SR_CC1OF_Pos

#define TIM_SR_CC1OF_Pos   (9U)

◆ TIM_SR_CC2IF

#define TIM_SR_CC2IF   TIM_SR_CC2IF_Msk

Capture/Compare 2 interrupt Flag

◆ TIM_SR_CC2IF_Msk

#define TIM_SR_CC2IF_Msk   (0x1U << TIM_SR_CC2IF_Pos)

0x00000004

◆ TIM_SR_CC2IF_Pos

#define TIM_SR_CC2IF_Pos   (2U)

◆ TIM_SR_CC2OF

#define TIM_SR_CC2OF   TIM_SR_CC2OF_Msk

Capture/Compare 2 Overcapture Flag

◆ TIM_SR_CC2OF_Msk

#define TIM_SR_CC2OF_Msk   (0x1U << TIM_SR_CC2OF_Pos)

0x00000400

◆ TIM_SR_CC2OF_Pos

#define TIM_SR_CC2OF_Pos   (10U)

◆ TIM_SR_CC3IF

#define TIM_SR_CC3IF   TIM_SR_CC3IF_Msk

Capture/Compare 3 interrupt Flag

◆ TIM_SR_CC3IF_Msk

#define TIM_SR_CC3IF_Msk   (0x1U << TIM_SR_CC3IF_Pos)

0x00000008

◆ TIM_SR_CC3IF_Pos

#define TIM_SR_CC3IF_Pos   (3U)

◆ TIM_SR_CC3OF

#define TIM_SR_CC3OF   TIM_SR_CC3OF_Msk

Capture/Compare 3 Overcapture Flag

◆ TIM_SR_CC3OF_Msk

#define TIM_SR_CC3OF_Msk   (0x1U << TIM_SR_CC3OF_Pos)

0x00000800

◆ TIM_SR_CC3OF_Pos

#define TIM_SR_CC3OF_Pos   (11U)

◆ TIM_SR_CC4IF

#define TIM_SR_CC4IF   TIM_SR_CC4IF_Msk

Capture/Compare 4 interrupt Flag

◆ TIM_SR_CC4IF_Msk

#define TIM_SR_CC4IF_Msk   (0x1U << TIM_SR_CC4IF_Pos)

0x00000010

◆ TIM_SR_CC4IF_Pos

#define TIM_SR_CC4IF_Pos   (4U)

◆ TIM_SR_CC4OF

#define TIM_SR_CC4OF   TIM_SR_CC4OF_Msk

Capture/Compare 4 Overcapture Flag

◆ TIM_SR_CC4OF_Msk

#define TIM_SR_CC4OF_Msk   (0x1U << TIM_SR_CC4OF_Pos)

0x00001000

◆ TIM_SR_CC4OF_Pos

#define TIM_SR_CC4OF_Pos   (12U)

◆ TIM_SR_TIF

#define TIM_SR_TIF   TIM_SR_TIF_Msk

Trigger interrupt Flag

◆ TIM_SR_TIF_Msk

#define TIM_SR_TIF_Msk   (0x1U << TIM_SR_TIF_Pos)

0x00000040

◆ TIM_SR_TIF_Pos

#define TIM_SR_TIF_Pos   (6U)

◆ TIM_SR_UIF

#define TIM_SR_UIF   TIM_SR_UIF_Msk

Update interrupt Flag

◆ TIM_SR_UIF_Msk

#define TIM_SR_UIF_Msk   (0x1U << TIM_SR_UIF_Pos)

0x00000001

◆ TIM_SR_UIF_Pos

#define TIM_SR_UIF_Pos   (0U)

◆ USART_BRR_DIV_FRACTION

#define USART_BRR_DIV_FRACTION   USART_BRR_DIV_FRACTION_Msk

Fraction of USARTDIV

◆ USART_BRR_DIV_FRACTION_Msk

#define USART_BRR_DIV_FRACTION_Msk   (0xFU << USART_BRR_DIV_FRACTION_Pos)

0x0000000F

◆ USART_BRR_DIV_FRACTION_Pos

#define USART_BRR_DIV_FRACTION_Pos   (0U)

◆ USART_BRR_DIV_MANTISSA

#define USART_BRR_DIV_MANTISSA   USART_BRR_DIV_MANTISSA_Msk

Mantissa of USARTDIV

◆ USART_BRR_DIV_MANTISSA_Msk

#define USART_BRR_DIV_MANTISSA_Msk   (0xFFFU << USART_BRR_DIV_MANTISSA_Pos)

0x0000FFF0

◆ USART_BRR_DIV_MANTISSA_Pos

#define USART_BRR_DIV_MANTISSA_Pos   (4U)

◆ USART_CR1_IDLEIE

#define USART_CR1_IDLEIE   USART_CR1_IDLEIE_Msk

IDLE Interrupt Enable

◆ USART_CR1_IDLEIE_Msk

#define USART_CR1_IDLEIE_Msk   (0x1U << USART_CR1_IDLEIE_Pos)

0x00000010

◆ USART_CR1_IDLEIE_Pos

#define USART_CR1_IDLEIE_Pos   (4U)

◆ USART_CR1_M

#define USART_CR1_M   USART_CR1_M_Msk

Word length

◆ USART_CR1_M_Msk

#define USART_CR1_M_Msk   (0x1U << USART_CR1_M_Pos)

0x00001000

◆ USART_CR1_M_Pos

#define USART_CR1_M_Pos   (12U)

◆ USART_CR1_OVER8

#define USART_CR1_OVER8   USART_CR1_OVER8_Msk

Oversampling by 8-bit mode

◆ USART_CR1_OVER8_Msk

#define USART_CR1_OVER8_Msk   (0x1U << USART_CR1_OVER8_Pos)

0x00008000

◆ USART_CR1_OVER8_Pos

#define USART_CR1_OVER8_Pos   (15U)

◆ USART_CR1_PCE

#define USART_CR1_PCE   USART_CR1_PCE_Msk

Parity Control Enable

◆ USART_CR1_PCE_Msk

#define USART_CR1_PCE_Msk   (0x1U << USART_CR1_PCE_Pos)

0x00000400

◆ USART_CR1_PCE_Pos

#define USART_CR1_PCE_Pos   (10U)

◆ USART_CR1_PEIE

#define USART_CR1_PEIE   USART_CR1_PEIE_Msk

PE Interrupt Enable

◆ USART_CR1_PEIE_Msk

#define USART_CR1_PEIE_Msk   (0x1U << USART_CR1_PEIE_Pos)

0x00000100

◆ USART_CR1_PEIE_Pos

#define USART_CR1_PEIE_Pos   (8U)

◆ USART_CR1_PS

#define USART_CR1_PS   USART_CR1_PS_Msk

Parity Selection

◆ USART_CR1_PS_Msk

#define USART_CR1_PS_Msk   (0x1U << USART_CR1_PS_Pos)

0x00000200

◆ USART_CR1_PS_Pos

#define USART_CR1_PS_Pos   (9U)

◆ USART_CR1_RE

#define USART_CR1_RE   USART_CR1_RE_Msk

Receiver Enable

◆ USART_CR1_RE_Msk

#define USART_CR1_RE_Msk   (0x1U << USART_CR1_RE_Pos)

0x00000004

◆ USART_CR1_RE_Pos

#define USART_CR1_RE_Pos   (2U)

◆ USART_CR1_RWU

#define USART_CR1_RWU   USART_CR1_RWU_Msk

Receiver wakeup

◆ USART_CR1_RWU_Msk

#define USART_CR1_RWU_Msk   (0x1U << USART_CR1_RWU_Pos)

0x00000002

◆ USART_CR1_RWU_Pos

#define USART_CR1_RWU_Pos   (1U)

◆ USART_CR1_RXNEIE

#define USART_CR1_RXNEIE   USART_CR1_RXNEIE_Msk

RXNE Interrupt Enable

◆ USART_CR1_RXNEIE_Msk

#define USART_CR1_RXNEIE_Msk   (0x1U << USART_CR1_RXNEIE_Pos)

0x00000020

◆ USART_CR1_RXNEIE_Pos

#define USART_CR1_RXNEIE_Pos   (5U)

◆ USART_CR1_SBK

#define USART_CR1_SBK   USART_CR1_SBK_Msk

Send Break

◆ USART_CR1_SBK_Msk

#define USART_CR1_SBK_Msk   (0x1U << USART_CR1_SBK_Pos)

0x00000001

◆ USART_CR1_SBK_Pos

#define USART_CR1_SBK_Pos   (0U)

◆ USART_CR1_TCIE

#define USART_CR1_TCIE   USART_CR1_TCIE_Msk

Transmission Complete Interrupt Enable

◆ USART_CR1_TCIE_Msk

#define USART_CR1_TCIE_Msk   (0x1U << USART_CR1_TCIE_Pos)

0x00000040

◆ USART_CR1_TCIE_Pos

#define USART_CR1_TCIE_Pos   (6U)

◆ USART_CR1_TE

#define USART_CR1_TE   USART_CR1_TE_Msk

Transmitter Enable

◆ USART_CR1_TE_Msk

#define USART_CR1_TE_Msk   (0x1U << USART_CR1_TE_Pos)

0x00000008

◆ USART_CR1_TE_Pos

#define USART_CR1_TE_Pos   (3U)

◆ USART_CR1_TXEIE

#define USART_CR1_TXEIE   USART_CR1_TXEIE_Msk

PE Interrupt Enable

◆ USART_CR1_TXEIE_Msk

#define USART_CR1_TXEIE_Msk   (0x1U << USART_CR1_TXEIE_Pos)

0x00000080

◆ USART_CR1_TXEIE_Pos

#define USART_CR1_TXEIE_Pos   (7U)

◆ USART_CR1_UE

#define USART_CR1_UE   USART_CR1_UE_Msk

USART Enable

◆ USART_CR1_UE_Msk

#define USART_CR1_UE_Msk   (0x1U << USART_CR1_UE_Pos)

0x00002000

◆ USART_CR1_UE_Pos

#define USART_CR1_UE_Pos   (13U)

◆ USART_CR1_WAKE

#define USART_CR1_WAKE   USART_CR1_WAKE_Msk

Wakeup method

◆ USART_CR1_WAKE_Msk

#define USART_CR1_WAKE_Msk   (0x1U << USART_CR1_WAKE_Pos)

0x00000800

◆ USART_CR1_WAKE_Pos

#define USART_CR1_WAKE_Pos   (11U)

◆ USART_CR2_ADD

#define USART_CR2_ADD   USART_CR2_ADD_Msk

Address of the USART node

◆ USART_CR2_ADD_Msk

#define USART_CR2_ADD_Msk   (0xFU << USART_CR2_ADD_Pos)

0x0000000F

◆ USART_CR2_ADD_Pos

#define USART_CR2_ADD_Pos   (0U)

◆ USART_CR2_CLKEN

#define USART_CR2_CLKEN   USART_CR2_CLKEN_Msk

Clock Enable

◆ USART_CR2_CLKEN_Msk

#define USART_CR2_CLKEN_Msk   (0x1U << USART_CR2_CLKEN_Pos)

0x00000800

◆ USART_CR2_CLKEN_Pos

#define USART_CR2_CLKEN_Pos   (11U)

◆ USART_CR2_CPHA

#define USART_CR2_CPHA   USART_CR2_CPHA_Msk

Clock Phase

◆ USART_CR2_CPHA_Msk

#define USART_CR2_CPHA_Msk   (0x1U << USART_CR2_CPHA_Pos)

0x00000200

◆ USART_CR2_CPHA_Pos

#define USART_CR2_CPHA_Pos   (9U)

◆ USART_CR2_CPOL

#define USART_CR2_CPOL   USART_CR2_CPOL_Msk

Clock Polarity

◆ USART_CR2_CPOL_Msk

#define USART_CR2_CPOL_Msk   (0x1U << USART_CR2_CPOL_Pos)

0x00000400

◆ USART_CR2_CPOL_Pos

#define USART_CR2_CPOL_Pos   (10U)

◆ USART_CR2_LBCL

#define USART_CR2_LBCL   USART_CR2_LBCL_Msk

Last Bit Clock pulse

◆ USART_CR2_LBCL_Msk

#define USART_CR2_LBCL_Msk   (0x1U << USART_CR2_LBCL_Pos)

0x00000100

◆ USART_CR2_LBCL_Pos

#define USART_CR2_LBCL_Pos   (8U)

◆ USART_CR2_LBDIE

#define USART_CR2_LBDIE   USART_CR2_LBDIE_Msk

LIN Break Detection Interrupt Enable

◆ USART_CR2_LBDIE_Msk

#define USART_CR2_LBDIE_Msk   (0x1U << USART_CR2_LBDIE_Pos)

0x00000040

◆ USART_CR2_LBDIE_Pos

#define USART_CR2_LBDIE_Pos   (6U)

◆ USART_CR2_LBDL

#define USART_CR2_LBDL   USART_CR2_LBDL_Msk

LIN Break Detection Length

◆ USART_CR2_LBDL_Msk

#define USART_CR2_LBDL_Msk   (0x1U << USART_CR2_LBDL_Pos)

0x00000020

◆ USART_CR2_LBDL_Pos

#define USART_CR2_LBDL_Pos   (5U)

◆ USART_CR2_LINEN

#define USART_CR2_LINEN   USART_CR2_LINEN_Msk

LIN mode enable

◆ USART_CR2_LINEN_Msk

#define USART_CR2_LINEN_Msk   (0x1U << USART_CR2_LINEN_Pos)

0x00004000

◆ USART_CR2_LINEN_Pos

#define USART_CR2_LINEN_Pos   (14U)

◆ USART_CR2_STOP

#define USART_CR2_STOP   USART_CR2_STOP_Msk

STOP[1:0] bits (STOP bits)

◆ USART_CR2_STOP_0

#define USART_CR2_STOP_0   (0x1U << USART_CR2_STOP_Pos)

0x00001000

◆ USART_CR2_STOP_1

#define USART_CR2_STOP_1   (0x2U << USART_CR2_STOP_Pos)

0x00002000

◆ USART_CR2_STOP_Msk

#define USART_CR2_STOP_Msk   (0x3U << USART_CR2_STOP_Pos)

0x00003000

◆ USART_CR2_STOP_Pos

#define USART_CR2_STOP_Pos   (12U)

◆ USART_CR3_CTSE

#define USART_CR3_CTSE   USART_CR3_CTSE_Msk

CTS Enable

◆ USART_CR3_CTSE_Msk

#define USART_CR3_CTSE_Msk   (0x1U << USART_CR3_CTSE_Pos)

0x00000200

◆ USART_CR3_CTSE_Pos

#define USART_CR3_CTSE_Pos   (9U)

◆ USART_CR3_CTSIE

#define USART_CR3_CTSIE   USART_CR3_CTSIE_Msk

CTS Interrupt Enable

◆ USART_CR3_CTSIE_Msk

#define USART_CR3_CTSIE_Msk   (0x1U << USART_CR3_CTSIE_Pos)

0x00000400

◆ USART_CR3_CTSIE_Pos

#define USART_CR3_CTSIE_Pos   (10U)

◆ USART_CR3_DMAR

#define USART_CR3_DMAR   USART_CR3_DMAR_Msk

DMA Enable Receiver

◆ USART_CR3_DMAR_Msk

#define USART_CR3_DMAR_Msk   (0x1U << USART_CR3_DMAR_Pos)

0x00000040

◆ USART_CR3_DMAR_Pos

#define USART_CR3_DMAR_Pos   (6U)

◆ USART_CR3_DMAT

#define USART_CR3_DMAT   USART_CR3_DMAT_Msk

DMA Enable Transmitter

◆ USART_CR3_DMAT_Msk

#define USART_CR3_DMAT_Msk   (0x1U << USART_CR3_DMAT_Pos)

0x00000080

◆ USART_CR3_DMAT_Pos

#define USART_CR3_DMAT_Pos   (7U)

◆ USART_CR3_EIE

#define USART_CR3_EIE   USART_CR3_EIE_Msk

Error Interrupt Enable

◆ USART_CR3_EIE_Msk

#define USART_CR3_EIE_Msk   (0x1U << USART_CR3_EIE_Pos)

0x00000001

◆ USART_CR3_EIE_Pos

#define USART_CR3_EIE_Pos   (0U)

◆ USART_CR3_HDSEL

#define USART_CR3_HDSEL   USART_CR3_HDSEL_Msk

Half-Duplex Selection

◆ USART_CR3_HDSEL_Msk

#define USART_CR3_HDSEL_Msk   (0x1U << USART_CR3_HDSEL_Pos)

0x00000008

◆ USART_CR3_HDSEL_Pos

#define USART_CR3_HDSEL_Pos   (3U)

◆ USART_CR3_IREN

#define USART_CR3_IREN   USART_CR3_IREN_Msk

IrDA mode Enable

◆ USART_CR3_IREN_Msk

#define USART_CR3_IREN_Msk   (0x1U << USART_CR3_IREN_Pos)

0x00000002

◆ USART_CR3_IREN_Pos

#define USART_CR3_IREN_Pos   (1U)

◆ USART_CR3_IRLP

#define USART_CR3_IRLP   USART_CR3_IRLP_Msk

IrDA Low-Power

◆ USART_CR3_IRLP_Msk

#define USART_CR3_IRLP_Msk   (0x1U << USART_CR3_IRLP_Pos)

0x00000004

◆ USART_CR3_IRLP_Pos

#define USART_CR3_IRLP_Pos   (2U)

◆ USART_CR3_NACK

#define USART_CR3_NACK   USART_CR3_NACK_Msk

Smartcard NACK enable

◆ USART_CR3_NACK_Msk

#define USART_CR3_NACK_Msk   (0x1U << USART_CR3_NACK_Pos)

0x00000010

◆ USART_CR3_NACK_Pos

#define USART_CR3_NACK_Pos   (4U)

◆ USART_CR3_ONEBIT

#define USART_CR3_ONEBIT   USART_CR3_ONEBIT_Msk

One sample bit method enable

◆ USART_CR3_ONEBIT_Msk

#define USART_CR3_ONEBIT_Msk   (0x1U << USART_CR3_ONEBIT_Pos)

0x00000800

◆ USART_CR3_ONEBIT_Pos

#define USART_CR3_ONEBIT_Pos   (11U)

◆ USART_CR3_RTSE

#define USART_CR3_RTSE   USART_CR3_RTSE_Msk

RTS Enable

◆ USART_CR3_RTSE_Msk

#define USART_CR3_RTSE_Msk   (0x1U << USART_CR3_RTSE_Pos)

0x00000100

◆ USART_CR3_RTSE_Pos

#define USART_CR3_RTSE_Pos   (8U)

◆ USART_CR3_SCEN

#define USART_CR3_SCEN   USART_CR3_SCEN_Msk

Smartcard mode enable

◆ USART_CR3_SCEN_Msk

#define USART_CR3_SCEN_Msk   (0x1U << USART_CR3_SCEN_Pos)

0x00000020

◆ USART_CR3_SCEN_Pos

#define USART_CR3_SCEN_Pos   (5U)

◆ USART_DR_DR

#define USART_DR_DR   USART_DR_DR_Msk

Data value

◆ USART_DR_DR_Msk

#define USART_DR_DR_Msk   (0x1FFU << USART_DR_DR_Pos)

0x000001FF

◆ USART_DR_DR_Pos

#define USART_DR_DR_Pos   (0U)

◆ USART_GTPR_GT

#define USART_GTPR_GT   USART_GTPR_GT_Msk

Guard time value

◆ USART_GTPR_GT_Msk

#define USART_GTPR_GT_Msk   (0xFFU << USART_GTPR_GT_Pos)

0x0000FF00

◆ USART_GTPR_GT_Pos

#define USART_GTPR_GT_Pos   (8U)

◆ USART_GTPR_PSC

#define USART_GTPR_PSC   USART_GTPR_PSC_Msk

PSC[7:0] bits (Prescaler value)

◆ USART_GTPR_PSC_0

#define USART_GTPR_PSC_0   (0x01U << USART_GTPR_PSC_Pos)

0x00000001

◆ USART_GTPR_PSC_1

#define USART_GTPR_PSC_1   (0x02U << USART_GTPR_PSC_Pos)

0x00000002

◆ USART_GTPR_PSC_2

#define USART_GTPR_PSC_2   (0x04U << USART_GTPR_PSC_Pos)

0x00000004

◆ USART_GTPR_PSC_3

#define USART_GTPR_PSC_3   (0x08U << USART_GTPR_PSC_Pos)

0x00000008

◆ USART_GTPR_PSC_4

#define USART_GTPR_PSC_4   (0x10U << USART_GTPR_PSC_Pos)

0x00000010

◆ USART_GTPR_PSC_5

#define USART_GTPR_PSC_5   (0x20U << USART_GTPR_PSC_Pos)

0x00000020

◆ USART_GTPR_PSC_6

#define USART_GTPR_PSC_6   (0x40U << USART_GTPR_PSC_Pos)

0x00000040

◆ USART_GTPR_PSC_7

#define USART_GTPR_PSC_7   (0x80U << USART_GTPR_PSC_Pos)

0x00000080

◆ USART_GTPR_PSC_Msk

#define USART_GTPR_PSC_Msk   (0xFFU << USART_GTPR_PSC_Pos)

0x000000FF

◆ USART_GTPR_PSC_Pos

#define USART_GTPR_PSC_Pos   (0U)

◆ USART_SR_CTS

#define USART_SR_CTS   USART_SR_CTS_Msk

CTS Flag

◆ USART_SR_CTS_Msk

#define USART_SR_CTS_Msk   (0x1U << USART_SR_CTS_Pos)

0x00000200

◆ USART_SR_CTS_Pos

#define USART_SR_CTS_Pos   (9U)

◆ USART_SR_FE

#define USART_SR_FE   USART_SR_FE_Msk

Framing Error

◆ USART_SR_FE_Msk

#define USART_SR_FE_Msk   (0x1U << USART_SR_FE_Pos)

0x00000002

◆ USART_SR_FE_Pos

#define USART_SR_FE_Pos   (1U)

◆ USART_SR_IDLE

#define USART_SR_IDLE   USART_SR_IDLE_Msk

IDLE line detected

◆ USART_SR_IDLE_Msk

#define USART_SR_IDLE_Msk   (0x1U << USART_SR_IDLE_Pos)

0x00000010

◆ USART_SR_IDLE_Pos

#define USART_SR_IDLE_Pos   (4U)

◆ USART_SR_LBD

#define USART_SR_LBD   USART_SR_LBD_Msk

LIN Break Detection Flag

◆ USART_SR_LBD_Msk

#define USART_SR_LBD_Msk   (0x1U << USART_SR_LBD_Pos)

0x00000100

◆ USART_SR_LBD_Pos

#define USART_SR_LBD_Pos   (8U)

◆ USART_SR_NE

#define USART_SR_NE   USART_SR_NE_Msk

Noise Error Flag

◆ USART_SR_NE_Msk

#define USART_SR_NE_Msk   (0x1U << USART_SR_NE_Pos)

0x00000004

◆ USART_SR_NE_Pos

#define USART_SR_NE_Pos   (2U)

◆ USART_SR_ORE

#define USART_SR_ORE   USART_SR_ORE_Msk

OverRun Error

◆ USART_SR_ORE_Msk

#define USART_SR_ORE_Msk   (0x1U << USART_SR_ORE_Pos)

0x00000008

◆ USART_SR_ORE_Pos

#define USART_SR_ORE_Pos   (3U)

◆ USART_SR_PE

#define USART_SR_PE   USART_SR_PE_Msk

Parity Error

◆ USART_SR_PE_Msk

#define USART_SR_PE_Msk   (0x1U << USART_SR_PE_Pos)

0x00000001

◆ USART_SR_PE_Pos

#define USART_SR_PE_Pos   (0U)

◆ USART_SR_RXNE

#define USART_SR_RXNE   USART_SR_RXNE_Msk

Read Data Register Not Empty

◆ USART_SR_RXNE_Msk

#define USART_SR_RXNE_Msk   (0x1U << USART_SR_RXNE_Pos)

0x00000020

◆ USART_SR_RXNE_Pos

#define USART_SR_RXNE_Pos   (5U)

◆ USART_SR_TC

#define USART_SR_TC   USART_SR_TC_Msk

Transmission Complete

◆ USART_SR_TC_Msk

#define USART_SR_TC_Msk   (0x1U << USART_SR_TC_Pos)

0x00000040

◆ USART_SR_TC_Pos

#define USART_SR_TC_Pos   (6U)

◆ USART_SR_TXE

#define USART_SR_TXE   USART_SR_TXE_Msk

Transmit Data Register Empty

◆ USART_SR_TXE_Msk

#define USART_SR_TXE_Msk   (0x1U << USART_SR_TXE_Pos)

0x00000080

◆ USART_SR_TXE_Pos

#define USART_SR_TXE_Pos   (7U)

◆ USB_ADDR0_RX_ADDR0_RX

#define USB_ADDR0_RX_ADDR0_RX   USB_ADDR0_RX_ADDR0_RX_Msk

Reception Buffer Address 0

◆ USB_ADDR0_RX_ADDR0_RX_Msk

#define USB_ADDR0_RX_ADDR0_RX_Msk   (0x7FFFU << USB_ADDR0_RX_ADDR0_RX_Pos)

0x0000FFFE

◆ USB_ADDR0_RX_ADDR0_RX_Pos

#define USB_ADDR0_RX_ADDR0_RX_Pos   (1U)

◆ USB_ADDR0_TX_ADDR0_TX

#define USB_ADDR0_TX_ADDR0_TX   USB_ADDR0_TX_ADDR0_TX_Msk

Transmission Buffer Address 0

◆ USB_ADDR0_TX_ADDR0_TX_Msk

#define USB_ADDR0_TX_ADDR0_TX_Msk   (0x7FFFU << USB_ADDR0_TX_ADDR0_TX_Pos)

0x0000FFFE

◆ USB_ADDR0_TX_ADDR0_TX_Pos

#define USB_ADDR0_TX_ADDR0_TX_Pos   (1U)

◆ USB_ADDR1_RX_ADDR1_RX

#define USB_ADDR1_RX_ADDR1_RX   USB_ADDR1_RX_ADDR1_RX_Msk

Reception Buffer Address 1

◆ USB_ADDR1_RX_ADDR1_RX_Msk

#define USB_ADDR1_RX_ADDR1_RX_Msk   (0x7FFFU << USB_ADDR1_RX_ADDR1_RX_Pos)

0x0000FFFE

◆ USB_ADDR1_RX_ADDR1_RX_Pos

#define USB_ADDR1_RX_ADDR1_RX_Pos   (1U)

◆ USB_ADDR1_TX_ADDR1_TX

#define USB_ADDR1_TX_ADDR1_TX   USB_ADDR1_TX_ADDR1_TX_Msk

Transmission Buffer Address 1

◆ USB_ADDR1_TX_ADDR1_TX_Msk

#define USB_ADDR1_TX_ADDR1_TX_Msk   (0x7FFFU << USB_ADDR1_TX_ADDR1_TX_Pos)

0x0000FFFE

◆ USB_ADDR1_TX_ADDR1_TX_Pos

#define USB_ADDR1_TX_ADDR1_TX_Pos   (1U)

◆ USB_ADDR2_RX_ADDR2_RX

#define USB_ADDR2_RX_ADDR2_RX   USB_ADDR2_RX_ADDR2_RX_Msk

Reception Buffer Address 2

◆ USB_ADDR2_RX_ADDR2_RX_Msk

#define USB_ADDR2_RX_ADDR2_RX_Msk   (0x7FFFU << USB_ADDR2_RX_ADDR2_RX_Pos)

0x0000FFFE

◆ USB_ADDR2_RX_ADDR2_RX_Pos

#define USB_ADDR2_RX_ADDR2_RX_Pos   (1U)

◆ USB_ADDR2_TX_ADDR2_TX

#define USB_ADDR2_TX_ADDR2_TX   USB_ADDR2_TX_ADDR2_TX_Msk

Transmission Buffer Address 2

◆ USB_ADDR2_TX_ADDR2_TX_Msk

#define USB_ADDR2_TX_ADDR2_TX_Msk   (0x7FFFU << USB_ADDR2_TX_ADDR2_TX_Pos)

0x0000FFFE

◆ USB_ADDR2_TX_ADDR2_TX_Pos

#define USB_ADDR2_TX_ADDR2_TX_Pos   (1U)

◆ USB_ADDR3_RX_ADDR3_RX

#define USB_ADDR3_RX_ADDR3_RX   USB_ADDR3_RX_ADDR3_RX_Msk

Reception Buffer Address 3

◆ USB_ADDR3_RX_ADDR3_RX_Msk

#define USB_ADDR3_RX_ADDR3_RX_Msk   (0x7FFFU << USB_ADDR3_RX_ADDR3_RX_Pos)

0x0000FFFE

◆ USB_ADDR3_RX_ADDR3_RX_Pos

#define USB_ADDR3_RX_ADDR3_RX_Pos   (1U)

◆ USB_ADDR3_TX_ADDR3_TX

#define USB_ADDR3_TX_ADDR3_TX   USB_ADDR3_TX_ADDR3_TX_Msk

Transmission Buffer Address 3

◆ USB_ADDR3_TX_ADDR3_TX_Msk

#define USB_ADDR3_TX_ADDR3_TX_Msk   (0x7FFFU << USB_ADDR3_TX_ADDR3_TX_Pos)

0x0000FFFE

◆ USB_ADDR3_TX_ADDR3_TX_Pos

#define USB_ADDR3_TX_ADDR3_TX_Pos   (1U)

◆ USB_ADDR4_RX_ADDR4_RX

#define USB_ADDR4_RX_ADDR4_RX   USB_ADDR4_RX_ADDR4_RX_Msk

Reception Buffer Address 4

◆ USB_ADDR4_RX_ADDR4_RX_Msk

#define USB_ADDR4_RX_ADDR4_RX_Msk   (0x7FFFU << USB_ADDR4_RX_ADDR4_RX_Pos)

0x0000FFFE

◆ USB_ADDR4_RX_ADDR4_RX_Pos

#define USB_ADDR4_RX_ADDR4_RX_Pos   (1U)

◆ USB_ADDR4_TX_ADDR4_TX

#define USB_ADDR4_TX_ADDR4_TX   USB_ADDR4_TX_ADDR4_TX_Msk

Transmission Buffer Address 4

◆ USB_ADDR4_TX_ADDR4_TX_Msk

#define USB_ADDR4_TX_ADDR4_TX_Msk   (0x7FFFU << USB_ADDR4_TX_ADDR4_TX_Pos)

0x0000FFFE

◆ USB_ADDR4_TX_ADDR4_TX_Pos

#define USB_ADDR4_TX_ADDR4_TX_Pos   (1U)

◆ USB_ADDR5_RX_ADDR5_RX

#define USB_ADDR5_RX_ADDR5_RX   USB_ADDR5_RX_ADDR5_RX_Msk

Reception Buffer Address 5

◆ USB_ADDR5_RX_ADDR5_RX_Msk

#define USB_ADDR5_RX_ADDR5_RX_Msk   (0x7FFFU << USB_ADDR5_RX_ADDR5_RX_Pos)

0x0000FFFE

◆ USB_ADDR5_RX_ADDR5_RX_Pos

#define USB_ADDR5_RX_ADDR5_RX_Pos   (1U)

◆ USB_ADDR5_TX_ADDR5_TX

#define USB_ADDR5_TX_ADDR5_TX   USB_ADDR5_TX_ADDR5_TX_Msk

Transmission Buffer Address 5

◆ USB_ADDR5_TX_ADDR5_TX_Msk

#define USB_ADDR5_TX_ADDR5_TX_Msk   (0x7FFFU << USB_ADDR5_TX_ADDR5_TX_Pos)

0x0000FFFE

◆ USB_ADDR5_TX_ADDR5_TX_Pos

#define USB_ADDR5_TX_ADDR5_TX_Pos   (1U)

◆ USB_ADDR6_RX_ADDR6_RX

#define USB_ADDR6_RX_ADDR6_RX   USB_ADDR6_RX_ADDR6_RX_Msk

Reception Buffer Address 6

◆ USB_ADDR6_RX_ADDR6_RX_Msk

#define USB_ADDR6_RX_ADDR6_RX_Msk   (0x7FFFU << USB_ADDR6_RX_ADDR6_RX_Pos)

0x0000FFFE

◆ USB_ADDR6_RX_ADDR6_RX_Pos

#define USB_ADDR6_RX_ADDR6_RX_Pos   (1U)

◆ USB_ADDR6_TX_ADDR6_TX

#define USB_ADDR6_TX_ADDR6_TX   USB_ADDR6_TX_ADDR6_TX_Msk

Transmission Buffer Address 6

◆ USB_ADDR6_TX_ADDR6_TX_Msk

#define USB_ADDR6_TX_ADDR6_TX_Msk   (0x7FFFU << USB_ADDR6_TX_ADDR6_TX_Pos)

0x0000FFFE

◆ USB_ADDR6_TX_ADDR6_TX_Pos

#define USB_ADDR6_TX_ADDR6_TX_Pos   (1U)

◆ USB_ADDR7_RX_ADDR7_RX

#define USB_ADDR7_RX_ADDR7_RX   USB_ADDR7_RX_ADDR7_RX_Msk

Reception Buffer Address 7

◆ USB_ADDR7_RX_ADDR7_RX_Msk

#define USB_ADDR7_RX_ADDR7_RX_Msk   (0x7FFFU << USB_ADDR7_RX_ADDR7_RX_Pos)

0x0000FFFE

◆ USB_ADDR7_RX_ADDR7_RX_Pos

#define USB_ADDR7_RX_ADDR7_RX_Pos   (1U)

◆ USB_ADDR7_TX_ADDR7_TX

#define USB_ADDR7_TX_ADDR7_TX   USB_ADDR7_TX_ADDR7_TX_Msk

Transmission Buffer Address 7

◆ USB_ADDR7_TX_ADDR7_TX_Msk

#define USB_ADDR7_TX_ADDR7_TX_Msk   (0x7FFFU << USB_ADDR7_TX_ADDR7_TX_Pos)

0x0000FFFE

◆ USB_ADDR7_TX_ADDR7_TX_Pos

#define USB_ADDR7_TX_ADDR7_TX_Pos   (1U)

◆ USB_BTABLE

#define USB_BTABLE   (USB_BASE + 0x00000050U)

Buffer Table address register

◆ USB_BTABLE_BTABLE

#define USB_BTABLE_BTABLE   USB_BTABLE_BTABLE_Msk

Buffer Table Buffer descriptor table

◆ USB_BTABLE_BTABLE_Msk

#define USB_BTABLE_BTABLE_Msk   (0x1FFFU << USB_BTABLE_BTABLE_Pos)

0x0000FFF8

◆ USB_BTABLE_BTABLE_Pos

#define USB_BTABLE_BTABLE_Pos   (3U)

◆ USB_CLR_CTR

#define USB_CLR_CTR   (~USB_ISTR_CTR)

clear Correct TRansfer bit

◆ USB_CLR_ERR

#define USB_CLR_ERR   (~USB_ISTR_ERR)

clear ERRor bit

◆ USB_CLR_ESOF

#define USB_CLR_ESOF   (~USB_ISTR_ESOF)

clear Expected Start Of Frame bit

◆ USB_CLR_PMAOVRM

#define USB_CLR_PMAOVRM   (~USB_ISTR_PMAOVR)

clear DMA OVeR/underrun bit

◆ USB_CLR_RESET

#define USB_CLR_RESET   (~USB_ISTR_RESET)

clear RESET bit

◆ USB_CLR_SOF

#define USB_CLR_SOF   (~USB_ISTR_SOF)

clear Start Of Frame bit

◆ USB_CLR_SUSP

#define USB_CLR_SUSP   (~USB_ISTR_SUSP)

clear SUSPend bit

◆ USB_CLR_WKUP

#define USB_CLR_WKUP   (~USB_ISTR_WKUP)

clear WaKe UP bit

◆ USB_CNTR

#define USB_CNTR   (USB_BASE + 0x00000040U)

Control register

◆ USB_CNTR_CTRM

#define USB_CNTR_CTRM   USB_CNTR_CTRM_Msk

Correct Transfer Interrupt Mask

◆ USB_CNTR_CTRM_Msk

#define USB_CNTR_CTRM_Msk   (0x1U << USB_CNTR_CTRM_Pos)

0x00008000

◆ USB_CNTR_CTRM_Pos

#define USB_CNTR_CTRM_Pos   (15U)

◆ USB_CNTR_ERRM

#define USB_CNTR_ERRM   USB_CNTR_ERRM_Msk

Error Interrupt Mask

◆ USB_CNTR_ERRM_Msk

#define USB_CNTR_ERRM_Msk   (0x1U << USB_CNTR_ERRM_Pos)

0x00002000

◆ USB_CNTR_ERRM_Pos

#define USB_CNTR_ERRM_Pos   (13U)

◆ USB_CNTR_ESOFM

#define USB_CNTR_ESOFM   USB_CNTR_ESOFM_Msk

Expected Start Of Frame Interrupt Mask

◆ USB_CNTR_ESOFM_Msk

#define USB_CNTR_ESOFM_Msk   (0x1U << USB_CNTR_ESOFM_Pos)

0x00000100

◆ USB_CNTR_ESOFM_Pos

#define USB_CNTR_ESOFM_Pos   (8U)

◆ USB_CNTR_FRES

#define USB_CNTR_FRES   USB_CNTR_FRES_Msk

Force USB Reset

◆ USB_CNTR_FRES_Msk

#define USB_CNTR_FRES_Msk   (0x1U << USB_CNTR_FRES_Pos)

0x00000001

◆ USB_CNTR_FRES_Pos

#define USB_CNTR_FRES_Pos   (0U)

◆ USB_CNTR_FSUSP

#define USB_CNTR_FSUSP   USB_CNTR_FSUSP_Msk

Force suspend

◆ USB_CNTR_FSUSP_Msk

#define USB_CNTR_FSUSP_Msk   (0x1U << USB_CNTR_FSUSP_Pos)

0x00000008

◆ USB_CNTR_FSUSP_Pos

#define USB_CNTR_FSUSP_Pos   (3U)

◆ USB_CNTR_LPMODE

#define USB_CNTR_LPMODE   USB_CNTR_LPMODE_Msk

Low-power mode

◆ USB_CNTR_LPMODE_Msk

#define USB_CNTR_LPMODE_Msk   (0x1U << USB_CNTR_LPMODE_Pos)

0x00000004

◆ USB_CNTR_LPMODE_Pos

#define USB_CNTR_LPMODE_Pos   (2U)

◆ USB_CNTR_PDWN

#define USB_CNTR_PDWN   USB_CNTR_PDWN_Msk

Power down

◆ USB_CNTR_PDWN_Msk

#define USB_CNTR_PDWN_Msk   (0x1U << USB_CNTR_PDWN_Pos)

0x00000002

◆ USB_CNTR_PDWN_Pos

#define USB_CNTR_PDWN_Pos   (1U)

◆ USB_CNTR_PMAOVRM

#define USB_CNTR_PMAOVRM   USB_CNTR_PMAOVRM_Msk

Packet Memory Area Over / Underrun Interrupt Mask

◆ USB_CNTR_PMAOVRM_Msk

#define USB_CNTR_PMAOVRM_Msk   (0x1U << USB_CNTR_PMAOVRM_Pos)

0x00004000

◆ USB_CNTR_PMAOVRM_Pos

#define USB_CNTR_PMAOVRM_Pos   (14U)

◆ USB_CNTR_RESETM

#define USB_CNTR_RESETM   USB_CNTR_RESETM_Msk

RESET Interrupt Mask

◆ USB_CNTR_RESETM_Msk

#define USB_CNTR_RESETM_Msk   (0x1U << USB_CNTR_RESETM_Pos)

0x00000400

◆ USB_CNTR_RESETM_Pos

#define USB_CNTR_RESETM_Pos   (10U)

◆ USB_CNTR_RESUME

#define USB_CNTR_RESUME   USB_CNTR_RESUME_Msk

Resume request

◆ USB_CNTR_RESUME_Msk

#define USB_CNTR_RESUME_Msk   (0x1U << USB_CNTR_RESUME_Pos)

0x00000010

◆ USB_CNTR_RESUME_Pos

#define USB_CNTR_RESUME_Pos   (4U)

◆ USB_CNTR_SOFM

#define USB_CNTR_SOFM   USB_CNTR_SOFM_Msk

Start Of Frame Interrupt Mask

◆ USB_CNTR_SOFM_Msk

#define USB_CNTR_SOFM_Msk   (0x1U << USB_CNTR_SOFM_Pos)

0x00000200

◆ USB_CNTR_SOFM_Pos

#define USB_CNTR_SOFM_Pos   (9U)

◆ USB_CNTR_SUSPM

#define USB_CNTR_SUSPM   USB_CNTR_SUSPM_Msk

Suspend mode Interrupt Mask

◆ USB_CNTR_SUSPM_Msk

#define USB_CNTR_SUSPM_Msk   (0x1U << USB_CNTR_SUSPM_Pos)

0x00000800

◆ USB_CNTR_SUSPM_Pos

#define USB_CNTR_SUSPM_Pos   (11U)

◆ USB_CNTR_WKUPM

#define USB_CNTR_WKUPM   USB_CNTR_WKUPM_Msk

Wakeup Interrupt Mask

◆ USB_CNTR_WKUPM_Msk

#define USB_CNTR_WKUPM_Msk   (0x1U << USB_CNTR_WKUPM_Pos)

0x00001000

◆ USB_CNTR_WKUPM_Pos

#define USB_CNTR_WKUPM_Pos   (12U)

◆ USB_COUNT0_RX_0_BLSIZE_0

#define USB_COUNT0_RX_0_BLSIZE_0   (0x00008000U)

BLock SIZE (low)

◆ USB_COUNT0_RX_0_COUNT0_RX_0

#define USB_COUNT0_RX_0_COUNT0_RX_0   (0x000003FFU)

Reception Byte Count (low)

◆ USB_COUNT0_RX_0_NUM_BLOCK_0

#define USB_COUNT0_RX_0_NUM_BLOCK_0   (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_0

#define USB_COUNT0_RX_0_NUM_BLOCK_0_0   (0x00000400U)

Bit 0

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_1

#define USB_COUNT0_RX_0_NUM_BLOCK_0_1   (0x00000800U)

Bit 1

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_2

#define USB_COUNT0_RX_0_NUM_BLOCK_0_2   (0x00001000U)

Bit 2

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_3

#define USB_COUNT0_RX_0_NUM_BLOCK_0_3   (0x00002000U)

Bit 3

◆ USB_COUNT0_RX_0_NUM_BLOCK_0_4

#define USB_COUNT0_RX_0_NUM_BLOCK_0_4   (0x00004000U)

Bit 4

◆ USB_COUNT0_RX_1_BLSIZE_1

#define USB_COUNT0_RX_1_BLSIZE_1   (0x80000000U)

BLock SIZE (high)

◆ USB_COUNT0_RX_1_COUNT0_RX_1

#define USB_COUNT0_RX_1_COUNT0_RX_1   (0x03FF0000U)

Reception Byte Count (high)

◆ USB_COUNT0_RX_1_NUM_BLOCK_1

#define USB_COUNT0_RX_1_NUM_BLOCK_1   (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_0

#define USB_COUNT0_RX_1_NUM_BLOCK_1_0   (0x04000000U)

Bit 1

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_1

#define USB_COUNT0_RX_1_NUM_BLOCK_1_1   (0x08000000U)

Bit 1

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_2

#define USB_COUNT0_RX_1_NUM_BLOCK_1_2   (0x10000000U)

Bit 2

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_3

#define USB_COUNT0_RX_1_NUM_BLOCK_1_3   (0x20000000U)

Bit 3

◆ USB_COUNT0_RX_1_NUM_BLOCK_1_4

#define USB_COUNT0_RX_1_NUM_BLOCK_1_4   (0x40000000U)

Bit 4

◆ USB_COUNT0_RX_BLSIZE

#define USB_COUNT0_RX_BLSIZE   USB_COUNT0_RX_BLSIZE_Msk

BLock SIZE

◆ USB_COUNT0_RX_BLSIZE_Msk

#define USB_COUNT0_RX_BLSIZE_Msk   (0x1U << USB_COUNT0_RX_BLSIZE_Pos)

0x00008000

◆ USB_COUNT0_RX_BLSIZE_Pos

#define USB_COUNT0_RX_BLSIZE_Pos   (15U)

◆ USB_COUNT0_RX_COUNT0_RX

#define USB_COUNT0_RX_COUNT0_RX   USB_COUNT0_RX_COUNT0_RX_Msk

Reception Byte Count

◆ USB_COUNT0_RX_COUNT0_RX_Msk

#define USB_COUNT0_RX_COUNT0_RX_Msk   (0x3FFU << USB_COUNT0_RX_COUNT0_RX_Pos)

0x000003FF

◆ USB_COUNT0_RX_COUNT0_RX_Pos

#define USB_COUNT0_RX_COUNT0_RX_Pos   (0U)

◆ USB_COUNT0_RX_NUM_BLOCK

#define USB_COUNT0_RX_NUM_BLOCK   USB_COUNT0_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

◆ USB_COUNT0_RX_NUM_BLOCK_0

#define USB_COUNT0_RX_NUM_BLOCK_0   (0x01U << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00000400

◆ USB_COUNT0_RX_NUM_BLOCK_1

#define USB_COUNT0_RX_NUM_BLOCK_1   (0x02U << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00000800

◆ USB_COUNT0_RX_NUM_BLOCK_2

#define USB_COUNT0_RX_NUM_BLOCK_2   (0x04U << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00001000

◆ USB_COUNT0_RX_NUM_BLOCK_3

#define USB_COUNT0_RX_NUM_BLOCK_3   (0x08U << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00002000

◆ USB_COUNT0_RX_NUM_BLOCK_4

#define USB_COUNT0_RX_NUM_BLOCK_4   (0x10U << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00004000

◆ USB_COUNT0_RX_NUM_BLOCK_Msk

#define USB_COUNT0_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT0_RX_NUM_BLOCK_Pos)

0x00007C00

◆ USB_COUNT0_RX_NUM_BLOCK_Pos

#define USB_COUNT0_RX_NUM_BLOCK_Pos   (10U)

◆ USB_COUNT0_TX_0_COUNT0_TX_0

#define USB_COUNT0_TX_0_COUNT0_TX_0   (0x000003FFU)

Transmission Byte Count 0 (low)

◆ USB_COUNT0_TX_1_COUNT0_TX_1

#define USB_COUNT0_TX_1_COUNT0_TX_1   (0x03FF0000U)

Transmission Byte Count 0 (high)

◆ USB_COUNT0_TX_COUNT0_TX

#define USB_COUNT0_TX_COUNT0_TX   USB_COUNT0_TX_COUNT0_TX_Msk

Transmission Byte Count 0

◆ USB_COUNT0_TX_COUNT0_TX_Msk

#define USB_COUNT0_TX_COUNT0_TX_Msk   (0x3FFU << USB_COUNT0_TX_COUNT0_TX_Pos)

0x000003FF

◆ USB_COUNT0_TX_COUNT0_TX_Pos

#define USB_COUNT0_TX_COUNT0_TX_Pos   (0U)

◆ USB_COUNT1_RX_0_BLSIZE_0

#define USB_COUNT1_RX_0_BLSIZE_0   (0x00008000U)

BLock SIZE (low)

◆ USB_COUNT1_RX_0_COUNT1_RX_0

#define USB_COUNT1_RX_0_COUNT1_RX_0   (0x000003FFU)

Reception Byte Count (low)

◆ USB_COUNT1_RX_0_NUM_BLOCK_0

#define USB_COUNT1_RX_0_NUM_BLOCK_0   (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_0

#define USB_COUNT1_RX_0_NUM_BLOCK_0_0   (0x00000400U)

Bit 0

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_1

#define USB_COUNT1_RX_0_NUM_BLOCK_0_1   (0x00000800U)

Bit 1

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_2

#define USB_COUNT1_RX_0_NUM_BLOCK_0_2   (0x00001000U)

Bit 2

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_3

#define USB_COUNT1_RX_0_NUM_BLOCK_0_3   (0x00002000U)

Bit 3

◆ USB_COUNT1_RX_0_NUM_BLOCK_0_4

#define USB_COUNT1_RX_0_NUM_BLOCK_0_4   (0x00004000U)

Bit 4

◆ USB_COUNT1_RX_1_BLSIZE_1

#define USB_COUNT1_RX_1_BLSIZE_1   (0x80000000U)

BLock SIZE (high)

◆ USB_COUNT1_RX_1_COUNT1_RX_1

#define USB_COUNT1_RX_1_COUNT1_RX_1   (0x03FF0000U)

Reception Byte Count (high)

◆ USB_COUNT1_RX_1_NUM_BLOCK_1

#define USB_COUNT1_RX_1_NUM_BLOCK_1   (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_0

#define USB_COUNT1_RX_1_NUM_BLOCK_1_0   (0x04000000U)

Bit 0

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_1

#define USB_COUNT1_RX_1_NUM_BLOCK_1_1   (0x08000000U)

Bit 1

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_2

#define USB_COUNT1_RX_1_NUM_BLOCK_1_2   (0x10000000U)

Bit 2

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_3

#define USB_COUNT1_RX_1_NUM_BLOCK_1_3   (0x20000000U)

Bit 3

◆ USB_COUNT1_RX_1_NUM_BLOCK_1_4

#define USB_COUNT1_RX_1_NUM_BLOCK_1_4   (0x40000000U)

Bit 4

◆ USB_COUNT1_RX_BLSIZE

#define USB_COUNT1_RX_BLSIZE   USB_COUNT1_RX_BLSIZE_Msk

BLock SIZE

◆ USB_COUNT1_RX_BLSIZE_Msk

#define USB_COUNT1_RX_BLSIZE_Msk   (0x1U << USB_COUNT1_RX_BLSIZE_Pos)

0x00008000

◆ USB_COUNT1_RX_BLSIZE_Pos

#define USB_COUNT1_RX_BLSIZE_Pos   (15U)

◆ USB_COUNT1_RX_COUNT1_RX

#define USB_COUNT1_RX_COUNT1_RX   USB_COUNT1_RX_COUNT1_RX_Msk

Reception Byte Count

◆ USB_COUNT1_RX_COUNT1_RX_Msk

#define USB_COUNT1_RX_COUNT1_RX_Msk   (0x3FFU << USB_COUNT1_RX_COUNT1_RX_Pos)

0x000003FF

◆ USB_COUNT1_RX_COUNT1_RX_Pos

#define USB_COUNT1_RX_COUNT1_RX_Pos   (0U)

◆ USB_COUNT1_RX_NUM_BLOCK

#define USB_COUNT1_RX_NUM_BLOCK   USB_COUNT1_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

◆ USB_COUNT1_RX_NUM_BLOCK_0

#define USB_COUNT1_RX_NUM_BLOCK_0   (0x01U << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00000400

◆ USB_COUNT1_RX_NUM_BLOCK_1

#define USB_COUNT1_RX_NUM_BLOCK_1   (0x02U << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00000800

◆ USB_COUNT1_RX_NUM_BLOCK_2

#define USB_COUNT1_RX_NUM_BLOCK_2   (0x04U << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00001000

◆ USB_COUNT1_RX_NUM_BLOCK_3

#define USB_COUNT1_RX_NUM_BLOCK_3   (0x08U << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00002000

◆ USB_COUNT1_RX_NUM_BLOCK_4

#define USB_COUNT1_RX_NUM_BLOCK_4   (0x10U << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00004000

◆ USB_COUNT1_RX_NUM_BLOCK_Msk

#define USB_COUNT1_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT1_RX_NUM_BLOCK_Pos)

0x00007C00

◆ USB_COUNT1_RX_NUM_BLOCK_Pos

#define USB_COUNT1_RX_NUM_BLOCK_Pos   (10U)

◆ USB_COUNT1_TX_0_COUNT1_TX_0

#define USB_COUNT1_TX_0_COUNT1_TX_0   (0x000003FFU)

Transmission Byte Count 1 (low)

◆ USB_COUNT1_TX_1_COUNT1_TX_1

#define USB_COUNT1_TX_1_COUNT1_TX_1   (0x03FF0000U)

Transmission Byte Count 1 (high)

◆ USB_COUNT1_TX_COUNT1_TX

#define USB_COUNT1_TX_COUNT1_TX   USB_COUNT1_TX_COUNT1_TX_Msk

Transmission Byte Count 1

◆ USB_COUNT1_TX_COUNT1_TX_Msk

#define USB_COUNT1_TX_COUNT1_TX_Msk   (0x3FFU << USB_COUNT1_TX_COUNT1_TX_Pos)

0x000003FF

◆ USB_COUNT1_TX_COUNT1_TX_Pos

#define USB_COUNT1_TX_COUNT1_TX_Pos   (0U)

◆ USB_COUNT2_RX_0_BLSIZE_0

#define USB_COUNT2_RX_0_BLSIZE_0   (0x00008000U)

BLock SIZE (low)

◆ USB_COUNT2_RX_0_COUNT2_RX_0

#define USB_COUNT2_RX_0_COUNT2_RX_0   (0x000003FFU)

Reception Byte Count (low)

◆ USB_COUNT2_RX_0_NUM_BLOCK_0

#define USB_COUNT2_RX_0_NUM_BLOCK_0   (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_0

#define USB_COUNT2_RX_0_NUM_BLOCK_0_0   (0x00000400U)

Bit 0

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_1

#define USB_COUNT2_RX_0_NUM_BLOCK_0_1   (0x00000800U)

Bit 1

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_2

#define USB_COUNT2_RX_0_NUM_BLOCK_0_2   (0x00001000U)

Bit 2

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_3

#define USB_COUNT2_RX_0_NUM_BLOCK_0_3   (0x00002000U)

Bit 3

◆ USB_COUNT2_RX_0_NUM_BLOCK_0_4

#define USB_COUNT2_RX_0_NUM_BLOCK_0_4   (0x00004000U)

Bit 4

◆ USB_COUNT2_RX_1_BLSIZE_1

#define USB_COUNT2_RX_1_BLSIZE_1   (0x80000000U)

BLock SIZE (high)

◆ USB_COUNT2_RX_1_COUNT2_RX_1

#define USB_COUNT2_RX_1_COUNT2_RX_1   (0x03FF0000U)

Reception Byte Count (high)

◆ USB_COUNT2_RX_1_NUM_BLOCK_1

#define USB_COUNT2_RX_1_NUM_BLOCK_1   (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_0

#define USB_COUNT2_RX_1_NUM_BLOCK_1_0   (0x04000000U)

Bit 0

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_1

#define USB_COUNT2_RX_1_NUM_BLOCK_1_1   (0x08000000U)

Bit 1

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_2

#define USB_COUNT2_RX_1_NUM_BLOCK_1_2   (0x10000000U)

Bit 2

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_3

#define USB_COUNT2_RX_1_NUM_BLOCK_1_3   (0x20000000U)

Bit 3

◆ USB_COUNT2_RX_1_NUM_BLOCK_1_4

#define USB_COUNT2_RX_1_NUM_BLOCK_1_4   (0x40000000U)

Bit 4

◆ USB_COUNT2_RX_BLSIZE

#define USB_COUNT2_RX_BLSIZE   USB_COUNT2_RX_BLSIZE_Msk

BLock SIZE

◆ USB_COUNT2_RX_BLSIZE_Msk

#define USB_COUNT2_RX_BLSIZE_Msk   (0x1U << USB_COUNT2_RX_BLSIZE_Pos)

0x00008000

◆ USB_COUNT2_RX_BLSIZE_Pos

#define USB_COUNT2_RX_BLSIZE_Pos   (15U)

◆ USB_COUNT2_RX_COUNT2_RX

#define USB_COUNT2_RX_COUNT2_RX   USB_COUNT2_RX_COUNT2_RX_Msk

Reception Byte Count

◆ USB_COUNT2_RX_COUNT2_RX_Msk

#define USB_COUNT2_RX_COUNT2_RX_Msk   (0x3FFU << USB_COUNT2_RX_COUNT2_RX_Pos)

0x000003FF

◆ USB_COUNT2_RX_COUNT2_RX_Pos

#define USB_COUNT2_RX_COUNT2_RX_Pos   (0U)

◆ USB_COUNT2_RX_NUM_BLOCK

#define USB_COUNT2_RX_NUM_BLOCK   USB_COUNT2_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

◆ USB_COUNT2_RX_NUM_BLOCK_0

#define USB_COUNT2_RX_NUM_BLOCK_0   (0x01U << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00000400

◆ USB_COUNT2_RX_NUM_BLOCK_1

#define USB_COUNT2_RX_NUM_BLOCK_1   (0x02U << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00000800

◆ USB_COUNT2_RX_NUM_BLOCK_2

#define USB_COUNT2_RX_NUM_BLOCK_2   (0x04U << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00001000

◆ USB_COUNT2_RX_NUM_BLOCK_3

#define USB_COUNT2_RX_NUM_BLOCK_3   (0x08U << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00002000

◆ USB_COUNT2_RX_NUM_BLOCK_4

#define USB_COUNT2_RX_NUM_BLOCK_4   (0x10U << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00004000

◆ USB_COUNT2_RX_NUM_BLOCK_Msk

#define USB_COUNT2_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT2_RX_NUM_BLOCK_Pos)

0x00007C00

◆ USB_COUNT2_RX_NUM_BLOCK_Pos

#define USB_COUNT2_RX_NUM_BLOCK_Pos   (10U)

◆ USB_COUNT2_TX_0_COUNT2_TX_0

#define USB_COUNT2_TX_0_COUNT2_TX_0   (0x000003FFU)

Transmission Byte Count 2 (low)

◆ USB_COUNT2_TX_1_COUNT2_TX_1

#define USB_COUNT2_TX_1_COUNT2_TX_1   (0x03FF0000U)

Transmission Byte Count 2 (high)

◆ USB_COUNT2_TX_COUNT2_TX

#define USB_COUNT2_TX_COUNT2_TX   USB_COUNT2_TX_COUNT2_TX_Msk

Transmission Byte Count 2

◆ USB_COUNT2_TX_COUNT2_TX_Msk

#define USB_COUNT2_TX_COUNT2_TX_Msk   (0x3FFU << USB_COUNT2_TX_COUNT2_TX_Pos)

0x000003FF

◆ USB_COUNT2_TX_COUNT2_TX_Pos

#define USB_COUNT2_TX_COUNT2_TX_Pos   (0U)

◆ USB_COUNT3_RX_0_BLSIZE_0

#define USB_COUNT3_RX_0_BLSIZE_0   (0x00008000U)

BLock SIZE (low)

◆ USB_COUNT3_RX_0_COUNT3_RX_0

#define USB_COUNT3_RX_0_COUNT3_RX_0   (0x000003FFU)

Reception Byte Count (low)

◆ USB_COUNT3_RX_0_NUM_BLOCK_0

#define USB_COUNT3_RX_0_NUM_BLOCK_0   (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_0

#define USB_COUNT3_RX_0_NUM_BLOCK_0_0   (0x00000400U)

Bit 0

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_1

#define USB_COUNT3_RX_0_NUM_BLOCK_0_1   (0x00000800U)

Bit 1

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_2

#define USB_COUNT3_RX_0_NUM_BLOCK_0_2   (0x00001000U)

Bit 2

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_3

#define USB_COUNT3_RX_0_NUM_BLOCK_0_3   (0x00002000U)

Bit 3

◆ USB_COUNT3_RX_0_NUM_BLOCK_0_4

#define USB_COUNT3_RX_0_NUM_BLOCK_0_4   (0x00004000U)

Bit 4

◆ USB_COUNT3_RX_1_BLSIZE_1

#define USB_COUNT3_RX_1_BLSIZE_1   (0x80000000U)

BLock SIZE (high)

◆ USB_COUNT3_RX_1_COUNT3_RX_1

#define USB_COUNT3_RX_1_COUNT3_RX_1   (0x03FF0000U)

Reception Byte Count (high)

◆ USB_COUNT3_RX_1_NUM_BLOCK_1

#define USB_COUNT3_RX_1_NUM_BLOCK_1   (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_0

#define USB_COUNT3_RX_1_NUM_BLOCK_1_0   (0x04000000U)

Bit 0

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_1

#define USB_COUNT3_RX_1_NUM_BLOCK_1_1   (0x08000000U)

Bit 1

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_2

#define USB_COUNT3_RX_1_NUM_BLOCK_1_2   (0x10000000U)

Bit 2

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_3

#define USB_COUNT3_RX_1_NUM_BLOCK_1_3   (0x20000000U)

Bit 3

◆ USB_COUNT3_RX_1_NUM_BLOCK_1_4

#define USB_COUNT3_RX_1_NUM_BLOCK_1_4   (0x40000000U)

Bit 4

◆ USB_COUNT3_RX_BLSIZE

#define USB_COUNT3_RX_BLSIZE   USB_COUNT3_RX_BLSIZE_Msk

BLock SIZE

◆ USB_COUNT3_RX_BLSIZE_Msk

#define USB_COUNT3_RX_BLSIZE_Msk   (0x1U << USB_COUNT3_RX_BLSIZE_Pos)

0x00008000

◆ USB_COUNT3_RX_BLSIZE_Pos

#define USB_COUNT3_RX_BLSIZE_Pos   (15U)

◆ USB_COUNT3_RX_COUNT3_RX

#define USB_COUNT3_RX_COUNT3_RX   USB_COUNT3_RX_COUNT3_RX_Msk

Reception Byte Count

◆ USB_COUNT3_RX_COUNT3_RX_Msk

#define USB_COUNT3_RX_COUNT3_RX_Msk   (0x3FFU << USB_COUNT3_RX_COUNT3_RX_Pos)

0x000003FF

◆ USB_COUNT3_RX_COUNT3_RX_Pos

#define USB_COUNT3_RX_COUNT3_RX_Pos   (0U)

◆ USB_COUNT3_RX_NUM_BLOCK

#define USB_COUNT3_RX_NUM_BLOCK   USB_COUNT3_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

◆ USB_COUNT3_RX_NUM_BLOCK_0

#define USB_COUNT3_RX_NUM_BLOCK_0   (0x01U << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00000400

◆ USB_COUNT3_RX_NUM_BLOCK_1

#define USB_COUNT3_RX_NUM_BLOCK_1   (0x02U << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00000800

◆ USB_COUNT3_RX_NUM_BLOCK_2

#define USB_COUNT3_RX_NUM_BLOCK_2   (0x04U << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00001000

◆ USB_COUNT3_RX_NUM_BLOCK_3

#define USB_COUNT3_RX_NUM_BLOCK_3   (0x08U << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00002000

◆ USB_COUNT3_RX_NUM_BLOCK_4

#define USB_COUNT3_RX_NUM_BLOCK_4   (0x10U << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00004000

◆ USB_COUNT3_RX_NUM_BLOCK_Msk

#define USB_COUNT3_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT3_RX_NUM_BLOCK_Pos)

0x00007C00

◆ USB_COUNT3_RX_NUM_BLOCK_Pos

#define USB_COUNT3_RX_NUM_BLOCK_Pos   (10U)

◆ USB_COUNT3_TX_0_COUNT3_TX_0

#define USB_COUNT3_TX_0_COUNT3_TX_0   ((uint32_t)0x00000000U03FF)

Transmission Byte Count 3 (low)

◆ USB_COUNT3_TX_1_COUNT3_TX_1

#define USB_COUNT3_TX_1_COUNT3_TX_1   ((uint32_t)0x000003FFU0000)

Transmission Byte Count 3 (high)

◆ USB_COUNT3_TX_COUNT3_TX

#define USB_COUNT3_TX_COUNT3_TX   USB_COUNT3_TX_COUNT3_TX_Msk

Transmission Byte Count 3

◆ USB_COUNT3_TX_COUNT3_TX_Msk

#define USB_COUNT3_TX_COUNT3_TX_Msk   (0x3FFU << USB_COUNT3_TX_COUNT3_TX_Pos)

0x000003FF

◆ USB_COUNT3_TX_COUNT3_TX_Pos

#define USB_COUNT3_TX_COUNT3_TX_Pos   (0U)

◆ USB_COUNT4_RX_0_BLSIZE_0

#define USB_COUNT4_RX_0_BLSIZE_0   (0x00008000U)

BLock SIZE (low)

◆ USB_COUNT4_RX_0_COUNT4_RX_0

#define USB_COUNT4_RX_0_COUNT4_RX_0   (0x000003FFU)

Reception Byte Count (low)

◆ USB_COUNT4_RX_0_NUM_BLOCK_0

#define USB_COUNT4_RX_0_NUM_BLOCK_0   (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_0

#define USB_COUNT4_RX_0_NUM_BLOCK_0_0   (0x00000400U)

Bit 0

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_1

#define USB_COUNT4_RX_0_NUM_BLOCK_0_1   (0x00000800U)

Bit 1

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_2

#define USB_COUNT4_RX_0_NUM_BLOCK_0_2   (0x00001000U)

Bit 2

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_3

#define USB_COUNT4_RX_0_NUM_BLOCK_0_3   (0x00002000U)

Bit 3

◆ USB_COUNT4_RX_0_NUM_BLOCK_0_4

#define USB_COUNT4_RX_0_NUM_BLOCK_0_4   (0x00004000U)

Bit 4

◆ USB_COUNT4_RX_1_BLSIZE_1

#define USB_COUNT4_RX_1_BLSIZE_1   (0x80000000U)

BLock SIZE (high)

◆ USB_COUNT4_RX_1_COUNT4_RX_1

#define USB_COUNT4_RX_1_COUNT4_RX_1   (0x03FF0000U)

Reception Byte Count (high)

◆ USB_COUNT4_RX_1_NUM_BLOCK_1

#define USB_COUNT4_RX_1_NUM_BLOCK_1   (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_0

#define USB_COUNT4_RX_1_NUM_BLOCK_1_0   (0x04000000U)

Bit 0

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_1

#define USB_COUNT4_RX_1_NUM_BLOCK_1_1   (0x08000000U)

Bit 1

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_2

#define USB_COUNT4_RX_1_NUM_BLOCK_1_2   (0x10000000U)

Bit 2

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_3

#define USB_COUNT4_RX_1_NUM_BLOCK_1_3   (0x20000000U)

Bit 3

◆ USB_COUNT4_RX_1_NUM_BLOCK_1_4

#define USB_COUNT4_RX_1_NUM_BLOCK_1_4   (0x40000000U)

Bit 4

◆ USB_COUNT4_RX_BLSIZE

#define USB_COUNT4_RX_BLSIZE   USB_COUNT4_RX_BLSIZE_Msk

BLock SIZE

◆ USB_COUNT4_RX_BLSIZE_Msk

#define USB_COUNT4_RX_BLSIZE_Msk   (0x1U << USB_COUNT4_RX_BLSIZE_Pos)

0x00008000

◆ USB_COUNT4_RX_BLSIZE_Pos

#define USB_COUNT4_RX_BLSIZE_Pos   (15U)

◆ USB_COUNT4_RX_COUNT4_RX

#define USB_COUNT4_RX_COUNT4_RX   USB_COUNT4_RX_COUNT4_RX_Msk

Reception Byte Count

◆ USB_COUNT4_RX_COUNT4_RX_Msk

#define USB_COUNT4_RX_COUNT4_RX_Msk   (0x3FFU << USB_COUNT4_RX_COUNT4_RX_Pos)

0x000003FF

◆ USB_COUNT4_RX_COUNT4_RX_Pos

#define USB_COUNT4_RX_COUNT4_RX_Pos   (0U)

◆ USB_COUNT4_RX_NUM_BLOCK

#define USB_COUNT4_RX_NUM_BLOCK   USB_COUNT4_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

◆ USB_COUNT4_RX_NUM_BLOCK_0

#define USB_COUNT4_RX_NUM_BLOCK_0   (0x01U << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00000400

◆ USB_COUNT4_RX_NUM_BLOCK_1

#define USB_COUNT4_RX_NUM_BLOCK_1   (0x02U << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00000800

◆ USB_COUNT4_RX_NUM_BLOCK_2

#define USB_COUNT4_RX_NUM_BLOCK_2   (0x04U << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00001000

◆ USB_COUNT4_RX_NUM_BLOCK_3

#define USB_COUNT4_RX_NUM_BLOCK_3   (0x08U << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00002000

◆ USB_COUNT4_RX_NUM_BLOCK_4

#define USB_COUNT4_RX_NUM_BLOCK_4   (0x10U << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00004000

◆ USB_COUNT4_RX_NUM_BLOCK_Msk

#define USB_COUNT4_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT4_RX_NUM_BLOCK_Pos)

0x00007C00

◆ USB_COUNT4_RX_NUM_BLOCK_Pos

#define USB_COUNT4_RX_NUM_BLOCK_Pos   (10U)

◆ USB_COUNT4_TX_0_COUNT4_TX_0

#define USB_COUNT4_TX_0_COUNT4_TX_0   (0x000003FFU)

Transmission Byte Count 4 (low)

◆ USB_COUNT4_TX_1_COUNT4_TX_1

#define USB_COUNT4_TX_1_COUNT4_TX_1   (0x03FF0000U)

Transmission Byte Count 4 (high)

◆ USB_COUNT4_TX_COUNT4_TX

#define USB_COUNT4_TX_COUNT4_TX   USB_COUNT4_TX_COUNT4_TX_Msk

Transmission Byte Count 4

◆ USB_COUNT4_TX_COUNT4_TX_Msk

#define USB_COUNT4_TX_COUNT4_TX_Msk   (0x3FFU << USB_COUNT4_TX_COUNT4_TX_Pos)

0x000003FF

◆ USB_COUNT4_TX_COUNT4_TX_Pos

#define USB_COUNT4_TX_COUNT4_TX_Pos   (0U)

◆ USB_COUNT5_RX_0_BLSIZE_0

#define USB_COUNT5_RX_0_BLSIZE_0   (0x00008000U)

BLock SIZE (low)

◆ USB_COUNT5_RX_0_COUNT5_RX_0

#define USB_COUNT5_RX_0_COUNT5_RX_0   (0x000003FFU)

Reception Byte Count (low)

◆ USB_COUNT5_RX_0_NUM_BLOCK_0

#define USB_COUNT5_RX_0_NUM_BLOCK_0   (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_0

#define USB_COUNT5_RX_0_NUM_BLOCK_0_0   (0x00000400U)

Bit 0

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_1

#define USB_COUNT5_RX_0_NUM_BLOCK_0_1   (0x00000800U)

Bit 1

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_2

#define USB_COUNT5_RX_0_NUM_BLOCK_0_2   (0x00001000U)

Bit 2

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_3

#define USB_COUNT5_RX_0_NUM_BLOCK_0_3   (0x00002000U)

Bit 3

◆ USB_COUNT5_RX_0_NUM_BLOCK_0_4

#define USB_COUNT5_RX_0_NUM_BLOCK_0_4   (0x00004000U)

Bit 4

◆ USB_COUNT5_RX_1_BLSIZE_1

#define USB_COUNT5_RX_1_BLSIZE_1   (0x80000000U)

BLock SIZE (high)

◆ USB_COUNT5_RX_1_COUNT5_RX_1

#define USB_COUNT5_RX_1_COUNT5_RX_1   (0x03FF0000U)

Reception Byte Count (high)

◆ USB_COUNT5_RX_1_NUM_BLOCK_1

#define USB_COUNT5_RX_1_NUM_BLOCK_1   (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_0

#define USB_COUNT5_RX_1_NUM_BLOCK_1_0   (0x04000000U)

Bit 0

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_1

#define USB_COUNT5_RX_1_NUM_BLOCK_1_1   (0x08000000U)

Bit 1

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_2

#define USB_COUNT5_RX_1_NUM_BLOCK_1_2   (0x10000000U)

Bit 2

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_3

#define USB_COUNT5_RX_1_NUM_BLOCK_1_3   (0x20000000U)

Bit 3

◆ USB_COUNT5_RX_1_NUM_BLOCK_1_4

#define USB_COUNT5_RX_1_NUM_BLOCK_1_4   (0x40000000U)

Bit 4

◆ USB_COUNT5_RX_BLSIZE

#define USB_COUNT5_RX_BLSIZE   USB_COUNT5_RX_BLSIZE_Msk

BLock SIZE

◆ USB_COUNT5_RX_BLSIZE_Msk

#define USB_COUNT5_RX_BLSIZE_Msk   (0x1U << USB_COUNT5_RX_BLSIZE_Pos)

0x00008000

◆ USB_COUNT5_RX_BLSIZE_Pos

#define USB_COUNT5_RX_BLSIZE_Pos   (15U)

◆ USB_COUNT5_RX_COUNT5_RX

#define USB_COUNT5_RX_COUNT5_RX   USB_COUNT5_RX_COUNT5_RX_Msk

Reception Byte Count

◆ USB_COUNT5_RX_COUNT5_RX_Msk

#define USB_COUNT5_RX_COUNT5_RX_Msk   (0x3FFU << USB_COUNT5_RX_COUNT5_RX_Pos)

0x000003FF

◆ USB_COUNT5_RX_COUNT5_RX_Pos

#define USB_COUNT5_RX_COUNT5_RX_Pos   (0U)

◆ USB_COUNT5_RX_NUM_BLOCK

#define USB_COUNT5_RX_NUM_BLOCK   USB_COUNT5_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

◆ USB_COUNT5_RX_NUM_BLOCK_0

#define USB_COUNT5_RX_NUM_BLOCK_0   (0x01U << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00000400

◆ USB_COUNT5_RX_NUM_BLOCK_1

#define USB_COUNT5_RX_NUM_BLOCK_1   (0x02U << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00000800

◆ USB_COUNT5_RX_NUM_BLOCK_2

#define USB_COUNT5_RX_NUM_BLOCK_2   (0x04U << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00001000

◆ USB_COUNT5_RX_NUM_BLOCK_3

#define USB_COUNT5_RX_NUM_BLOCK_3   (0x08U << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00002000

◆ USB_COUNT5_RX_NUM_BLOCK_4

#define USB_COUNT5_RX_NUM_BLOCK_4   (0x10U << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00004000

◆ USB_COUNT5_RX_NUM_BLOCK_Msk

#define USB_COUNT5_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT5_RX_NUM_BLOCK_Pos)

0x00007C00

◆ USB_COUNT5_RX_NUM_BLOCK_Pos

#define USB_COUNT5_RX_NUM_BLOCK_Pos   (10U)

◆ USB_COUNT5_TX_0_COUNT5_TX_0

#define USB_COUNT5_TX_0_COUNT5_TX_0   (0x000003FFU)

Transmission Byte Count 5 (low)

◆ USB_COUNT5_TX_1_COUNT5_TX_1

#define USB_COUNT5_TX_1_COUNT5_TX_1   (0x03FF0000U)

Transmission Byte Count 5 (high)

◆ USB_COUNT5_TX_COUNT5_TX

#define USB_COUNT5_TX_COUNT5_TX   USB_COUNT5_TX_COUNT5_TX_Msk

Transmission Byte Count 5

◆ USB_COUNT5_TX_COUNT5_TX_Msk

#define USB_COUNT5_TX_COUNT5_TX_Msk   (0x3FFU << USB_COUNT5_TX_COUNT5_TX_Pos)

0x000003FF

◆ USB_COUNT5_TX_COUNT5_TX_Pos

#define USB_COUNT5_TX_COUNT5_TX_Pos   (0U)

◆ USB_COUNT6_RX_0_BLSIZE_0

#define USB_COUNT6_RX_0_BLSIZE_0   (0x00008000U)

BLock SIZE (low)

◆ USB_COUNT6_RX_0_COUNT6_RX_0

#define USB_COUNT6_RX_0_COUNT6_RX_0   (0x000003FFU)

Reception Byte Count (low)

◆ USB_COUNT6_RX_0_NUM_BLOCK_0

#define USB_COUNT6_RX_0_NUM_BLOCK_0   (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_0

#define USB_COUNT6_RX_0_NUM_BLOCK_0_0   (0x00000400U)

Bit 0

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_1

#define USB_COUNT6_RX_0_NUM_BLOCK_0_1   (0x00000800U)

Bit 1

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_2

#define USB_COUNT6_RX_0_NUM_BLOCK_0_2   (0x00001000U)

Bit 2

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_3

#define USB_COUNT6_RX_0_NUM_BLOCK_0_3   (0x00002000U)

Bit 3

◆ USB_COUNT6_RX_0_NUM_BLOCK_0_4

#define USB_COUNT6_RX_0_NUM_BLOCK_0_4   (0x00004000U)

Bit 4

◆ USB_COUNT6_RX_1_BLSIZE_1

#define USB_COUNT6_RX_1_BLSIZE_1   (0x80000000U)

BLock SIZE (high)

◆ USB_COUNT6_RX_1_COUNT6_RX_1

#define USB_COUNT6_RX_1_COUNT6_RX_1   (0x03FF0000U)

Reception Byte Count (high)

◆ USB_COUNT6_RX_1_NUM_BLOCK_1

#define USB_COUNT6_RX_1_NUM_BLOCK_1   (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_0

#define USB_COUNT6_RX_1_NUM_BLOCK_1_0   (0x04000000U)

Bit 0

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_1

#define USB_COUNT6_RX_1_NUM_BLOCK_1_1   (0x08000000U)

Bit 1

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_2

#define USB_COUNT6_RX_1_NUM_BLOCK_1_2   (0x10000000U)

Bit 2

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_3

#define USB_COUNT6_RX_1_NUM_BLOCK_1_3   (0x20000000U)

Bit 3

◆ USB_COUNT6_RX_1_NUM_BLOCK_1_4

#define USB_COUNT6_RX_1_NUM_BLOCK_1_4   (0x40000000U)

Bit 4

◆ USB_COUNT6_RX_BLSIZE

#define USB_COUNT6_RX_BLSIZE   USB_COUNT6_RX_BLSIZE_Msk

BLock SIZE

◆ USB_COUNT6_RX_BLSIZE_Msk

#define USB_COUNT6_RX_BLSIZE_Msk   (0x1U << USB_COUNT6_RX_BLSIZE_Pos)

0x00008000

◆ USB_COUNT6_RX_BLSIZE_Pos

#define USB_COUNT6_RX_BLSIZE_Pos   (15U)

◆ USB_COUNT6_RX_COUNT6_RX

#define USB_COUNT6_RX_COUNT6_RX   USB_COUNT6_RX_COUNT6_RX_Msk

Reception Byte Count

◆ USB_COUNT6_RX_COUNT6_RX_Msk

#define USB_COUNT6_RX_COUNT6_RX_Msk   (0x3FFU << USB_COUNT6_RX_COUNT6_RX_Pos)

0x000003FF

◆ USB_COUNT6_RX_COUNT6_RX_Pos

#define USB_COUNT6_RX_COUNT6_RX_Pos   (0U)

◆ USB_COUNT6_RX_NUM_BLOCK

#define USB_COUNT6_RX_NUM_BLOCK   USB_COUNT6_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

◆ USB_COUNT6_RX_NUM_BLOCK_0

#define USB_COUNT6_RX_NUM_BLOCK_0   (0x01U << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00000400

◆ USB_COUNT6_RX_NUM_BLOCK_1

#define USB_COUNT6_RX_NUM_BLOCK_1   (0x02U << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00000800

◆ USB_COUNT6_RX_NUM_BLOCK_2

#define USB_COUNT6_RX_NUM_BLOCK_2   (0x04U << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00001000

◆ USB_COUNT6_RX_NUM_BLOCK_3

#define USB_COUNT6_RX_NUM_BLOCK_3   (0x08U << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00002000

◆ USB_COUNT6_RX_NUM_BLOCK_4

#define USB_COUNT6_RX_NUM_BLOCK_4   (0x10U << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00004000

◆ USB_COUNT6_RX_NUM_BLOCK_Msk

#define USB_COUNT6_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT6_RX_NUM_BLOCK_Pos)

0x00007C00

◆ USB_COUNT6_RX_NUM_BLOCK_Pos

#define USB_COUNT6_RX_NUM_BLOCK_Pos   (10U)

◆ USB_COUNT6_TX_0_COUNT6_TX_0

#define USB_COUNT6_TX_0_COUNT6_TX_0   (0x000003FFU)

Transmission Byte Count 6 (low)

◆ USB_COUNT6_TX_1_COUNT6_TX_1

#define USB_COUNT6_TX_1_COUNT6_TX_1   (0x03FF0000U)

Transmission Byte Count 6 (high)

◆ USB_COUNT6_TX_COUNT6_TX

#define USB_COUNT6_TX_COUNT6_TX   USB_COUNT6_TX_COUNT6_TX_Msk

Transmission Byte Count 6

◆ USB_COUNT6_TX_COUNT6_TX_Msk

#define USB_COUNT6_TX_COUNT6_TX_Msk   (0x3FFU << USB_COUNT6_TX_COUNT6_TX_Pos)

0x000003FF

◆ USB_COUNT6_TX_COUNT6_TX_Pos

#define USB_COUNT6_TX_COUNT6_TX_Pos   (0U)

◆ USB_COUNT7_RX_0_BLSIZE_0

#define USB_COUNT7_RX_0_BLSIZE_0   (0x00008000U)

BLock SIZE (low)

◆ USB_COUNT7_RX_0_COUNT7_RX_0

#define USB_COUNT7_RX_0_COUNT7_RX_0   (0x000003FFU)

Reception Byte Count (low)

◆ USB_COUNT7_RX_0_NUM_BLOCK_0

#define USB_COUNT7_RX_0_NUM_BLOCK_0   (0x00007C00U)

NUM_BLOCK_0[4:0] bits (Number of blocks) (low)

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_0

#define USB_COUNT7_RX_0_NUM_BLOCK_0_0   (0x00000400U)

Bit 0

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_1

#define USB_COUNT7_RX_0_NUM_BLOCK_0_1   (0x00000800U)

Bit 1

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_2

#define USB_COUNT7_RX_0_NUM_BLOCK_0_2   (0x00001000U)

Bit 2

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_3

#define USB_COUNT7_RX_0_NUM_BLOCK_0_3   (0x00002000U)

Bit 3

◆ USB_COUNT7_RX_0_NUM_BLOCK_0_4

#define USB_COUNT7_RX_0_NUM_BLOCK_0_4   (0x00004000U)

Bit 4

◆ USB_COUNT7_RX_1_BLSIZE_1

#define USB_COUNT7_RX_1_BLSIZE_1   (0x80000000U)

BLock SIZE (high)

◆ USB_COUNT7_RX_1_COUNT7_RX_1

#define USB_COUNT7_RX_1_COUNT7_RX_1   (0x03FF0000U)

Reception Byte Count (high)

◆ USB_COUNT7_RX_1_NUM_BLOCK_1

#define USB_COUNT7_RX_1_NUM_BLOCK_1   (0x7C000000U)

NUM_BLOCK_1[4:0] bits (Number of blocks) (high)

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_0

#define USB_COUNT7_RX_1_NUM_BLOCK_1_0   (0x04000000U)

Bit 0

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_1

#define USB_COUNT7_RX_1_NUM_BLOCK_1_1   (0x08000000U)

Bit 1

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_2

#define USB_COUNT7_RX_1_NUM_BLOCK_1_2   (0x10000000U)

Bit 2

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_3

#define USB_COUNT7_RX_1_NUM_BLOCK_1_3   (0x20000000U)

Bit 3

◆ USB_COUNT7_RX_1_NUM_BLOCK_1_4

#define USB_COUNT7_RX_1_NUM_BLOCK_1_4   (0x40000000U)

Bit 4

◆ USB_COUNT7_RX_BLSIZE

#define USB_COUNT7_RX_BLSIZE   USB_COUNT7_RX_BLSIZE_Msk

BLock SIZE

◆ USB_COUNT7_RX_BLSIZE_Msk

#define USB_COUNT7_RX_BLSIZE_Msk   (0x1U << USB_COUNT7_RX_BLSIZE_Pos)

0x00008000

◆ USB_COUNT7_RX_BLSIZE_Pos

#define USB_COUNT7_RX_BLSIZE_Pos   (15U)

◆ USB_COUNT7_RX_COUNT7_RX

#define USB_COUNT7_RX_COUNT7_RX   USB_COUNT7_RX_COUNT7_RX_Msk

Reception Byte Count

◆ USB_COUNT7_RX_COUNT7_RX_Msk

#define USB_COUNT7_RX_COUNT7_RX_Msk   (0x3FFU << USB_COUNT7_RX_COUNT7_RX_Pos)

0x000003FF

◆ USB_COUNT7_RX_COUNT7_RX_Pos

#define USB_COUNT7_RX_COUNT7_RX_Pos   (0U)

◆ USB_COUNT7_RX_NUM_BLOCK

#define USB_COUNT7_RX_NUM_BLOCK   USB_COUNT7_RX_NUM_BLOCK_Msk

NUM_BLOCK[4:0] bits (Number of blocks)

◆ USB_COUNT7_RX_NUM_BLOCK_0

#define USB_COUNT7_RX_NUM_BLOCK_0   (0x01U << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00000400

◆ USB_COUNT7_RX_NUM_BLOCK_1

#define USB_COUNT7_RX_NUM_BLOCK_1   (0x02U << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00000800

◆ USB_COUNT7_RX_NUM_BLOCK_2

#define USB_COUNT7_RX_NUM_BLOCK_2   (0x04U << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00001000

◆ USB_COUNT7_RX_NUM_BLOCK_3

#define USB_COUNT7_RX_NUM_BLOCK_3   (0x08U << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00002000

◆ USB_COUNT7_RX_NUM_BLOCK_4

#define USB_COUNT7_RX_NUM_BLOCK_4   (0x10U << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00004000

◆ USB_COUNT7_RX_NUM_BLOCK_Msk

#define USB_COUNT7_RX_NUM_BLOCK_Msk   (0x1FU << USB_COUNT7_RX_NUM_BLOCK_Pos)

0x00007C00

◆ USB_COUNT7_RX_NUM_BLOCK_Pos

#define USB_COUNT7_RX_NUM_BLOCK_Pos   (10U)

◆ USB_COUNT7_TX_0_COUNT7_TX_0

#define USB_COUNT7_TX_0_COUNT7_TX_0   (0x000003FFU)

Transmission Byte Count 7 (low)

◆ USB_COUNT7_TX_1_COUNT7_TX_1

#define USB_COUNT7_TX_1_COUNT7_TX_1   (0x03FF0000U)

Transmission Byte Count 7 (high)

◆ USB_COUNT7_TX_COUNT7_TX

#define USB_COUNT7_TX_COUNT7_TX   USB_COUNT7_TX_COUNT7_TX_Msk

Transmission Byte Count 7

◆ USB_COUNT7_TX_COUNT7_TX_Msk

#define USB_COUNT7_TX_COUNT7_TX_Msk   (0x3FFU << USB_COUNT7_TX_COUNT7_TX_Pos)

0x000003FF

◆ USB_COUNT7_TX_COUNT7_TX_Pos

#define USB_COUNT7_TX_COUNT7_TX_Pos   (0U)

◆ USB_DADDR

#define USB_DADDR   (USB_BASE + 0x0000004CU)

Device address register

◆ USB_DADDR_ADD

#define USB_DADDR_ADD   USB_DADDR_ADD_Msk

ADD[6:0] bits (Device Address)

◆ USB_DADDR_ADD0

#define USB_DADDR_ADD0   USB_DADDR_ADD0_Msk

Bit 0

◆ USB_DADDR_ADD0_Msk

#define USB_DADDR_ADD0_Msk   (0x1U << USB_DADDR_ADD0_Pos)

0x00000001

◆ USB_DADDR_ADD0_Pos

#define USB_DADDR_ADD0_Pos   (0U)

◆ USB_DADDR_ADD1

#define USB_DADDR_ADD1   USB_DADDR_ADD1_Msk

Bit 1

◆ USB_DADDR_ADD1_Msk

#define USB_DADDR_ADD1_Msk   (0x1U << USB_DADDR_ADD1_Pos)

0x00000002

◆ USB_DADDR_ADD1_Pos

#define USB_DADDR_ADD1_Pos   (1U)

◆ USB_DADDR_ADD2

#define USB_DADDR_ADD2   USB_DADDR_ADD2_Msk

Bit 2

◆ USB_DADDR_ADD2_Msk

#define USB_DADDR_ADD2_Msk   (0x1U << USB_DADDR_ADD2_Pos)

0x00000004

◆ USB_DADDR_ADD2_Pos

#define USB_DADDR_ADD2_Pos   (2U)

◆ USB_DADDR_ADD3

#define USB_DADDR_ADD3   USB_DADDR_ADD3_Msk

Bit 3

◆ USB_DADDR_ADD3_Msk

#define USB_DADDR_ADD3_Msk   (0x1U << USB_DADDR_ADD3_Pos)

0x00000008

◆ USB_DADDR_ADD3_Pos

#define USB_DADDR_ADD3_Pos   (3U)

◆ USB_DADDR_ADD4

#define USB_DADDR_ADD4   USB_DADDR_ADD4_Msk

Bit 4

◆ USB_DADDR_ADD4_Msk

#define USB_DADDR_ADD4_Msk   (0x1U << USB_DADDR_ADD4_Pos)

0x00000010

◆ USB_DADDR_ADD4_Pos

#define USB_DADDR_ADD4_Pos   (4U)

◆ USB_DADDR_ADD5

#define USB_DADDR_ADD5   USB_DADDR_ADD5_Msk

Bit 5

◆ USB_DADDR_ADD5_Msk

#define USB_DADDR_ADD5_Msk   (0x1U << USB_DADDR_ADD5_Pos)

0x00000020

◆ USB_DADDR_ADD5_Pos

#define USB_DADDR_ADD5_Pos   (5U)

◆ USB_DADDR_ADD6

#define USB_DADDR_ADD6   USB_DADDR_ADD6_Msk

Bit 6

◆ USB_DADDR_ADD6_Msk

#define USB_DADDR_ADD6_Msk   (0x1U << USB_DADDR_ADD6_Pos)

0x00000040

◆ USB_DADDR_ADD6_Pos

#define USB_DADDR_ADD6_Pos   (6U)

◆ USB_DADDR_ADD_Msk

#define USB_DADDR_ADD_Msk   (0x7FU << USB_DADDR_ADD_Pos)

0x0000007F

◆ USB_DADDR_ADD_Pos

#define USB_DADDR_ADD_Pos   (0U)

◆ USB_DADDR_EF

#define USB_DADDR_EF   USB_DADDR_EF_Msk

Enable Function

◆ USB_DADDR_EF_Msk

#define USB_DADDR_EF_Msk   (0x1U << USB_DADDR_EF_Pos)

0x00000080

◆ USB_DADDR_EF_Pos

#define USB_DADDR_EF_Pos   (7U)

◆ USB_EP0R

#define USB_EP0R   USB_BASE

<Endpoint-specific registers endpoint 0 register address

◆ USB_EP0R_CTR_RX

#define USB_EP0R_CTR_RX   USB_EP0R_CTR_RX_Msk

Correct Transfer for reception

◆ USB_EP0R_CTR_RX_Msk

#define USB_EP0R_CTR_RX_Msk   (0x1U << USB_EP0R_CTR_RX_Pos)

0x00008000

◆ USB_EP0R_CTR_RX_Pos

#define USB_EP0R_CTR_RX_Pos   (15U)

◆ USB_EP0R_CTR_TX

#define USB_EP0R_CTR_TX   USB_EP0R_CTR_TX_Msk

Correct Transfer for transmission

◆ USB_EP0R_CTR_TX_Msk

#define USB_EP0R_CTR_TX_Msk   (0x1U << USB_EP0R_CTR_TX_Pos)

0x00000080

◆ USB_EP0R_CTR_TX_Pos

#define USB_EP0R_CTR_TX_Pos   (7U)

◆ USB_EP0R_DTOG_RX

#define USB_EP0R_DTOG_RX   USB_EP0R_DTOG_RX_Msk

Data Toggle, for reception transfers

◆ USB_EP0R_DTOG_RX_Msk

#define USB_EP0R_DTOG_RX_Msk   (0x1U << USB_EP0R_DTOG_RX_Pos)

0x00004000

◆ USB_EP0R_DTOG_RX_Pos

#define USB_EP0R_DTOG_RX_Pos   (14U)

◆ USB_EP0R_DTOG_TX

#define USB_EP0R_DTOG_TX   USB_EP0R_DTOG_TX_Msk

Data Toggle, for transmission transfers

◆ USB_EP0R_DTOG_TX_Msk

#define USB_EP0R_DTOG_TX_Msk   (0x1U << USB_EP0R_DTOG_TX_Pos)

0x00000040

◆ USB_EP0R_DTOG_TX_Pos

#define USB_EP0R_DTOG_TX_Pos   (6U)

◆ USB_EP0R_EA

#define USB_EP0R_EA   USB_EP0R_EA_Msk

Endpoint Address

◆ USB_EP0R_EA_Msk

#define USB_EP0R_EA_Msk   (0xFU << USB_EP0R_EA_Pos)

0x0000000F

◆ USB_EP0R_EA_Pos

#define USB_EP0R_EA_Pos   (0U)

◆ USB_EP0R_EP_KIND

#define USB_EP0R_EP_KIND   USB_EP0R_EP_KIND_Msk

Endpoint Kind

◆ USB_EP0R_EP_KIND_Msk

#define USB_EP0R_EP_KIND_Msk   (0x1U << USB_EP0R_EP_KIND_Pos)

0x00000100

◆ USB_EP0R_EP_KIND_Pos

#define USB_EP0R_EP_KIND_Pos   (8U)

◆ USB_EP0R_EP_TYPE

#define USB_EP0R_EP_TYPE   USB_EP0R_EP_TYPE_Msk

EP_TYPE[1:0] bits (Endpoint type)

◆ USB_EP0R_EP_TYPE_0

#define USB_EP0R_EP_TYPE_0   (0x1U << USB_EP0R_EP_TYPE_Pos)

0x00000200

◆ USB_EP0R_EP_TYPE_1

#define USB_EP0R_EP_TYPE_1   (0x2U << USB_EP0R_EP_TYPE_Pos)

0x00000400

◆ USB_EP0R_EP_TYPE_Msk

#define USB_EP0R_EP_TYPE_Msk   (0x3U << USB_EP0R_EP_TYPE_Pos)

0x00000600

◆ USB_EP0R_EP_TYPE_Pos

#define USB_EP0R_EP_TYPE_Pos   (9U)

◆ USB_EP0R_SETUP

#define USB_EP0R_SETUP   USB_EP0R_SETUP_Msk

Setup transaction completed

◆ USB_EP0R_SETUP_Msk

#define USB_EP0R_SETUP_Msk   (0x1U << USB_EP0R_SETUP_Pos)

0x00000800

◆ USB_EP0R_SETUP_Pos

#define USB_EP0R_SETUP_Pos   (11U)

◆ USB_EP0R_STAT_RX

#define USB_EP0R_STAT_RX   USB_EP0R_STAT_RX_Msk

STAT_RX[1:0] bits (Status bits, for reception transfers)

◆ USB_EP0R_STAT_RX_0

#define USB_EP0R_STAT_RX_0   (0x1U << USB_EP0R_STAT_RX_Pos)

0x00001000

◆ USB_EP0R_STAT_RX_1

#define USB_EP0R_STAT_RX_1   (0x2U << USB_EP0R_STAT_RX_Pos)

0x00002000

◆ USB_EP0R_STAT_RX_Msk

#define USB_EP0R_STAT_RX_Msk   (0x3U << USB_EP0R_STAT_RX_Pos)

0x00003000

◆ USB_EP0R_STAT_RX_Pos

#define USB_EP0R_STAT_RX_Pos   (12U)

◆ USB_EP0R_STAT_TX

#define USB_EP0R_STAT_TX   USB_EP0R_STAT_TX_Msk

STAT_TX[1:0] bits (Status bits, for transmission transfers)

◆ USB_EP0R_STAT_TX_0

#define USB_EP0R_STAT_TX_0   (0x1U << USB_EP0R_STAT_TX_Pos)

0x00000010

◆ USB_EP0R_STAT_TX_1

#define USB_EP0R_STAT_TX_1   (0x2U << USB_EP0R_STAT_TX_Pos)

0x00000020

◆ USB_EP0R_STAT_TX_Msk

#define USB_EP0R_STAT_TX_Msk   (0x3U << USB_EP0R_STAT_TX_Pos)

0x00000030

◆ USB_EP0R_STAT_TX_Pos

#define USB_EP0R_STAT_TX_Pos   (4U)

◆ USB_EP1R

#define USB_EP1R   (USB_BASE + 0x00000004U)

endpoint 1 register address

◆ USB_EP1R_CTR_RX

#define USB_EP1R_CTR_RX   USB_EP1R_CTR_RX_Msk

Correct Transfer for reception

◆ USB_EP1R_CTR_RX_Msk

#define USB_EP1R_CTR_RX_Msk   (0x1U << USB_EP1R_CTR_RX_Pos)

0x00008000

◆ USB_EP1R_CTR_RX_Pos

#define USB_EP1R_CTR_RX_Pos   (15U)

◆ USB_EP1R_CTR_TX

#define USB_EP1R_CTR_TX   USB_EP1R_CTR_TX_Msk

Correct Transfer for transmission

◆ USB_EP1R_CTR_TX_Msk

#define USB_EP1R_CTR_TX_Msk   (0x1U << USB_EP1R_CTR_TX_Pos)

0x00000080

◆ USB_EP1R_CTR_TX_Pos

#define USB_EP1R_CTR_TX_Pos   (7U)

◆ USB_EP1R_DTOG_RX

#define USB_EP1R_DTOG_RX   USB_EP1R_DTOG_RX_Msk

Data Toggle, for reception transfers

◆ USB_EP1R_DTOG_RX_Msk

#define USB_EP1R_DTOG_RX_Msk   (0x1U << USB_EP1R_DTOG_RX_Pos)

0x00004000

◆ USB_EP1R_DTOG_RX_Pos

#define USB_EP1R_DTOG_RX_Pos   (14U)

◆ USB_EP1R_DTOG_TX

#define USB_EP1R_DTOG_TX   USB_EP1R_DTOG_TX_Msk

Data Toggle, for transmission transfers

◆ USB_EP1R_DTOG_TX_Msk

#define USB_EP1R_DTOG_TX_Msk   (0x1U << USB_EP1R_DTOG_TX_Pos)

0x00000040

◆ USB_EP1R_DTOG_TX_Pos

#define USB_EP1R_DTOG_TX_Pos   (6U)

◆ USB_EP1R_EA

#define USB_EP1R_EA   USB_EP1R_EA_Msk

Endpoint Address

◆ USB_EP1R_EA_Msk

#define USB_EP1R_EA_Msk   (0xFU << USB_EP1R_EA_Pos)

0x0000000F

◆ USB_EP1R_EA_Pos

#define USB_EP1R_EA_Pos   (0U)

◆ USB_EP1R_EP_KIND

#define USB_EP1R_EP_KIND   USB_EP1R_EP_KIND_Msk

Endpoint Kind

◆ USB_EP1R_EP_KIND_Msk

#define USB_EP1R_EP_KIND_Msk   (0x1U << USB_EP1R_EP_KIND_Pos)

0x00000100

◆ USB_EP1R_EP_KIND_Pos

#define USB_EP1R_EP_KIND_Pos   (8U)

◆ USB_EP1R_EP_TYPE

#define USB_EP1R_EP_TYPE   USB_EP1R_EP_TYPE_Msk

EP_TYPE[1:0] bits (Endpoint type)

◆ USB_EP1R_EP_TYPE_0

#define USB_EP1R_EP_TYPE_0   (0x1U << USB_EP1R_EP_TYPE_Pos)

0x00000200

◆ USB_EP1R_EP_TYPE_1

#define USB_EP1R_EP_TYPE_1   (0x2U << USB_EP1R_EP_TYPE_Pos)

0x00000400

◆ USB_EP1R_EP_TYPE_Msk

#define USB_EP1R_EP_TYPE_Msk   (0x3U << USB_EP1R_EP_TYPE_Pos)

0x00000600

◆ USB_EP1R_EP_TYPE_Pos

#define USB_EP1R_EP_TYPE_Pos   (9U)

◆ USB_EP1R_SETUP

#define USB_EP1R_SETUP   USB_EP1R_SETUP_Msk

Setup transaction completed

◆ USB_EP1R_SETUP_Msk

#define USB_EP1R_SETUP_Msk   (0x1U << USB_EP1R_SETUP_Pos)

0x00000800

◆ USB_EP1R_SETUP_Pos

#define USB_EP1R_SETUP_Pos   (11U)

◆ USB_EP1R_STAT_RX

#define USB_EP1R_STAT_RX   USB_EP1R_STAT_RX_Msk

STAT_RX[1:0] bits (Status bits, for reception transfers)

◆ USB_EP1R_STAT_RX_0

#define USB_EP1R_STAT_RX_0   (0x1U << USB_EP1R_STAT_RX_Pos)

0x00001000

◆ USB_EP1R_STAT_RX_1

#define USB_EP1R_STAT_RX_1   (0x2U << USB_EP1R_STAT_RX_Pos)

0x00002000

◆ USB_EP1R_STAT_RX_Msk

#define USB_EP1R_STAT_RX_Msk   (0x3U << USB_EP1R_STAT_RX_Pos)

0x00003000

◆ USB_EP1R_STAT_RX_Pos

#define USB_EP1R_STAT_RX_Pos   (12U)

◆ USB_EP1R_STAT_TX

#define USB_EP1R_STAT_TX   USB_EP1R_STAT_TX_Msk

STAT_TX[1:0] bits (Status bits, for transmission transfers)

◆ USB_EP1R_STAT_TX_0

#define USB_EP1R_STAT_TX_0   (0x1U << USB_EP1R_STAT_TX_Pos)

0x00000010

◆ USB_EP1R_STAT_TX_1

#define USB_EP1R_STAT_TX_1   (0x2U << USB_EP1R_STAT_TX_Pos)

0x00000020

◆ USB_EP1R_STAT_TX_Msk

#define USB_EP1R_STAT_TX_Msk   (0x3U << USB_EP1R_STAT_TX_Pos)

0x00000030

◆ USB_EP1R_STAT_TX_Pos

#define USB_EP1R_STAT_TX_Pos   (4U)

◆ USB_EP2R

#define USB_EP2R   (USB_BASE + 0x00000008U)

endpoint 2 register address

◆ USB_EP2R_CTR_RX

#define USB_EP2R_CTR_RX   USB_EP2R_CTR_RX_Msk

Correct Transfer for reception

◆ USB_EP2R_CTR_RX_Msk

#define USB_EP2R_CTR_RX_Msk   (0x1U << USB_EP2R_CTR_RX_Pos)

0x00008000

◆ USB_EP2R_CTR_RX_Pos

#define USB_EP2R_CTR_RX_Pos   (15U)

◆ USB_EP2R_CTR_TX

#define USB_EP2R_CTR_TX   USB_EP2R_CTR_TX_Msk

Correct Transfer for transmission

◆ USB_EP2R_CTR_TX_Msk

#define USB_EP2R_CTR_TX_Msk   (0x1U << USB_EP2R_CTR_TX_Pos)

0x00000080

◆ USB_EP2R_CTR_TX_Pos

#define USB_EP2R_CTR_TX_Pos   (7U)

◆ USB_EP2R_DTOG_RX

#define USB_EP2R_DTOG_RX   USB_EP2R_DTOG_RX_Msk

Data Toggle, for reception transfers

◆ USB_EP2R_DTOG_RX_Msk

#define USB_EP2R_DTOG_RX_Msk   (0x1U << USB_EP2R_DTOG_RX_Pos)

0x00004000

◆ USB_EP2R_DTOG_RX_Pos

#define USB_EP2R_DTOG_RX_Pos   (14U)

◆ USB_EP2R_DTOG_TX

#define USB_EP2R_DTOG_TX   USB_EP2R_DTOG_TX_Msk

Data Toggle, for transmission transfers

◆ USB_EP2R_DTOG_TX_Msk

#define USB_EP2R_DTOG_TX_Msk   (0x1U << USB_EP2R_DTOG_TX_Pos)

0x00000040

◆ USB_EP2R_DTOG_TX_Pos

#define USB_EP2R_DTOG_TX_Pos   (6U)

◆ USB_EP2R_EA

#define USB_EP2R_EA   USB_EP2R_EA_Msk

Endpoint Address

◆ USB_EP2R_EA_Msk

#define USB_EP2R_EA_Msk   (0xFU << USB_EP2R_EA_Pos)

0x0000000F

◆ USB_EP2R_EA_Pos

#define USB_EP2R_EA_Pos   (0U)

◆ USB_EP2R_EP_KIND

#define USB_EP2R_EP_KIND   USB_EP2R_EP_KIND_Msk

Endpoint Kind

◆ USB_EP2R_EP_KIND_Msk

#define USB_EP2R_EP_KIND_Msk   (0x1U << USB_EP2R_EP_KIND_Pos)

0x00000100

◆ USB_EP2R_EP_KIND_Pos

#define USB_EP2R_EP_KIND_Pos   (8U)

◆ USB_EP2R_EP_TYPE

#define USB_EP2R_EP_TYPE   USB_EP2R_EP_TYPE_Msk

EP_TYPE[1:0] bits (Endpoint type)

◆ USB_EP2R_EP_TYPE_0

#define USB_EP2R_EP_TYPE_0   (0x1U << USB_EP2R_EP_TYPE_Pos)

0x00000200

◆ USB_EP2R_EP_TYPE_1

#define USB_EP2R_EP_TYPE_1   (0x2U << USB_EP2R_EP_TYPE_Pos)

0x00000400

◆ USB_EP2R_EP_TYPE_Msk

#define USB_EP2R_EP_TYPE_Msk   (0x3U << USB_EP2R_EP_TYPE_Pos)

0x00000600

◆ USB_EP2R_EP_TYPE_Pos

#define USB_EP2R_EP_TYPE_Pos   (9U)

◆ USB_EP2R_SETUP

#define USB_EP2R_SETUP   USB_EP2R_SETUP_Msk

Setup transaction completed

◆ USB_EP2R_SETUP_Msk

#define USB_EP2R_SETUP_Msk   (0x1U << USB_EP2R_SETUP_Pos)

0x00000800

◆ USB_EP2R_SETUP_Pos

#define USB_EP2R_SETUP_Pos   (11U)

◆ USB_EP2R_STAT_RX

#define USB_EP2R_STAT_RX   USB_EP2R_STAT_RX_Msk

STAT_RX[1:0] bits (Status bits, for reception transfers)

◆ USB_EP2R_STAT_RX_0

#define USB_EP2R_STAT_RX_0   (0x1U << USB_EP2R_STAT_RX_Pos)

0x00001000

◆ USB_EP2R_STAT_RX_1

#define USB_EP2R_STAT_RX_1   (0x2U << USB_EP2R_STAT_RX_Pos)

0x00002000

◆ USB_EP2R_STAT_RX_Msk

#define USB_EP2R_STAT_RX_Msk   (0x3U << USB_EP2R_STAT_RX_Pos)

0x00003000

◆ USB_EP2R_STAT_RX_Pos

#define USB_EP2R_STAT_RX_Pos   (12U)

◆ USB_EP2R_STAT_TX

#define USB_EP2R_STAT_TX   USB_EP2R_STAT_TX_Msk

STAT_TX[1:0] bits (Status bits, for transmission transfers)

◆ USB_EP2R_STAT_TX_0

#define USB_EP2R_STAT_TX_0   (0x1U << USB_EP2R_STAT_TX_Pos)

0x00000010

◆ USB_EP2R_STAT_TX_1

#define USB_EP2R_STAT_TX_1   (0x2U << USB_EP2R_STAT_TX_Pos)

0x00000020

◆ USB_EP2R_STAT_TX_Msk

#define USB_EP2R_STAT_TX_Msk   (0x3U << USB_EP2R_STAT_TX_Pos)

0x00000030

◆ USB_EP2R_STAT_TX_Pos

#define USB_EP2R_STAT_TX_Pos   (4U)

◆ USB_EP3R

#define USB_EP3R   (USB_BASE + 0x0000000CU)

endpoint 3 register address

◆ USB_EP3R_CTR_RX

#define USB_EP3R_CTR_RX   USB_EP3R_CTR_RX_Msk

Correct Transfer for reception

◆ USB_EP3R_CTR_RX_Msk

#define USB_EP3R_CTR_RX_Msk   (0x1U << USB_EP3R_CTR_RX_Pos)

0x00008000

◆ USB_EP3R_CTR_RX_Pos

#define USB_EP3R_CTR_RX_Pos   (15U)

◆ USB_EP3R_CTR_TX

#define USB_EP3R_CTR_TX   USB_EP3R_CTR_TX_Msk

Correct Transfer for transmission

◆ USB_EP3R_CTR_TX_Msk

#define USB_EP3R_CTR_TX_Msk   (0x1U << USB_EP3R_CTR_TX_Pos)

0x00000080

◆ USB_EP3R_CTR_TX_Pos

#define USB_EP3R_CTR_TX_Pos   (7U)

◆ USB_EP3R_DTOG_RX

#define USB_EP3R_DTOG_RX   USB_EP3R_DTOG_RX_Msk

Data Toggle, for reception transfers

◆ USB_EP3R_DTOG_RX_Msk

#define USB_EP3R_DTOG_RX_Msk   (0x1U << USB_EP3R_DTOG_RX_Pos)

0x00004000

◆ USB_EP3R_DTOG_RX_Pos

#define USB_EP3R_DTOG_RX_Pos   (14U)

◆ USB_EP3R_DTOG_TX

#define USB_EP3R_DTOG_TX   USB_EP3R_DTOG_TX_Msk

Data Toggle, for transmission transfers

◆ USB_EP3R_DTOG_TX_Msk

#define USB_EP3R_DTOG_TX_Msk   (0x1U << USB_EP3R_DTOG_TX_Pos)

0x00000040

◆ USB_EP3R_DTOG_TX_Pos

#define USB_EP3R_DTOG_TX_Pos   (6U)

◆ USB_EP3R_EA

#define USB_EP3R_EA   USB_EP3R_EA_Msk

Endpoint Address

◆ USB_EP3R_EA_Msk

#define USB_EP3R_EA_Msk   (0xFU << USB_EP3R_EA_Pos)

0x0000000F

◆ USB_EP3R_EA_Pos

#define USB_EP3R_EA_Pos   (0U)

◆ USB_EP3R_EP_KIND

#define USB_EP3R_EP_KIND   USB_EP3R_EP_KIND_Msk

Endpoint Kind

◆ USB_EP3R_EP_KIND_Msk

#define USB_EP3R_EP_KIND_Msk   (0x1U << USB_EP3R_EP_KIND_Pos)

0x00000100

◆ USB_EP3R_EP_KIND_Pos

#define USB_EP3R_EP_KIND_Pos   (8U)

◆ USB_EP3R_EP_TYPE

#define USB_EP3R_EP_TYPE   USB_EP3R_EP_TYPE_Msk

EP_TYPE[1:0] bits (Endpoint type)

◆ USB_EP3R_EP_TYPE_0

#define USB_EP3R_EP_TYPE_0   (0x1U << USB_EP3R_EP_TYPE_Pos)

0x00000200

◆ USB_EP3R_EP_TYPE_1

#define USB_EP3R_EP_TYPE_1   (0x2U << USB_EP3R_EP_TYPE_Pos)

0x00000400

◆ USB_EP3R_EP_TYPE_Msk

#define USB_EP3R_EP_TYPE_Msk   (0x3U << USB_EP3R_EP_TYPE_Pos)

0x00000600

◆ USB_EP3R_EP_TYPE_Pos

#define USB_EP3R_EP_TYPE_Pos   (9U)

◆ USB_EP3R_SETUP

#define USB_EP3R_SETUP   USB_EP3R_SETUP_Msk

Setup transaction completed

◆ USB_EP3R_SETUP_Msk

#define USB_EP3R_SETUP_Msk   (0x1U << USB_EP3R_SETUP_Pos)

0x00000800

◆ USB_EP3R_SETUP_Pos

#define USB_EP3R_SETUP_Pos   (11U)

◆ USB_EP3R_STAT_RX

#define USB_EP3R_STAT_RX   USB_EP3R_STAT_RX_Msk

STAT_RX[1:0] bits (Status bits, for reception transfers)

◆ USB_EP3R_STAT_RX_0

#define USB_EP3R_STAT_RX_0   (0x1U << USB_EP3R_STAT_RX_Pos)

0x00001000

◆ USB_EP3R_STAT_RX_1

#define USB_EP3R_STAT_RX_1   (0x2U << USB_EP3R_STAT_RX_Pos)

0x00002000

◆ USB_EP3R_STAT_RX_Msk

#define USB_EP3R_STAT_RX_Msk   (0x3U << USB_EP3R_STAT_RX_Pos)

0x00003000

◆ USB_EP3R_STAT_RX_Pos

#define USB_EP3R_STAT_RX_Pos   (12U)

◆ USB_EP3R_STAT_TX

#define USB_EP3R_STAT_TX   USB_EP3R_STAT_TX_Msk

STAT_TX[1:0] bits (Status bits, for transmission transfers)

◆ USB_EP3R_STAT_TX_0

#define USB_EP3R_STAT_TX_0   (0x1U << USB_EP3R_STAT_TX_Pos)

0x00000010

◆ USB_EP3R_STAT_TX_1

#define USB_EP3R_STAT_TX_1   (0x2U << USB_EP3R_STAT_TX_Pos)

0x00000020

◆ USB_EP3R_STAT_TX_Msk

#define USB_EP3R_STAT_TX_Msk   (0x3U << USB_EP3R_STAT_TX_Pos)

0x00000030

◆ USB_EP3R_STAT_TX_Pos

#define USB_EP3R_STAT_TX_Pos   (4U)

◆ USB_EP4R

#define USB_EP4R   (USB_BASE + 0x00000010U)

endpoint 4 register address

◆ USB_EP4R_CTR_RX

#define USB_EP4R_CTR_RX   USB_EP4R_CTR_RX_Msk

Correct Transfer for reception

◆ USB_EP4R_CTR_RX_Msk

#define USB_EP4R_CTR_RX_Msk   (0x1U << USB_EP4R_CTR_RX_Pos)

0x00008000

◆ USB_EP4R_CTR_RX_Pos

#define USB_EP4R_CTR_RX_Pos   (15U)

◆ USB_EP4R_CTR_TX

#define USB_EP4R_CTR_TX   USB_EP4R_CTR_TX_Msk

Correct Transfer for transmission

◆ USB_EP4R_CTR_TX_Msk

#define USB_EP4R_CTR_TX_Msk   (0x1U << USB_EP4R_CTR_TX_Pos)

0x00000080

◆ USB_EP4R_CTR_TX_Pos

#define USB_EP4R_CTR_TX_Pos   (7U)

◆ USB_EP4R_DTOG_RX

#define USB_EP4R_DTOG_RX   USB_EP4R_DTOG_RX_Msk

Data Toggle, for reception transfers

◆ USB_EP4R_DTOG_RX_Msk

#define USB_EP4R_DTOG_RX_Msk   (0x1U << USB_EP4R_DTOG_RX_Pos)

0x00004000

◆ USB_EP4R_DTOG_RX_Pos

#define USB_EP4R_DTOG_RX_Pos   (14U)

◆ USB_EP4R_DTOG_TX

#define USB_EP4R_DTOG_TX   USB_EP4R_DTOG_TX_Msk

Data Toggle, for transmission transfers

◆ USB_EP4R_DTOG_TX_Msk

#define USB_EP4R_DTOG_TX_Msk   (0x1U << USB_EP4R_DTOG_TX_Pos)

0x00000040

◆ USB_EP4R_DTOG_TX_Pos

#define USB_EP4R_DTOG_TX_Pos   (6U)

◆ USB_EP4R_EA

#define USB_EP4R_EA   USB_EP4R_EA_Msk

Endpoint Address

◆ USB_EP4R_EA_Msk

#define USB_EP4R_EA_Msk   (0xFU << USB_EP4R_EA_Pos)

0x0000000F

◆ USB_EP4R_EA_Pos

#define USB_EP4R_EA_Pos   (0U)

◆ USB_EP4R_EP_KIND

#define USB_EP4R_EP_KIND   USB_EP4R_EP_KIND_Msk

Endpoint Kind

◆ USB_EP4R_EP_KIND_Msk

#define USB_EP4R_EP_KIND_Msk   (0x1U << USB_EP4R_EP_KIND_Pos)

0x00000100

◆ USB_EP4R_EP_KIND_Pos

#define USB_EP4R_EP_KIND_Pos   (8U)

◆ USB_EP4R_EP_TYPE

#define USB_EP4R_EP_TYPE   USB_EP4R_EP_TYPE_Msk

EP_TYPE[1:0] bits (Endpoint type)

◆ USB_EP4R_EP_TYPE_0

#define USB_EP4R_EP_TYPE_0   (0x1U << USB_EP4R_EP_TYPE_Pos)

0x00000200

◆ USB_EP4R_EP_TYPE_1

#define USB_EP4R_EP_TYPE_1   (0x2U << USB_EP4R_EP_TYPE_Pos)

0x00000400

◆ USB_EP4R_EP_TYPE_Msk

#define USB_EP4R_EP_TYPE_Msk   (0x3U << USB_EP4R_EP_TYPE_Pos)

0x00000600

◆ USB_EP4R_EP_TYPE_Pos

#define USB_EP4R_EP_TYPE_Pos   (9U)

◆ USB_EP4R_SETUP

#define USB_EP4R_SETUP   USB_EP4R_SETUP_Msk

Setup transaction completed

◆ USB_EP4R_SETUP_Msk

#define USB_EP4R_SETUP_Msk   (0x1U << USB_EP4R_SETUP_Pos)

0x00000800

◆ USB_EP4R_SETUP_Pos

#define USB_EP4R_SETUP_Pos   (11U)

◆ USB_EP4R_STAT_RX

#define USB_EP4R_STAT_RX   USB_EP4R_STAT_RX_Msk

STAT_RX[1:0] bits (Status bits, for reception transfers)

◆ USB_EP4R_STAT_RX_0

#define USB_EP4R_STAT_RX_0   (0x1U << USB_EP4R_STAT_RX_Pos)

0x00001000

◆ USB_EP4R_STAT_RX_1

#define USB_EP4R_STAT_RX_1   (0x2U << USB_EP4R_STAT_RX_Pos)

0x00002000

◆ USB_EP4R_STAT_RX_Msk

#define USB_EP4R_STAT_RX_Msk   (0x3U << USB_EP4R_STAT_RX_Pos)

0x00003000

◆ USB_EP4R_STAT_RX_Pos

#define USB_EP4R_STAT_RX_Pos   (12U)

◆ USB_EP4R_STAT_TX

#define USB_EP4R_STAT_TX   USB_EP4R_STAT_TX_Msk

STAT_TX[1:0] bits (Status bits, for transmission transfers)

◆ USB_EP4R_STAT_TX_0

#define USB_EP4R_STAT_TX_0   (0x1U << USB_EP4R_STAT_TX_Pos)

0x00000010

◆ USB_EP4R_STAT_TX_1

#define USB_EP4R_STAT_TX_1   (0x2U << USB_EP4R_STAT_TX_Pos)

0x00000020

◆ USB_EP4R_STAT_TX_Msk

#define USB_EP4R_STAT_TX_Msk   (0x3U << USB_EP4R_STAT_TX_Pos)

0x00000030

◆ USB_EP4R_STAT_TX_Pos

#define USB_EP4R_STAT_TX_Pos   (4U)

◆ USB_EP5R

#define USB_EP5R   (USB_BASE + 0x00000014U)

endpoint 5 register address

◆ USB_EP5R_CTR_RX

#define USB_EP5R_CTR_RX   USB_EP5R_CTR_RX_Msk

Correct Transfer for reception

◆ USB_EP5R_CTR_RX_Msk

#define USB_EP5R_CTR_RX_Msk   (0x1U << USB_EP5R_CTR_RX_Pos)

0x00008000

◆ USB_EP5R_CTR_RX_Pos

#define USB_EP5R_CTR_RX_Pos   (15U)

◆ USB_EP5R_CTR_TX

#define USB_EP5R_CTR_TX   USB_EP5R_CTR_TX_Msk

Correct Transfer for transmission

◆ USB_EP5R_CTR_TX_Msk

#define USB_EP5R_CTR_TX_Msk   (0x1U << USB_EP5R_CTR_TX_Pos)

0x00000080

◆ USB_EP5R_CTR_TX_Pos

#define USB_EP5R_CTR_TX_Pos   (7U)

◆ USB_EP5R_DTOG_RX

#define USB_EP5R_DTOG_RX   USB_EP5R_DTOG_RX_Msk

Data Toggle, for reception transfers

◆ USB_EP5R_DTOG_RX_Msk

#define USB_EP5R_DTOG_RX_Msk   (0x1U << USB_EP5R_DTOG_RX_Pos)

0x00004000

◆ USB_EP5R_DTOG_RX_Pos

#define USB_EP5R_DTOG_RX_Pos   (14U)

◆ USB_EP5R_DTOG_TX

#define USB_EP5R_DTOG_TX   USB_EP5R_DTOG_TX_Msk

Data Toggle, for transmission transfers

◆ USB_EP5R_DTOG_TX_Msk

#define USB_EP5R_DTOG_TX_Msk   (0x1U << USB_EP5R_DTOG_TX_Pos)

0x00000040

◆ USB_EP5R_DTOG_TX_Pos

#define USB_EP5R_DTOG_TX_Pos   (6U)

◆ USB_EP5R_EA

#define USB_EP5R_EA   USB_EP5R_EA_Msk

Endpoint Address

◆ USB_EP5R_EA_Msk

#define USB_EP5R_EA_Msk   (0xFU << USB_EP5R_EA_Pos)

0x0000000F

◆ USB_EP5R_EA_Pos

#define USB_EP5R_EA_Pos   (0U)

◆ USB_EP5R_EP_KIND

#define USB_EP5R_EP_KIND   USB_EP5R_EP_KIND_Msk

Endpoint Kind

◆ USB_EP5R_EP_KIND_Msk

#define USB_EP5R_EP_KIND_Msk   (0x1U << USB_EP5R_EP_KIND_Pos)

0x00000100

◆ USB_EP5R_EP_KIND_Pos

#define USB_EP5R_EP_KIND_Pos   (8U)

◆ USB_EP5R_EP_TYPE

#define USB_EP5R_EP_TYPE   USB_EP5R_EP_TYPE_Msk

EP_TYPE[1:0] bits (Endpoint type)

◆ USB_EP5R_EP_TYPE_0

#define USB_EP5R_EP_TYPE_0   (0x1U << USB_EP5R_EP_TYPE_Pos)

0x00000200

◆ USB_EP5R_EP_TYPE_1

#define USB_EP5R_EP_TYPE_1   (0x2U << USB_EP5R_EP_TYPE_Pos)

0x00000400

◆ USB_EP5R_EP_TYPE_Msk

#define USB_EP5R_EP_TYPE_Msk   (0x3U << USB_EP5R_EP_TYPE_Pos)

0x00000600

◆ USB_EP5R_EP_TYPE_Pos

#define USB_EP5R_EP_TYPE_Pos   (9U)

◆ USB_EP5R_SETUP

#define USB_EP5R_SETUP   USB_EP5R_SETUP_Msk

Setup transaction completed

◆ USB_EP5R_SETUP_Msk

#define USB_EP5R_SETUP_Msk   (0x1U << USB_EP5R_SETUP_Pos)

0x00000800

◆ USB_EP5R_SETUP_Pos

#define USB_EP5R_SETUP_Pos   (11U)

◆ USB_EP5R_STAT_RX

#define USB_EP5R_STAT_RX   USB_EP5R_STAT_RX_Msk

STAT_RX[1:0] bits (Status bits, for reception transfers)

◆ USB_EP5R_STAT_RX_0

#define USB_EP5R_STAT_RX_0   (0x1U << USB_EP5R_STAT_RX_Pos)

0x00001000

◆ USB_EP5R_STAT_RX_1

#define USB_EP5R_STAT_RX_1   (0x2U << USB_EP5R_STAT_RX_Pos)

0x00002000

◆ USB_EP5R_STAT_RX_Msk

#define USB_EP5R_STAT_RX_Msk   (0x3U << USB_EP5R_STAT_RX_Pos)

0x00003000

◆ USB_EP5R_STAT_RX_Pos

#define USB_EP5R_STAT_RX_Pos   (12U)

◆ USB_EP5R_STAT_TX

#define USB_EP5R_STAT_TX   USB_EP5R_STAT_TX_Msk

STAT_TX[1:0] bits (Status bits, for transmission transfers)

◆ USB_EP5R_STAT_TX_0

#define USB_EP5R_STAT_TX_0   (0x1U << USB_EP5R_STAT_TX_Pos)

0x00000010

◆ USB_EP5R_STAT_TX_1

#define USB_EP5R_STAT_TX_1   (0x2U << USB_EP5R_STAT_TX_Pos)

0x00000020

◆ USB_EP5R_STAT_TX_Msk

#define USB_EP5R_STAT_TX_Msk   (0x3U << USB_EP5R_STAT_TX_Pos)

0x00000030

◆ USB_EP5R_STAT_TX_Pos

#define USB_EP5R_STAT_TX_Pos   (4U)

◆ USB_EP6R

#define USB_EP6R   (USB_BASE + 0x00000018U)

endpoint 6 register address

◆ USB_EP6R_CTR_RX

#define USB_EP6R_CTR_RX   USB_EP6R_CTR_RX_Msk

Correct Transfer for reception

◆ USB_EP6R_CTR_RX_Msk

#define USB_EP6R_CTR_RX_Msk   (0x1U << USB_EP6R_CTR_RX_Pos)

0x00008000

◆ USB_EP6R_CTR_RX_Pos

#define USB_EP6R_CTR_RX_Pos   (15U)

◆ USB_EP6R_CTR_TX

#define USB_EP6R_CTR_TX   USB_EP6R_CTR_TX_Msk

Correct Transfer for transmission

◆ USB_EP6R_CTR_TX_Msk

#define USB_EP6R_CTR_TX_Msk   (0x1U << USB_EP6R_CTR_TX_Pos)

0x00000080

◆ USB_EP6R_CTR_TX_Pos

#define USB_EP6R_CTR_TX_Pos   (7U)

◆ USB_EP6R_DTOG_RX

#define USB_EP6R_DTOG_RX   USB_EP6R_DTOG_RX_Msk

Data Toggle, for reception transfers

◆ USB_EP6R_DTOG_RX_Msk

#define USB_EP6R_DTOG_RX_Msk   (0x1U << USB_EP6R_DTOG_RX_Pos)

0x00004000

◆ USB_EP6R_DTOG_RX_Pos

#define USB_EP6R_DTOG_RX_Pos   (14U)

◆ USB_EP6R_DTOG_TX

#define USB_EP6R_DTOG_TX   USB_EP6R_DTOG_TX_Msk

Data Toggle, for transmission transfers

◆ USB_EP6R_DTOG_TX_Msk

#define USB_EP6R_DTOG_TX_Msk   (0x1U << USB_EP6R_DTOG_TX_Pos)

0x00000040

◆ USB_EP6R_DTOG_TX_Pos

#define USB_EP6R_DTOG_TX_Pos   (6U)

◆ USB_EP6R_EA

#define USB_EP6R_EA   USB_EP6R_EA_Msk

Endpoint Address

◆ USB_EP6R_EA_Msk

#define USB_EP6R_EA_Msk   (0xFU << USB_EP6R_EA_Pos)

0x0000000F

◆ USB_EP6R_EA_Pos

#define USB_EP6R_EA_Pos   (0U)

◆ USB_EP6R_EP_KIND

#define USB_EP6R_EP_KIND   USB_EP6R_EP_KIND_Msk

Endpoint Kind

◆ USB_EP6R_EP_KIND_Msk

#define USB_EP6R_EP_KIND_Msk   (0x1U << USB_EP6R_EP_KIND_Pos)

0x00000100

◆ USB_EP6R_EP_KIND_Pos

#define USB_EP6R_EP_KIND_Pos   (8U)

◆ USB_EP6R_EP_TYPE

#define USB_EP6R_EP_TYPE   USB_EP6R_EP_TYPE_Msk

EP_TYPE[1:0] bits (Endpoint type)

◆ USB_EP6R_EP_TYPE_0

#define USB_EP6R_EP_TYPE_0   (0x1U << USB_EP6R_EP_TYPE_Pos)

0x00000200

◆ USB_EP6R_EP_TYPE_1

#define USB_EP6R_EP_TYPE_1   (0x2U << USB_EP6R_EP_TYPE_Pos)

0x00000400

◆ USB_EP6R_EP_TYPE_Msk

#define USB_EP6R_EP_TYPE_Msk   (0x3U << USB_EP6R_EP_TYPE_Pos)

0x00000600

◆ USB_EP6R_EP_TYPE_Pos

#define USB_EP6R_EP_TYPE_Pos   (9U)

◆ USB_EP6R_SETUP

#define USB_EP6R_SETUP   USB_EP6R_SETUP_Msk

Setup transaction completed

◆ USB_EP6R_SETUP_Msk

#define USB_EP6R_SETUP_Msk   (0x1U << USB_EP6R_SETUP_Pos)

0x00000800

◆ USB_EP6R_SETUP_Pos

#define USB_EP6R_SETUP_Pos   (11U)

◆ USB_EP6R_STAT_RX

#define USB_EP6R_STAT_RX   USB_EP6R_STAT_RX_Msk

STAT_RX[1:0] bits (Status bits, for reception transfers)

◆ USB_EP6R_STAT_RX_0

#define USB_EP6R_STAT_RX_0   (0x1U << USB_EP6R_STAT_RX_Pos)

0x00001000

◆ USB_EP6R_STAT_RX_1

#define USB_EP6R_STAT_RX_1   (0x2U << USB_EP6R_STAT_RX_Pos)

0x00002000

◆ USB_EP6R_STAT_RX_Msk

#define USB_EP6R_STAT_RX_Msk   (0x3U << USB_EP6R_STAT_RX_Pos)

0x00003000

◆ USB_EP6R_STAT_RX_Pos

#define USB_EP6R_STAT_RX_Pos   (12U)

◆ USB_EP6R_STAT_TX

#define USB_EP6R_STAT_TX   USB_EP6R_STAT_TX_Msk

STAT_TX[1:0] bits (Status bits, for transmission transfers)

◆ USB_EP6R_STAT_TX_0

#define USB_EP6R_STAT_TX_0   (0x1U << USB_EP6R_STAT_TX_Pos)

0x00000010

◆ USB_EP6R_STAT_TX_1

#define USB_EP6R_STAT_TX_1   (0x2U << USB_EP6R_STAT_TX_Pos)

0x00000020

◆ USB_EP6R_STAT_TX_Msk

#define USB_EP6R_STAT_TX_Msk   (0x3U << USB_EP6R_STAT_TX_Pos)

0x00000030

◆ USB_EP6R_STAT_TX_Pos

#define USB_EP6R_STAT_TX_Pos   (4U)

◆ USB_EP7R

#define USB_EP7R   (USB_BASE + 0x0000001CU)

endpoint 7 register address

◆ USB_EP7R_CTR_RX

#define USB_EP7R_CTR_RX   USB_EP7R_CTR_RX_Msk

Correct Transfer for reception Common registers

◆ USB_EP7R_CTR_RX_Msk

#define USB_EP7R_CTR_RX_Msk   (0x1U << USB_EP7R_CTR_RX_Pos)

0x00008000

◆ USB_EP7R_CTR_RX_Pos

#define USB_EP7R_CTR_RX_Pos   (15U)

◆ USB_EP7R_CTR_TX

#define USB_EP7R_CTR_TX   USB_EP7R_CTR_TX_Msk

Correct Transfer for transmission

◆ USB_EP7R_CTR_TX_Msk

#define USB_EP7R_CTR_TX_Msk   (0x1U << USB_EP7R_CTR_TX_Pos)

0x00000080

◆ USB_EP7R_CTR_TX_Pos

#define USB_EP7R_CTR_TX_Pos   (7U)

◆ USB_EP7R_DTOG_RX

#define USB_EP7R_DTOG_RX   USB_EP7R_DTOG_RX_Msk

Data Toggle, for reception transfers

◆ USB_EP7R_DTOG_RX_Msk

#define USB_EP7R_DTOG_RX_Msk   (0x1U << USB_EP7R_DTOG_RX_Pos)

0x00004000

◆ USB_EP7R_DTOG_RX_Pos

#define USB_EP7R_DTOG_RX_Pos   (14U)

◆ USB_EP7R_DTOG_TX

#define USB_EP7R_DTOG_TX   USB_EP7R_DTOG_TX_Msk

Data Toggle, for transmission transfers

◆ USB_EP7R_DTOG_TX_Msk

#define USB_EP7R_DTOG_TX_Msk   (0x1U << USB_EP7R_DTOG_TX_Pos)

0x00000040

◆ USB_EP7R_DTOG_TX_Pos

#define USB_EP7R_DTOG_TX_Pos   (6U)

◆ USB_EP7R_EA

#define USB_EP7R_EA   USB_EP7R_EA_Msk

Endpoint Address

◆ USB_EP7R_EA_Msk

#define USB_EP7R_EA_Msk   (0xFU << USB_EP7R_EA_Pos)

0x0000000F

◆ USB_EP7R_EA_Pos

#define USB_EP7R_EA_Pos   (0U)

◆ USB_EP7R_EP_KIND

#define USB_EP7R_EP_KIND   USB_EP7R_EP_KIND_Msk

Endpoint Kind

◆ USB_EP7R_EP_KIND_Msk

#define USB_EP7R_EP_KIND_Msk   (0x1U << USB_EP7R_EP_KIND_Pos)

0x00000100

◆ USB_EP7R_EP_KIND_Pos

#define USB_EP7R_EP_KIND_Pos   (8U)

◆ USB_EP7R_EP_TYPE

#define USB_EP7R_EP_TYPE   USB_EP7R_EP_TYPE_Msk

EP_TYPE[1:0] bits (Endpoint type)

◆ USB_EP7R_EP_TYPE_0

#define USB_EP7R_EP_TYPE_0   (0x1U << USB_EP7R_EP_TYPE_Pos)

0x00000200

◆ USB_EP7R_EP_TYPE_1

#define USB_EP7R_EP_TYPE_1   (0x2U << USB_EP7R_EP_TYPE_Pos)

0x00000400

◆ USB_EP7R_EP_TYPE_Msk

#define USB_EP7R_EP_TYPE_Msk   (0x3U << USB_EP7R_EP_TYPE_Pos)

0x00000600

◆ USB_EP7R_EP_TYPE_Pos

#define USB_EP7R_EP_TYPE_Pos   (9U)

◆ USB_EP7R_SETUP

#define USB_EP7R_SETUP   USB_EP7R_SETUP_Msk

Setup transaction completed

◆ USB_EP7R_SETUP_Msk

#define USB_EP7R_SETUP_Msk   (0x1U << USB_EP7R_SETUP_Pos)

0x00000800

◆ USB_EP7R_SETUP_Pos

#define USB_EP7R_SETUP_Pos   (11U)

◆ USB_EP7R_STAT_RX

#define USB_EP7R_STAT_RX   USB_EP7R_STAT_RX_Msk

STAT_RX[1:0] bits (Status bits, for reception transfers)

◆ USB_EP7R_STAT_RX_0

#define USB_EP7R_STAT_RX_0   (0x1U << USB_EP7R_STAT_RX_Pos)

0x00001000

◆ USB_EP7R_STAT_RX_1

#define USB_EP7R_STAT_RX_1   (0x2U << USB_EP7R_STAT_RX_Pos)

0x00002000

◆ USB_EP7R_STAT_RX_Msk

#define USB_EP7R_STAT_RX_Msk   (0x3U << USB_EP7R_STAT_RX_Pos)

0x00003000

◆ USB_EP7R_STAT_RX_Pos

#define USB_EP7R_STAT_RX_Pos   (12U)

◆ USB_EP7R_STAT_TX

#define USB_EP7R_STAT_TX   USB_EP7R_STAT_TX_Msk

STAT_TX[1:0] bits (Status bits, for transmission transfers)

◆ USB_EP7R_STAT_TX_0

#define USB_EP7R_STAT_TX_0   (0x1U << USB_EP7R_STAT_TX_Pos)

0x00000010

◆ USB_EP7R_STAT_TX_1

#define USB_EP7R_STAT_TX_1   (0x2U << USB_EP7R_STAT_TX_Pos)

0x00000020

◆ USB_EP7R_STAT_TX_Msk

#define USB_EP7R_STAT_TX_Msk   (0x3U << USB_EP7R_STAT_TX_Pos)

0x00000030

◆ USB_EP7R_STAT_TX_Pos

#define USB_EP7R_STAT_TX_Pos   (4U)

◆ USB_EP_BULK

#define USB_EP_BULK   (0x00000000U)

EndPoint BULK

◆ USB_EP_CONTROL

#define USB_EP_CONTROL   (0x00000200U)

EndPoint CONTROL

◆ USB_EP_CTR_RX

#define USB_EP_CTR_RX   USB_EP_CTR_RX_Msk

EndPoint Correct TRansfer RX

◆ USB_EP_CTR_RX_Msk

#define USB_EP_CTR_RX_Msk   (0x1U << USB_EP_CTR_RX_Pos)

0x00008000

◆ USB_EP_CTR_RX_Pos

#define USB_EP_CTR_RX_Pos   (15U)

◆ USB_EP_CTR_TX

#define USB_EP_CTR_TX   USB_EP_CTR_TX_Msk

EndPoint Correct TRansfer TX

◆ USB_EP_CTR_TX_Msk

#define USB_EP_CTR_TX_Msk   (0x1U << USB_EP_CTR_TX_Pos)

0x00000080

◆ USB_EP_CTR_TX_Pos

#define USB_EP_CTR_TX_Pos   (7U)

◆ USB_EP_DTOG_RX

#define USB_EP_DTOG_RX   USB_EP_DTOG_RX_Msk

EndPoint Data TOGGLE RX

◆ USB_EP_DTOG_RX_Msk

#define USB_EP_DTOG_RX_Msk   (0x1U << USB_EP_DTOG_RX_Pos)

0x00004000

◆ USB_EP_DTOG_RX_Pos

#define USB_EP_DTOG_RX_Pos   (14U)

◆ USB_EP_DTOG_TX

#define USB_EP_DTOG_TX   USB_EP_DTOG_TX_Msk

EndPoint Data TOGGLE TX

◆ USB_EP_DTOG_TX_Msk

#define USB_EP_DTOG_TX_Msk   (0x1U << USB_EP_DTOG_TX_Pos)

0x00000040

◆ USB_EP_DTOG_TX_Pos

#define USB_EP_DTOG_TX_Pos   (6U)

◆ USB_EP_INTERRUPT

#define USB_EP_INTERRUPT   (0x00000600U)

EndPoint INTERRUPT

◆ USB_EP_ISOCHRONOUS

#define USB_EP_ISOCHRONOUS   (0x00000400U)

EndPoint ISOCHRONOUS

◆ USB_EP_KIND

#define USB_EP_KIND   USB_EP_KIND_Msk

EndPoint KIND

◆ USB_EP_KIND_Msk

#define USB_EP_KIND_Msk   (0x1U << USB_EP_KIND_Pos)

0x00000100

◆ USB_EP_KIND_Pos

#define USB_EP_KIND_Pos   (8U)

◆ USB_EP_RX_DIS

#define USB_EP_RX_DIS   (0x00000000U)

EndPoint RX DISabled

◆ USB_EP_RX_NAK

#define USB_EP_RX_NAK   (0x00002000U)

EndPoint RX NAKed

◆ USB_EP_RX_STALL

#define USB_EP_RX_STALL   (0x00001000U)

EndPoint RX STALLed

◆ USB_EP_RX_VALID

#define USB_EP_RX_VALID   (0x00003000U)

EndPoint RX VALID

◆ USB_EP_SETUP

#define USB_EP_SETUP   USB_EP_SETUP_Msk

EndPoint SETUP

◆ USB_EP_SETUP_Msk

#define USB_EP_SETUP_Msk   (0x1U << USB_EP_SETUP_Pos)

0x00000800

◆ USB_EP_SETUP_Pos

#define USB_EP_SETUP_Pos   (11U)

◆ USB_EP_T_FIELD

#define USB_EP_T_FIELD   USB_EP_T_FIELD_Msk

EndPoint TYPE

◆ USB_EP_T_FIELD_Msk

#define USB_EP_T_FIELD_Msk   (0x3U << USB_EP_T_FIELD_Pos)

0x00000600

◆ USB_EP_T_FIELD_Pos

#define USB_EP_T_FIELD_Pos   (9U)

◆ USB_EP_T_MASK

#define USB_EP_T_MASK   (~USB_EP_T_FIELD & USB_EPREG_MASK)

◆ USB_EP_TX_DIS

#define USB_EP_TX_DIS   (0x00000000U)

EndPoint TX DISabled

◆ USB_EP_TX_NAK

#define USB_EP_TX_NAK   (0x00000020U)

EndPoint TX NAKed

◆ USB_EP_TX_STALL

#define USB_EP_TX_STALL   (0x00000010U)

EndPoint TX STALLed

◆ USB_EP_TX_VALID

#define USB_EP_TX_VALID   (0x00000030U)

EndPoint TX VALID

◆ USB_EP_TYPE_MASK

#define USB_EP_TYPE_MASK   USB_EP_TYPE_MASK_Msk

EndPoint TYPE Mask

◆ USB_EP_TYPE_MASK_Msk

#define USB_EP_TYPE_MASK_Msk   (0x3U << USB_EP_TYPE_MASK_Pos)

0x00000600

◆ USB_EP_TYPE_MASK_Pos

#define USB_EP_TYPE_MASK_Pos   (9U)

◆ USB_EPADDR_FIELD

#define USB_EPADDR_FIELD   USB_EPADDR_FIELD_Msk

EndPoint ADDRess FIELD

◆ USB_EPADDR_FIELD_Msk

#define USB_EPADDR_FIELD_Msk   (0xFU << USB_EPADDR_FIELD_Pos)

0x0000000F

◆ USB_EPADDR_FIELD_Pos

#define USB_EPADDR_FIELD_Pos   (0U)

◆ USB_EPKIND_MASK

#define USB_EPKIND_MASK   (~USB_EP_KIND & USB_EPREG_MASK)

EP_KIND EndPoint KIND STAT_TX[1:0] STATus for TX transfer

◆ USB_EPREG_MASK

#define USB_EPREG_MASK   (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)

EP_TYPE[1:0] EndPoint TYPE

◆ USB_EPRX_DTOG1

#define USB_EPRX_DTOG1   (0x00001000U)

EndPoint RX Data TOGgle bit1

◆ USB_EPRX_DTOG2

#define USB_EPRX_DTOG2   (0x00002000U)

EndPoint RX Data TOGgle bit1

◆ USB_EPRX_DTOGMASK

#define USB_EPRX_DTOGMASK   (USB_EPRX_STAT|USB_EPREG_MASK)

◆ USB_EPRX_STAT

#define USB_EPRX_STAT   USB_EPRX_STAT_Msk

EndPoint RX STATus bit field

◆ USB_EPRX_STAT_Msk

#define USB_EPRX_STAT_Msk   (0x3U << USB_EPRX_STAT_Pos)

0x00003000

◆ USB_EPRX_STAT_Pos

#define USB_EPRX_STAT_Pos   (12U)

◆ USB_EPTX_DTOG1

#define USB_EPTX_DTOG1   (0x00000010U)

EndPoint TX Data TOGgle bit1

◆ USB_EPTX_DTOG2

#define USB_EPTX_DTOG2   (0x00000020U)

EndPoint TX Data TOGgle bit2

◆ USB_EPTX_DTOGMASK

#define USB_EPTX_DTOGMASK   (USB_EPTX_STAT|USB_EPREG_MASK)

STAT_RX[1:0] STATus for RX transfer

◆ USB_EPTX_STAT

#define USB_EPTX_STAT   USB_EPTX_STAT_Msk

EndPoint TX STATus bit field

◆ USB_EPTX_STAT_Msk

#define USB_EPTX_STAT_Msk   (0x3U << USB_EPTX_STAT_Pos)

0x00000030

◆ USB_EPTX_STAT_Pos

#define USB_EPTX_STAT_Pos   (4U)

◆ USB_FNR

#define USB_FNR   (USB_BASE + 0x00000048U)

Frame number register

◆ USB_FNR_FN

#define USB_FNR_FN   USB_FNR_FN_Msk

Frame Number

◆ USB_FNR_FN_Msk

#define USB_FNR_FN_Msk   (0x7FFU << USB_FNR_FN_Pos)

0x000007FF

◆ USB_FNR_FN_Pos

#define USB_FNR_FN_Pos   (0U)

◆ USB_FNR_LCK

#define USB_FNR_LCK   USB_FNR_LCK_Msk

Locked

◆ USB_FNR_LCK_Msk

#define USB_FNR_LCK_Msk   (0x1U << USB_FNR_LCK_Pos)

0x00002000

◆ USB_FNR_LCK_Pos

#define USB_FNR_LCK_Pos   (13U)

◆ USB_FNR_LSOF

#define USB_FNR_LSOF   USB_FNR_LSOF_Msk

Lost SOF

◆ USB_FNR_LSOF_Msk

#define USB_FNR_LSOF_Msk   (0x3U << USB_FNR_LSOF_Pos)

0x00001800

◆ USB_FNR_LSOF_Pos

#define USB_FNR_LSOF_Pos   (11U)

◆ USB_FNR_RXDM

#define USB_FNR_RXDM   USB_FNR_RXDM_Msk

Receive Data - Line Status

◆ USB_FNR_RXDM_Msk

#define USB_FNR_RXDM_Msk   (0x1U << USB_FNR_RXDM_Pos)

0x00004000

◆ USB_FNR_RXDM_Pos

#define USB_FNR_RXDM_Pos   (14U)

◆ USB_FNR_RXDP

#define USB_FNR_RXDP   USB_FNR_RXDP_Msk

Receive Data + Line Status

◆ USB_FNR_RXDP_Msk

#define USB_FNR_RXDP_Msk   (0x1U << USB_FNR_RXDP_Pos)

0x00008000

◆ USB_FNR_RXDP_Pos

#define USB_FNR_RXDP_Pos   (15U)

◆ USB_ISTR

#define USB_ISTR   (USB_BASE + 0x00000044U)

Interrupt status register

◆ USB_ISTR_CTR

#define USB_ISTR_CTR   USB_ISTR_CTR_Msk

Correct Transfer

◆ USB_ISTR_CTR_Msk

#define USB_ISTR_CTR_Msk   (0x1U << USB_ISTR_CTR_Pos)

0x00008000

◆ USB_ISTR_CTR_Pos

#define USB_ISTR_CTR_Pos   (15U)

◆ USB_ISTR_DIR

#define USB_ISTR_DIR   USB_ISTR_DIR_Msk

Direction of transaction

◆ USB_ISTR_DIR_Msk

#define USB_ISTR_DIR_Msk   (0x1U << USB_ISTR_DIR_Pos)

0x00000010

◆ USB_ISTR_DIR_Pos

#define USB_ISTR_DIR_Pos   (4U)

◆ USB_ISTR_EP_ID

#define USB_ISTR_EP_ID   USB_ISTR_EP_ID_Msk

Endpoint Identifier

◆ USB_ISTR_EP_ID_Msk

#define USB_ISTR_EP_ID_Msk   (0xFU << USB_ISTR_EP_ID_Pos)

0x0000000F

◆ USB_ISTR_EP_ID_Pos

#define USB_ISTR_EP_ID_Pos   (0U)

◆ USB_ISTR_ERR

#define USB_ISTR_ERR   USB_ISTR_ERR_Msk

Error

◆ USB_ISTR_ERR_Msk

#define USB_ISTR_ERR_Msk   (0x1U << USB_ISTR_ERR_Pos)

0x00002000

◆ USB_ISTR_ERR_Pos

#define USB_ISTR_ERR_Pos   (13U)

◆ USB_ISTR_ESOF

#define USB_ISTR_ESOF   USB_ISTR_ESOF_Msk

Expected Start Of Frame

◆ USB_ISTR_ESOF_Msk

#define USB_ISTR_ESOF_Msk   (0x1U << USB_ISTR_ESOF_Pos)

0x00000100

◆ USB_ISTR_ESOF_Pos

#define USB_ISTR_ESOF_Pos   (8U)

◆ USB_ISTR_PMAOVR

#define USB_ISTR_PMAOVR   USB_ISTR_PMAOVR_Msk

Packet Memory Area Over / Underrun

◆ USB_ISTR_PMAOVR_Msk

#define USB_ISTR_PMAOVR_Msk   (0x1U << USB_ISTR_PMAOVR_Pos)

0x00004000

◆ USB_ISTR_PMAOVR_Pos

#define USB_ISTR_PMAOVR_Pos   (14U)

◆ USB_ISTR_RESET

#define USB_ISTR_RESET   USB_ISTR_RESET_Msk

USB RESET request

◆ USB_ISTR_RESET_Msk

#define USB_ISTR_RESET_Msk   (0x1U << USB_ISTR_RESET_Pos)

0x00000400

◆ USB_ISTR_RESET_Pos

#define USB_ISTR_RESET_Pos   (10U)

◆ USB_ISTR_SOF

#define USB_ISTR_SOF   USB_ISTR_SOF_Msk

Start Of Frame

◆ USB_ISTR_SOF_Msk

#define USB_ISTR_SOF_Msk   (0x1U << USB_ISTR_SOF_Pos)

0x00000200

◆ USB_ISTR_SOF_Pos

#define USB_ISTR_SOF_Pos   (9U)

◆ USB_ISTR_SUSP

#define USB_ISTR_SUSP   USB_ISTR_SUSP_Msk

Suspend mode request

◆ USB_ISTR_SUSP_Msk

#define USB_ISTR_SUSP_Msk   (0x1U << USB_ISTR_SUSP_Pos)

0x00000800

◆ USB_ISTR_SUSP_Pos

#define USB_ISTR_SUSP_Pos   (11U)

◆ USB_ISTR_WKUP

#define USB_ISTR_WKUP   USB_ISTR_WKUP_Msk

Wake up

◆ USB_ISTR_WKUP_Msk

#define USB_ISTR_WKUP_Msk   (0x1U << USB_ISTR_WKUP_Pos)

0x00001000

◆ USB_ISTR_WKUP_Pos

#define USB_ISTR_WKUP_Pos   (12U)

◆ WWDG_CFR_EWI

#define WWDG_CFR_EWI   WWDG_CFR_EWI_Msk

Early Wakeup Interrupt

◆ WWDG_CFR_EWI_Msk

#define WWDG_CFR_EWI_Msk   (0x1U << WWDG_CFR_EWI_Pos)

0x00000200

◆ WWDG_CFR_EWI_Pos

#define WWDG_CFR_EWI_Pos   (9U)

◆ WWDG_CFR_W

#define WWDG_CFR_W   WWDG_CFR_W_Msk

W[6:0] bits (7-bit window value)

◆ WWDG_CFR_W0

#define WWDG_CFR_W0   WWDG_CFR_W_0

◆ WWDG_CFR_W1

#define WWDG_CFR_W1   WWDG_CFR_W_1

◆ WWDG_CFR_W2

#define WWDG_CFR_W2   WWDG_CFR_W_2

◆ WWDG_CFR_W3

#define WWDG_CFR_W3   WWDG_CFR_W_3

◆ WWDG_CFR_W4

#define WWDG_CFR_W4   WWDG_CFR_W_4

◆ WWDG_CFR_W5

#define WWDG_CFR_W5   WWDG_CFR_W_5

◆ WWDG_CFR_W6

#define WWDG_CFR_W6   WWDG_CFR_W_6

◆ WWDG_CFR_W_0

#define WWDG_CFR_W_0   (0x01U << WWDG_CFR_W_Pos)

0x00000001

◆ WWDG_CFR_W_1

#define WWDG_CFR_W_1   (0x02U << WWDG_CFR_W_Pos)

0x00000002

◆ WWDG_CFR_W_2

#define WWDG_CFR_W_2   (0x04U << WWDG_CFR_W_Pos)

0x00000004

◆ WWDG_CFR_W_3

#define WWDG_CFR_W_3   (0x08U << WWDG_CFR_W_Pos)

0x00000008

◆ WWDG_CFR_W_4

#define WWDG_CFR_W_4   (0x10U << WWDG_CFR_W_Pos)

0x00000010

◆ WWDG_CFR_W_5

#define WWDG_CFR_W_5   (0x20U << WWDG_CFR_W_Pos)

0x00000020

◆ WWDG_CFR_W_6

#define WWDG_CFR_W_6   (0x40U << WWDG_CFR_W_Pos)

0x00000040

◆ WWDG_CFR_W_Msk

#define WWDG_CFR_W_Msk   (0x7FU << WWDG_CFR_W_Pos)

0x0000007F

◆ WWDG_CFR_W_Pos

#define WWDG_CFR_W_Pos   (0U)

◆ WWDG_CFR_WDGTB

#define WWDG_CFR_WDGTB   WWDG_CFR_WDGTB_Msk

WDGTB[1:0] bits (Timer Base)

◆ WWDG_CFR_WDGTB0

#define WWDG_CFR_WDGTB0   WWDG_CFR_WDGTB_0

◆ WWDG_CFR_WDGTB1

#define WWDG_CFR_WDGTB1   WWDG_CFR_WDGTB_1

◆ WWDG_CFR_WDGTB_0

#define WWDG_CFR_WDGTB_0   (0x1U << WWDG_CFR_WDGTB_Pos)

0x00000080

◆ WWDG_CFR_WDGTB_1

#define WWDG_CFR_WDGTB_1   (0x2U << WWDG_CFR_WDGTB_Pos)

0x00000100

◆ WWDG_CFR_WDGTB_Msk

#define WWDG_CFR_WDGTB_Msk   (0x3U << WWDG_CFR_WDGTB_Pos)

0x00000180

◆ WWDG_CFR_WDGTB_Pos

#define WWDG_CFR_WDGTB_Pos   (7U)

◆ WWDG_CR_T

#define WWDG_CR_T   WWDG_CR_T_Msk

T[6:0] bits (7-Bit counter (MSB to LSB))

◆ WWDG_CR_T0

#define WWDG_CR_T0   WWDG_CR_T_0

◆ WWDG_CR_T1

#define WWDG_CR_T1   WWDG_CR_T_1

◆ WWDG_CR_T2

#define WWDG_CR_T2   WWDG_CR_T_2

◆ WWDG_CR_T3

#define WWDG_CR_T3   WWDG_CR_T_3

◆ WWDG_CR_T4

#define WWDG_CR_T4   WWDG_CR_T_4

◆ WWDG_CR_T5

#define WWDG_CR_T5   WWDG_CR_T_5

◆ WWDG_CR_T6

#define WWDG_CR_T6   WWDG_CR_T_6

◆ WWDG_CR_T_0

#define WWDG_CR_T_0   (0x01U << WWDG_CR_T_Pos)

0x00000001

◆ WWDG_CR_T_1

#define WWDG_CR_T_1   (0x02U << WWDG_CR_T_Pos)

0x00000002

◆ WWDG_CR_T_2

#define WWDG_CR_T_2   (0x04U << WWDG_CR_T_Pos)

0x00000004

◆ WWDG_CR_T_3

#define WWDG_CR_T_3   (0x08U << WWDG_CR_T_Pos)

0x00000008

◆ WWDG_CR_T_4

#define WWDG_CR_T_4   (0x10U << WWDG_CR_T_Pos)

0x00000010

◆ WWDG_CR_T_5

#define WWDG_CR_T_5   (0x20U << WWDG_CR_T_Pos)

0x00000020

◆ WWDG_CR_T_6

#define WWDG_CR_T_6   (0x40U << WWDG_CR_T_Pos)

0x00000040

◆ WWDG_CR_T_Msk

#define WWDG_CR_T_Msk   (0x7FU << WWDG_CR_T_Pos)

0x0000007F

◆ WWDG_CR_T_Pos

#define WWDG_CR_T_Pos   (0U)

◆ WWDG_CR_WDGA

#define WWDG_CR_WDGA   WWDG_CR_WDGA_Msk

Activation bit

◆ WWDG_CR_WDGA_Msk

#define WWDG_CR_WDGA_Msk   (0x1U << WWDG_CR_WDGA_Pos)

0x00000080

◆ WWDG_CR_WDGA_Pos

#define WWDG_CR_WDGA_Pos   (7U)

◆ WWDG_SR_EWIF

#define WWDG_SR_EWIF   WWDG_SR_EWIF_Msk

Early Wakeup Interrupt Flag

◆ WWDG_SR_EWIF_Msk

#define WWDG_SR_EWIF_Msk   (0x1U << WWDG_SR_EWIF_Pos)

0x00000001

◆ WWDG_SR_EWIF_Pos

#define WWDG_SR_EWIF_Pos   (0U)
Generated by   doxygen 1.8.14